SONIX SN32F280 Series Manual de usuario

SN32F280 Series

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 1 Version 1.1

SN32F280 Series

USER’S MANUAL

SN32F289

SN32F288

SN32F287

SONiX 32-Bit Cortex-M0 Micro-Controller

SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not

assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent

rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product

could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or

unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against

all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the

part.

SN32F280 Series

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 2 Version 1.1

AMENDENT HISTORY

Version

Date

Description

1.0

2020/03/25

First version released.

1.1

2020/06/01

1. Fix typing errors.

2. Update the CMP and OPA block diagram.

3. Add I2C0PRE and I2C1PRE bits in 3.4.3 SYS1_APBCP1 register.

4. Fix 3.3V Regulator Output voltage.

SN32F280 Series

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 3 Version 1.1

Table of Content

AMENDENT HISTORY................................................................................................................................ 2

PRODUCT OVERVIEW....................................................................................................................... 16

1.1 FEATURES...................................................................................................................................... 16

1.2 SYSTEM BLOCK DIAGRAM........................................................................................................ 18

1.3 CLOCK GENERATION BLOCK DIAGRAM................................................................................ 19

1.4 PIN ASSIGNMENT......................................................................................................................... 20

1.5 PIN ALLOCATION TABLE............................................................................................................ 23

1.6 PIN DESCRIPTIONS....................................................................................................................... 26

1.7 PIN CIRCUIT DIAGRAMS............................................................................................................. 34

1.8 PIN CHARACTERISTICS............................................................................................................... 36

CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 38

2.1 MEMORY MAP............................................................................................................................... 38

2.2 SYSTEM TICK TIMER................................................................................................................... 39

2.2.1 OPERATION ............................................................................................................................ 39

2.2.2 SYSTICK USAGE HINTS AND TIPS ....................................................................................... 40

2.2.3 SYSTICK REGISTERS.............................................................................................................. 40

2.2.3.1 System Tick Timer Control and Status register (SYSTICK_CTRL)................................... 40

2.2.3.2 System Tick Timer Reload value register (SYSTICK_LOAD)........................................... 40

2.2.3.3 System Tick Timer Current Value register (SYSTICK_VAL)............................................ 41

2.2.3.4 System Tick Timer Calibration Value register (SYSTICK_CALIB) .................................. 41

2.3 NESTED VECTORED INTERRUPT CONTROLLER (NVIC) ..................................................... 42

2.3.1 INTERRUPT AND EXCEPTION VECTORS ........................................................................... 42

2.3.2 NVIC REGISTERS.................................................................................................................... 43

2.3.2.1 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER)....................................................... 43

2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER)................................................... 43

2.3.2.3 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR) ..................................................... 44

2.3.2.4 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR) ................................................. 44

2.3.2.5 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7)............................................... 44

2.4 APPLICATION INTERRUPT AND RESET CONTROL (AIRC).................................................. 45

2.5 CODE OPTION TABLE.................................................................................................................. 46

2.6 UNIQUE NUMBER......................................................................................................................... 46

2.7 CORE REGISTER OVERVIEW ..................................................................................................... 47

SYSTEM CONTROL............................................................................................................................. 48

3.1 RESET.............................................................................................................................................. 48

3.1.1 POWER-ON RESET (POR)...................................................................................................... 48

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32-Bit Cortex-M0 Micro-Controller

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3.1.2 WATCHDOG RESET (WDT RESET)....................................................................................... 49

3.1.3 BROWN-OUT RESET............................................................................................................... 49

3.1.3.1 BROWN OUT DESCRIPTION........................................................................................... 49

3.1.3.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION............................................... 50

3.1.3.3 BROWN-OUT RESET IMPROVEMENT.......................................................................... 50

3.1.4 EXTERNAL RESET .................................................................................................................. 51

3.1.4.1 SIMPLY RC RESET CIRCUIT........................................................................................... 52

3.1.4.2 DIODE & RC RESET CIRCUIT......................................................................................... 52

3.1.4.3 ZENER DIODE RESET CIRCUIT...................................................................................... 53

3.1.4.4 VOLTAGE BIAS RESET CIRCUIT................................................................................... 53

3.1.4.5 EXTERNAL RESET IC....................................................................................................... 54

3.1.5 SOFTWARE RESET ................................................................................................................. 54

3.2 SYSTEM CLOCK............................................................................................................................ 55

3.2.1 INTERNAL RC CLOCK SOURCE ........................................................................................... 55

3.2.1.1 Internal High-speed RC Oscillator (IHRC).......................................................................... 55

3.2.1.2 Internal Low-speed RC Oscillator (ILRC)........................................................................... 55

3.2.2 PLL ........................................................................................................................................... 56

3.2.2.1 PLL Frequency selection...................................................................................................... 56

3.2.3 EXTERNAL CLOCK SOURCE ................................................................................................ 57

3.2.3.1 External High-speed (EHS) Clock ....................................................................................... 57

3.2.3.2 CRYSTAL/CERAMIC......................................................................................................... 57

3.2.3.3 External Low-speed (ELS) Clock......................................................................................... 58

3.2.3.4 CRYSTAL............................................................................................................................ 58

3.2.3.5 Bypass Mode ........................................................................................................................ 59

3.2.4 SYSTEM CLOCK (SYSCLK) SELECTION............................................................................... 59

3.2.5 CLOCK-OUT CAPABITITY..................................................................................................... 59

3.3 SYSTEM CONTROL REGISTERS 0.............................................................................................. 60

3.3.1 Analog Block Control register (SYS0_ANBCTRL)................................................................... 60

3.3.2 PLL control register (SYS0_PLLCTRL)................................................................................... 60

3.3.2.1 RECOMMEND FREQUENCY SETTING.......................................................................... 61

3.3.3 Clock Source Status register (SYS0_CSST).............................................................................. 61

3.3.4 System Clock Configuration register (SYS0_CLKCFG).......................................................... 61

3.3.5 AHB Clock Prescale register (SYS0_AHBCP)......................................................................... 62

3.3.6 System Reset Status register (SYS0_RSTST) ............................................................................ 62

3.3.7 LVD Control register (SYS0_LVDCTRL)................................................................................. 63

3.3.8 External RESET Pin Control register (SYS0_EXRSTCTRL) ................................................... 63

3.3.9 SWD Pin Control register (SYS0_SWDCTRL)......................................................................... 64

3.3.10 Interrupt Vector Table Mapping register (SYS0_IVTM).......................................................... 64

3.3.11 Noise Detect Control register (SYS0_NDTCTRL).................................................................... 64

3.3.12 Noise Detect Status register (SYS0_NDTSTS).......................................................................... 65

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32-Bit Cortex-M0 Micro-Controller

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3.3.13 Anti-EFT Ability Control register (SYS0_ANTIEFT)............................................................... 65

3.3.14 IHRC Frequency Adjustment register (SYS0_IHRCADJ)........................................................ 65

3.4 SYSTEM CONTROL REGISTERS 1.............................................................................................. 66

3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN).................................................................... 66

3.4.2 APB Clock Prescale register 0 (SYS1_APBCP0)..................................................................... 67

3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1)..................................................................... 68

3.4.4 Peripheral Reset register (SYS1_PRST)................................................................................... 69

SYSTEM OPERATION MODE........................................................................................................... 71

4.1 OVERVIEW..................................................................................................................................... 71

4.2 NORMAL MODE ............................................................................................................................ 71

4.3 LOW-POWER MODES................................................................................................................... 71

4.3.1 SLEEP MODE.......................................................................................................................... 71

4.3.2 DEEP-SLEEP MODE............................................................................................................... 72

4.4 WAKEUP......................................................................................................................................... 73

4.4.1 OVERVIEW .............................................................................................................................. 73

4.4.2 WAKEUP TIME........................................................................................................................ 73

4.5 STATE MACHINE OF PMU........................................................................................................... 74

4.6 OPERATION MODE COMPARSION TABLE .............................................................................. 75

4.7 PMU REGISTERS ........................................................................................................................... 76

4.7.1 Power Control register (PMU_CTRL)..................................................................................... 76

GENERAL PURPOSE I/O PORT (GPIO).......................................................................................... 77

5.1 OVERVIEW..................................................................................................................................... 77

5.2 GPIO MODE .................................................................................................................................... 77

5.3 GPIO REGISTERS........................................................................................................................... 78

5.3.1 GPIO Port n Data register (GPIOn_DATA) (n=0,1,2,3)......................................................... 78

5.3.2 GPIO Port n Mode register (GPIOn_MODE) (n=0,1,2,3)...................................................... 78

5.3.3 GPIO Port n Configuration register (GPIOn_CFG) (n=0,1,2,3)............................................ 78

5.3.4 GPIO Port n Interrupt Sense register (GPIOn_IS) (n=0,1,2,3)............................................... 80

5.3.5 GPIO Port n Interrupt Both-edge Sense register (GPIOn_IBS) (n=0,1,2,3)........................... 80

5.3.6 GPIO Port n Interrupt Event register (GPIOn_IEV) (n=0,1,2,3)............................................ 80

5.3.7 GPIO Port n Interrupt Enable register (GPIOn_IE) (n=0,1,2,3)............................................ 80

5.3.8 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3) ................................... 81

5.3.9 GPIO Port n Interrupt Clear register (GPIOn_IC) (n=0,1,2,3).............................................. 81

5.3.10 GPIO Port n Bits Set Operation register (GPIOn_BSET) (n=0,1,2,3).................................... 81

5.3.11 Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3) ......................................... 81

5.3.12 GPIO Port n Configuration register 1 (GPIOn_CFG1) (n=0,1,3).......................................... 82

PERIPHERAL FUNCTION PIN ASSIGNMENT (PFPA)................................................................ 83

6.1 OVERVIEW..................................................................................................................................... 83

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32-Bit Cortex-M0 Micro-Controller

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6.2 FEATURES...................................................................................................................................... 83

6.3 PIN ASSIGNMENT LIST................................................................................................................ 83

6.4 PFPA REGISTERS........................................................................................................................... 85

6.4.1 PFPA for CT16B0 register (PFPA_CT16B0).......................................................................... 85

6.4.2 PFPA for CT16B1 register (PFPA_CT16B1).......................................................................... 85

6.4.3 PFPA for UART register (PFPA_UART)................................................................................. 86

6.4.4 PFPA for I2S register (PFPA_I2C).......................................................................................... 87

6.4.5 PFPA for SPI register (PFPA_SPI) ......................................................................................... 87

6.4.6 PFPA for I2S register (PFPA_I2S).......................................................................................... 88

6.4.7 PFPA for CT16B2 register (PFPA_CT16B2).......................................................................... 89

6.4.8 PFPA for CT16B3 register (PFPA_CT16B3).......................................................................... 89

6.4.9 PFPA for CT16B4 register (PFPA_CT16B4).......................................................................... 90

6.4.10 PFPA for CT16B5 register (PFPA_CT16B5).......................................................................... 90

16+3 CHANNEL ANALOG TO DIGITAL CONVERTOR (ADC).................................................. 92

7.1 OVERVIEW..................................................................................................................................... 92

7.2 ADC CONVERTING TIME ............................................................................................................ 93

7.3 ADC CONTROL NOTICE............................................................................................................... 94

7.3.1 ADC SIGNAL............................................................................................................................ 94

7.3.2 ADC PROGRAM ...................................................................................................................... 94

7.3.3 ADC PIN CONFIGURATION.................................................................................................. 94

7.4 ADC CIRCUIT................................................................................................................................. 95

7.5 ADC REGISTERS............................................................................................................................ 96

7.5.1 ADC Management register (ADC_ADM)................................................................................. 96

7.5.2 ADC Data register (ADC_ADB) .............................................................................................. 97

7.5.3 ADC Interrupt Enable register (ADC_IE)................................................................................ 97

7.5.4 ADC Raw Interrupt Status register (ADC_RIS)....................................................................... 98

RAIL TO RAIL ANALOG COMPARATOR ..................................................................................... 99

8.1 OVERVIEW..................................................................................................................................... 99

8.2 NORMAL COMPARATOR MODE.............................................................................................. 101

8.2.1 COMPARATOR ENABLE ...................................................................................................... 101

8.2.2 CMnOUT, CMnG AND CMnIF.............................................................................................. 102

8.2.3 COMPARATOR OUTPUT DEBOUNCE TIME CONTROL.................................................. 103

8.3 COMPARATOR APPLICATION NOTICE.................................................................................. 103

8.4 CMP REGISTERS.......................................................................................................................... 104

8.4.1 CMP Control register (CMP_CTRL)..................................................................................... 104

8.4.2 CMP Control register 1 (CMP_CTRL1)................................................................................ 105

8.4.3 CMP Internal Reference Voltage Source register (CMP_VIREF)......................................... 105

8.4.4 CMP Output Status register (CMP_OS) ................................................................................ 105

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32-Bit Cortex-M0 Micro-Controller

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8.4.5 CMP Interrupt Enable register (CMP_IE)............................................................................. 106

8.4.6 CMP Raw Interrupt Status register (CMP_RIS).................................................................... 106

8.4.7 CMP Interrupt Clear register (CMP_IC)............................................................................... 107

8.4.8 CMP Output Debounce register (CMP_DB).......................................................................... 107

OPERATIONAL-AMPLIFIER (OPA).............................................................................................. 108

9.1 OVERVIEW................................................................................................................................... 108

9.2 CONFIGURATION OF OPERATION.......................................................................................... 108

9.3 OPA REGISTERS.......................................................................................................................... 110

9.3.1 OPA Control register (OPA_CTRL)....................................................................................... 110

16-BIT TIMER WITH CAPTURE FUNCTION .......................................................................... 111

10.1 OVERVIEW................................................................................................................................... 111

10.2 FEATURES.................................................................................................................................... 111

10.3 PIN DESCRIPTION....................................................................................................................... 112

10.4 BLOCK DIAGRAM....................................................................................................................... 112

10.5 TIMER OPERATION .................................................................................................................... 113

10.5.1 Edge-aligned Up-counting Mode ........................................................................................... 113

10.5.2 Edge-aligned Down-counting Mode....................................................................................... 114

10.5.3 Center-aligned Counting Mode.............................................................................................. 114

10.6 PWM............................................................................................................................................... 115

10.6.1 PWM Mode 1.......................................................................................................................... 115

10.6.2 PWM Mode 2.......................................................................................................................... 116

10.8 CT16BN REGISTERS.................................................................................................................... 120

10.8.1 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=0,2) ........................................... 120

10.8.2 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=1,3,4) ........................................ 121

10.8.3 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=5) .............................................. 121

10.8.4 CT16Bn Timer Counter register (CT16Bn_TC) (n=0,1,2,3,4,5) ........................................... 122

10.8.5 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1,2,3,4,5)................................................... 122

10.8.6 CT16Bn Prescale Counter register (CT16Bn_PC) (n=0,1,2,3,4,5)....................................... 122

10.8.7 CT16Bn Count Control register (CT16Bn_CNTCTRL) (n=0,1,2,3,4,5)................................ 122

10.8.8 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0,2,5) ............................................ 123

10.8.9 CT16Bn Match Control register (CT16Bn_MCTRL) (n=3,4) ............................................... 124

10.8.10 CT16Bn Match Control register (CT16Bn_MCTRL) (n=1) .............................................. 125

10.8.11 CT16Bn Match Control register 2 (CT16Bn_MCTRL2) (n=1) ......................................... 127

10.8.12 CT16Bn Match register 0~1 (CT16Bn_MR0~1) (n=0,2,3,4,5).......................................... 128

10.8.13 CT16Bn Match register 2~3 (CT16Bn_MR2~3) (n=0,2,5)................................................ 128

10.8.14 CT16Bn Match register 9 (CT16Bn_MR9) (n=0,2,3,4,5).................................................. 128

10.8.15 CT16Bn Match register 0~11 (CT16Bn_MR0~11) (n=1).................................................. 128

10.8.16 CT16Bn Match register 12 (CT16Bn_MR12) (n=1).......................................................... 129

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32-Bit Cortex-M0 Micro-Controller

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10.8.17 CT16Bn Capture Control register (CT16Bn_CAPCTRL) (n=0,1,2,3,4,5) ........................ 129

10.8.18 CT16Bn Capture 0 register (CT16Bn_CAP0) (n=0,1,2,3,4,5) .......................................... 130

10.8.19 CT16Bn External Match register (CT16Bn_EM) (n=0,2,5) .............................................. 131

10.8.20 CT16Bn External Match register (CT16Bn_EM) (n=3,4) ................................................. 132

10.8.21 CT16Bn External Match register (CT16Bn_EM) (n=1) .................................................... 132

10.8.22 CT16Bn External Match Control register (CT16Bn_EMC) (n=1) .................................... 133

10.8.23 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=0,2,5).................................... 135

10.8.24 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=3,4)....................................... 136

10.8.25 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=1).......................................... 137

10.8.26 CT16Bn PWM Enable register (CT16Bn_PWMENB) (n=1)............................................. 138

10.8.27 CT16Bn PWM IO Enable register (CT16Bn_PWMIOENB) (n=1) ................................... 139

10.8.28 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=0,2,5) ........................... 140

10.8.29 T16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=3,4)................................. 141

10.8.30 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=1) ................................. 141

10.8.31 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=0,2,5)...................................... 142

10.8.32 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=1)............................................ 143

10.8.33 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=3,4)......................................... 143

10.8.34 CT16Bn PWMmN IO Control register (CT16Bn_PWMmNIOCTRL) (n=0) ..................... 144

10.8.35 CT16Bn PWMmN IO Control register (CT16Bn_PWMmNIOCTRL) (n=3,4) .................. 144

10.8.36 CT16Bn PWMmN Dead-band Period register (CT16Bn_PWMmNDB) (n=0).................. 145

10.8.37 CT16Bn PWMmN Dead-band Period register (CT16Bn_PWMmNDB) (n=3,4)............... 145

WATCHDOG TIMER (WDT)........................................................................................................ 146

11.1 OVERVIEW................................................................................................................................... 146

11.2 BLOCK DIAGRAM....................................................................................................................... 147

11.3 WDT REGISTERS......................................................................................................................... 148

11.3.1 Watchdog Configuration register (WDT_CFG)..................................................................... 148

11.3.2 Watchdog Timer Constant register (WDT_TC)...................................................................... 148

11.3.3 Watchdog Feed register (WDT_FEED)................................................................................. 149

REAL-TIME CLOCK (RTC) ......................................................................................................... 150

12.1 OVERVIEW................................................................................................................................... 150

12.2 FEATURES.................................................................................................................................... 150

12.3 FUNCTIONAL DESCRIPTION.................................................................................................... 150

12.3.1 INTRODUCTION................................................................................................................... 150

12.3.2 RESET RTC REGISTERS....................................................................................................... 150

12.3.3 RTC FLAG ASSERTION ........................................................................................................ 150

12.3.4 RTC OPERATION.................................................................................................................. 150

12.4 BLOCK DIAGRAM....................................................................................................................... 151

12.5 RTC REGISTERS .......................................................................................................................... 152

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32-Bit Cortex-M0 Micro-Controller

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12.5.1 RTC Control register (RTC_CTRL) ....................................................................................... 152

12.5.2 RTC Clock Source Select register (RTC_CLKS).................................................................... 152

12.5.3 RTC Interrupt Enable register (RTC_IE)............................................................................... 152

12.5.4 RTC Raw Interrupt Status register (RTC_RIS) ...................................................................... 152

12.5.5 RTC Interrupt Clear register (RTC_IC)................................................................................. 152

12.5.6 RTC Second Counter Reload Value register (RTC_SECCNTV)............................................ 153

12.5.7 RTC Second Count register (RTC_SECCNT) ........................................................................ 153

SPI...................................................................................................................................................... 154

13.1 OVERVIEW................................................................................................................................... 154

13.2 FEATURES.................................................................................................................................... 154

13.3 PIN DESCRIPTION....................................................................................................................... 154

13.4 INTERFACE DESCRIPTION ....................................................................................................... 155

13.4.1 SPI .......................................................................................................................................... 155

13.4.2 COMMUNICATION FLOW................................................................................................... 156

13.4.2.1 SINGLE-FRAME........................................................................................................... 156

13.4.2.2 MULTI-FRAME ............................................................................................................ 156

13.5 AUTO-SEL..................................................................................................................................... 156

13.6 SPI REGISTERS ............................................................................................................................ 157

13.6.1 SPI n Control register 0 (SPIn_CTRL0) (n=0,1)................................................................... 157

13.6.2 SPI n Control register 1 (SPIn_CTRL1) (n=0,1)................................................................... 158

13.6.3 SPI n Clock Divider register (SPIn_CLKDIV) (n=0,1) ......................................................... 158

13.6.4 SPI n Status register (SPIn_STAT) (n=0,1)............................................................................ 158

13.6.5 SPI n Interrupt Enable register (SPIn_IE) (n=0,1)................................................................ 159

13.6.6 SPI n Raw Interrupt Status register (SPIn_RIS) (n=0,1)....................................................... 159

13.6.7 SPI n Interrupt Clear register (SPIn_IC) (n=0,1).................................................................. 160

13.6.8 SPI n Data register (SPIn_DATA) (n=0,1)............................................................................ 160

13.6.9 SPI n Data Fetch register (SPIn_DF) (n=0,1)....................................................................... 161

13.6.10 SPI n DMA Control register (SPIn_DMACTRL) (n=0)..................................................... 161

13.6.11 SPI n DMA Number of Data Transfer register (SPIn_DMACNT) (n=0)........................... 161

13.6.12 SPI n DMA Number of Half Data Transfer register (SPIn_DMAHTCNT) (n=0) ............. 161

13.6.13 SPI n DMA Current Transfer Data Counter register (SPIn_CURCNT) (n=0) ................. 162

I2C...................................................................................................................................................... 163

14.1 OVERVIEW................................................................................................................................... 163

14.2 FEATURES.................................................................................................................................... 163

14.3 PIN DESCRIPTION....................................................................................................................... 163

14.4 WAVE CHARACTERISTICS....................................................................................................... 164

14.5 I2C MASTER MODES .................................................................................................................. 165

14.5.1 MASTER TRANSMITTER MODE.......................................................................................... 165

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32-Bit Cortex-M0 Micro-Controller

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14.5.2 MASTER RECEIVER MODE................................................................................................. 165

14.5.3 ARBITRATION ....................................................................................................................... 165

14.6 I2C SLAVE MODES...................................................................................................................... 166

14.6.1 SLAVE TRANSMITTER MODE ............................................................................................. 166

14.6.2 SLAVE RECEIVER MODE .................................................................................................... 166

14.7 I2C REGISTERS............................................................................................................................ 167

14.7.1 I2C n Control register (I2Cn_CTRL) (n=0,1)........................................................................ 167

14.7.2 I2C n Status register (I2Cn_STAT) (n=0,1)........................................................................... 168

14.7.3 I2C n TX Data register (I2Cn_TXDATA) (n=0,1) ................................................................. 169

14.7.4 I2C n RX Data register (I2Cn_RXDATA) (n=0,1)................................................................. 169

14.7.5 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0,1)................................................. 169

14.7.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0,1) ........................................ 169

14.7.7 I2C n SCL High Time register (I2Cn_SCLHT) (n=0,1)......................................................... 169

14.7.8 I2C n SCL Low Time register (I2Cn_SCLLT) (n=0,1)........................................................... 170

14.7.9 I2C n Timeout Control register (I2Cn_TOCTRL) (n=0,1) .................................................... 170

UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART).................... 171

15.1 OVERVIEW................................................................................................................................... 171

15.2 FEATURES.................................................................................................................................... 171

15.3 PIN DESCRIPTION....................................................................................................................... 171

15.4 BLOCK DIAGRAM....................................................................................................................... 172

15.5 BAUD RATE CALCULATION .................................................................................................... 173

15.6 AUTO-BAUD FLOW .................................................................................................................... 174

15.6.1 AUTO-BAUD.......................................................................................................................... 174

15.6.2 AUTO-BAUD MODES ........................................................................................................... 175

15.7 UART REGISTERS....................................................................................................................... 177

15.7.1 UART n Receiver Buffer register (UARTn_RB) (n=0,1,2,3).................................................. 177

15.7.2 UART n Transmitter Holding register (UARTn_TH) (n=0,1,2,3).......................................... 177

15.7.3 UART n Divisor Latch LSB registers (UARTn_DLL) (n =0,1,2,3)........................................ 177

15.7.4 UART n Divisor Latch MSB register (UARTn_DLM) (n=0,1,2,3) ........................................ 178

15.7.5 UART n Interrupt Enable register (UARTn_IE) (n=0,1,2,3) ................................................. 178

15.7.6 UART n Interrupt Identification register (UARTn_II) (n=0,1,2,3)........................................ 178

15.7.7 UART n Line Control register (UARTn_LC) (n=0,1,2,3) ...................................................... 179

15.7.8 UART n Line Status register (UARTn_LS) (n=0,1,2,3).......................................................... 180

15.7.9 UART n Scratch Pad register (UARTn_SP) (n=0,1,2,3)........................................................ 181

15.7.10 UART n Auto-baud Control register (UARTn_ABCTRL) (n=0,1,2,3)............................... 181

15.7.11 UART n Fractional Divider register (UARTn_FD) (n=0,1,2,3)........................................ 182

15.7.12 UART n Control register (UARTn_CTRL) (n=0,1,2,3)...................................................... 182

I2S ...................................................................................................................................................... 184