Samsung HT-DL100 Manual de usuario

DVD RECEIVER AMP

HT-DL100

SERVICE Manual

DVD RECEIVER AMP SYSTEM CONTENTS

Phones

Standby

Volume

Function

Open/Close

VI D E O

1. Alignment and Adjustments

2. Exploded Views and Parts List

3. Electrical Parts List

4. Block Diagrams

5. PCB Diagrams

6. Wiring Diagram

7. Schematic Diagrams

8. IC block Diagrams

9. Troubleshooting

ELECTRONICS

Printed in Korea

Code no. AH68-00664V

Samsung Electronics 8-1

8. IC Block Digrams

8-1 Main

1. 74CX244

LOW VOLTAGE CMOS OCTAL BUS BUFFER (3-STATE)

WITH 5V TOLERANT INPUTS AND OUTPUTS

ORDER CODES :

74LCX244M 74LCX244T

(Micro Package)

■5VTOLERANTINPUTSAND OUTPUTS

■HIGHSPEED:

tPD =6.5ns(MAX.)atVCC =3V

■POWER-DOWNPROTECTIONONINPUTS

ANDOUTPUTS

■SYMMETRICALOUTPUTIMPEDANCE:

|IOH|=IOL =24mA(MIN)

■PCIBUSLEVELSGUARANTEED AT24mA

■BALANCEDPROPAGATIONDELAYS:

tPLH @tPHL

■OPERATINGVOLTAGERANGE:

VCC (OPR)= 2.0Vto3.6V (1.5VDataRetention)

■PINANDFUNCTIONCOMPATIBLEWITH

74SERIES244

■LATCH-UPPERFORMANCE EXCEEDS500mA

■ESDPERFORMANCE:

HBM >2000V;MM > 200V

DESCRIPTION

The LCX244 is a low voltage CMOS OCTAL BUS

BUFFER (NON-INVERTED) fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS technology. It is ideal for low

power and high speed 3.3V applications; it can

be interfaced to 5V signal environment for both

(TSSOPPackage)

inputsandoutputs.

It has same speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

This device is designed to be used with 3 state

memoryaddressdrivers, etc.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

8-2 Samsung Electronics

2. 74VHC244

74VHC244

Octal Buffer/Line Driver with 3-STATE Outputs

General Description

The VHC244 is an advanced high speed CMOS octal bus

buffer fabricated with silicon gate CMOS technology. It

achieves high speed operation similar to equivalent Bipolar

Schottky TTL while maintaining the CMOS low power dissi-

pation. The VHC244 is a non-inverting 3-STATE buffer hav-

ing two active-LOW output enables. These devices are

designed to be used as 3-STATE memory address drivers,

clock drivers, and bus oriented transmitter/receivers.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two supply systems such as battery back up. This cir-

cuit prevents device destruction due to mismatched supply

and input voltages.

Features

■High Speed: tPD =3.9ns (typ) at VCC =5V

■High noise immunity: VNIH =VNIL =28% VCC (min)

■Power down protection is provided on all inputs

■Low noise: VOLP =0.6V (typ)

■Low power dissipation: ICC =4 mA (max) @ TA=25°C

■Pin and function compatible with 74HC244

Ordering Code:

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter ìXî to the ordering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

74VHC244M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300î Wide

74VHC244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300î Wide

Pin Names Description

OE1, OE23-STATE Output Enable Inputs

I0ñI7Inputs

O0ñO73-STATE Outputs

Samsung Electronics 8-3

74VHCT244A

Octal Buffer/Line Driver with 3-STATE Outputs

General Description

The VHCT244A is an advanced high speed CMOS octal

bus transceiver fabricated with silicon gate CMOS technol-

ogy. It achieves high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The VHCT244A is a non-inverting 3-

STATE buffer having two active-LOW output enables. This

device is designed to be used as 3-STATE memory

address drivers, clock drivers, and bus oriented transmitter/

receivers.

Protection circuits ensure that 0V to 7V can be applied to

the input and output (Note 1) pins without regard to the

supply voltage. These circuits prevent device destruction

due to mismatched supply and input/output voltages. This

device can be used to interface 5V to 3V systems and two

supply systems such as battery back up.

Note 1: Outputs in OFF-State

Features

■High Speed: tPD =5.9 ns (typ) at VCC =5V

■Power down protection is provided on inputs and

outputs

■Low power dissipation: ICC =4 mA (max) @ TA=25°C

■Pin and function compatible with 74HCT244

Ordering Code:

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter ìXî to the ordering code.

Logic Symbol Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

74VHCT244AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74VHCT244ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHCT244AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHCT244AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

OE1, OE23-STATE Output Enable Inputs

I0ñI7Inputs

O0ñO73-STATE Outputs

3. 74VHCT244A

8-4 Samsung Electronics

4. CS4228

5. CS49300

Samsung Electronics 8-5

6. CS8415A

8-6 Samsung Electronics

7.LC75275A

Pin Functions

Pin Pin No. Function I/O Handling when unused

VFL 1, 13 Driver block power supply connection. (Both pins must be connected.) — —

VDD 60 Logic block power supply connection. Provide a voltage between 4.5 and 5.5 V. — —

VSS 57 Power supply connection. Connect to the ground. — —

OSCI 59 Oscillator connection. An oscillator circuit is formed by connecting an external resistor I GND

OSCO 58 and capacitor to these pins. O OPEN

Display off control input.

BLK 61 BLK = Low (VSS) ... Display off. (S1 to S43 and G1 to G11 at VFL level.) I GND

BLK = High (VDD) ... Display on.

Note that serial data can be transferred while the display is turned off.

CL 63

DI 64 I GND

CE 62

G1 to G11 2 to 12 Digit outputs. These pins are P-channel open drain outputs with pull-down resistors. O OPEN

S1 to S43 56 to 14 Segment outputs for displaying the display data transferred by serial data input. These pins O OPEN

are P-channel open drain outputs with pull-down resistors.

Serial data transfer inputs. These pins must be connected to the system microcontroller.

CL: Synchronization clock

DI: Transfer data

CE: Chip enable

Samsung Electronics 8-7

FEATURES

·High speed access time:

120/150 nS (max.)

·Read operating current: 10 mA (max.)

·Erase/Programming operating current:

30 mA (max.)

·Standby current: 20 mA (max.)

·Low voltage power supply range, 3.0V to 3.6V

·+14V erase/+12V programming voltage

·Fully static operation

·All inputs and outputs directly TTL/CMOS

compatible

·Three-state outputs

·Available packages: 32-pin 600 mil DIP, 450

mil SOP and PLCC

PIN CONFIGURATIONS

4 3 2 1 3

0A14

A13

A11

32-pin PLCC

A10

A13

A11

PGM

A12

A15

A16

A14

Vcc

Vpp

17 Q3

GND

32-pin DIP

BLOCK DIAGRAM

CONTROL OUTPUT

BUFFER

DECODER CORE

ARRAY

GND

A16

PGM

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0-A16 Address Inputs

Q0-Q7 Data Inputs/Outputs

Chip Enable

Output Enable

PGM

Program Enable

VPP Program/Erase Supply Voltage

VCC Power Supply

GND Ground

NC No Connection

8.W271010

8-8 Samsung Electronics

8-2 DVD

1. ZIVA- 5 DVD CONTROLER

Figure 1 ZiVA-5 controller Pinout (208-pin PQFP)

Table 1 ZiVA-5 controller Pin List

Pin No. Pin Name I/O Voltage I/O Type

1 VDDP 3.3V ó

2 HA1 3.3V* I/O

3 HA15 3.3V* I/O

4 HA14 3.3V* I/O

5 HA13 3.3V* I/O

6 HA12 3.3V* I/O

104

103

102

101

100

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

VDD_3.3

HA1

HAD15

HAD14

HAD13

HAD12

HAD11

HAD10

HAD9

HAD8

HAD7

VDD_3.3

VSS

HAD6

HAD5

HAD4

HAD3

HAD2

HAD1

VDD_3.3

VSS

HAD0

HDTACK/WAIT

HIRQ0

UDS/UWE

LDS/LWE

R/W

IRRX1

VSS

VDDC

VSS

VDD_3.3

MADDR9

MADDR8

MADDR7

MADDR6

MADDR5

MADDR4

MADDR3

MADDR2

MADDR1

MADDR0

VSS

VDD_3.3

MADDR10

MADDR11

BA1

BA0

MCS0

MCS1

MRAS

MCAS

DA-IEC958

DA-DATA3

DA-DATA2

VSS

VDD_3.3

DA-DATA1

DA-DATA0

DA-BCK

DA-LRCK

DA-XCK

VSS

VDDC

A_VSS1

A_VDD1

A_VDD2

A_VSS2

XVDD

XTAL/VCLK216BP

XTAL

XVSS

VSS_RREF

VDAC_RREF

VDD_RREF

VDAC_DVDD

VDAC_DVSS

VDAC_0

VDAC_VDD0

VDAC_0B

VDAC_1

VDAC_VDD1

VDAC_1B

VDAC_2

VDAC_VDD2

VDAC_2B

VDAC_3

VDAC_VDD3

VDAC_3B

VDAC_4

VDAC_VDD4

VDAC_4B

HSYNC/IRQ2

VDATA0

VDATA1

VDATA2

VSS

VDD_3.3

VDATA3

VDATA4

VDATA5

VDATA6

VDATA7

VCLK

DAI-DATA

DAI-BCK/SYSCLKBP

DAI-LRCK/IEC958BP

I2C_CL

I2C_DA

RTS1

RXD1

TXD1

CTS1

VSS

VDD_3.3

SD-DATA7

SD-DATA6

SD-DATA5

SD-DATA4

VSS

VDDC

SD-DATA3

SD-DATA2

SD-DATA1

SD-DATA0

SD-REQ

SD-EN

VSS

VDD_3.3

SD-ERROR

SD-CLK

VSYNC/HIRQ1

RTS2/SPI_CLK

RXD2/SPI_MISO

TXD2/SPI_MOSI

CTS2/SPI_CS

VDD_5

HCS4

HCS3

HCS2

HCS1

HCS0

VSS

VDD_3.3

TRST

TDO

TDI

TMS

TCK

RESET

ALE

VSS

VDDC

HAD3

HAD2

VSS

ZiVA-5 Controller

Top View

VDD_3.3

VSS

MDATA31

MDATA30

MDATA29

MDATA28

VDD_3.3

MDQM3

VSS

MDATA27

MDATA26

MDATA25

MDATA24

MDATA23

MDATA22

MDATA21

MDATA20

VDD_3.3

MDQM2

VSS

MDATA19

MDATA18

MDATA17

MDATA16

VDDC

VSS

MDATA15

MDATA14

MDATA13

MDATA12

VDD_3.3

MDQM1

VSS

MDATA11

MDATA10

MDATA9

MDATA8

MDATA7

MDATA6

MDATA5

MDATA4

VDD_3.3

MDQM0

VSS

MDATA3

MDATA2

MDATA1

MDATA0

MCLK

VDD_3.3

VSS

MWE

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