NXP Semiconductors MC9S08SU16 Manual de usuario

MC9S08SU16 Reference Manual

Supports: MC9S08SU16VFK MC9S08SU8VFK

Document Number: MC9S08SU16RM

Rev. 5, 4/2017

MC9S08SU16 Reference Manual, Rev. 5, 4/2017

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Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................33

1.1.1 Purpose...........................................................................................................................................................33

1.1.2 Audience........................................................................................................................................................ 33

1.2 Conventions.................................................................................................................................................................. 33

1.2.1 Numbering systems........................................................................................................................................33

1.2.2 Typographic notation..................................................................................................................................... 34

1.2.3 Special terms..................................................................................................................................................34

Chapter 2

Introduction

2.1 Introduction...................................................................................................................................................................35

2.2 Module functional categories........................................................................................................................................35

2.2.1 S08L core modules.........................................................................................................................................36

2.2.2 System modules............................................................................................................................................. 36

2.2.3 Memories and memory interfaces..................................................................................................................37

2.2.4 Clocks.............................................................................................................................................................37

2.2.5 Security and integrity modules...................................................................................................................... 37

2.2.6 Analog modules............................................................................................................................................. 38

2.2.7 Timer modules............................................................................................................................................... 38

2.2.8 Communication interfaces............................................................................................................................. 39

2.2.9 Human-machine interfaces............................................................................................................................ 39

2.3 MCU block diagram..................................................................................................................................................... 40

2.4 Orderable part numbers.................................................................................................................................................41

Chapter 3

Memory

3.1 Memory map.................................................................................................................................................................43

3.2 Reset and interrupt vector assignments.........................................................................................................................44

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3.3 Register addresses assignments.................................................................................................................................... 46

3.4 Random-access memory (RAM).................................................................................................................................. 51

3.5 Flash memory................................................................................................................................................................51

3.6 System register file....................................................................................................................................................... 52

Chapter 4

Interrupt

4.1 Interrupts.......................................................................................................................................................................53

4.1.1 Interrupt stack frame...................................................................................................................................... 54

4.1.2 Hardware nested interrupt..............................................................................................................................55

4.1.2.1 Interrupt priority level register...................................................................................................57

4.1.2.2 Interrupt priority level comparator set....................................................................................... 57

4.1.2.3 Interrupt priority mask update and restore mechanism..............................................................57

4.1.2.4 Integration and application of the IPC....................................................................................... 58

4.2 IPC memory map and register descriptions..................................................................................................................59

4.2.1 IPC Status and Control Register (IPC_SC)....................................................................................................59

4.2.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)...................................................................... 60

4.2.3 Interrupt Level Setting Registers n (IPC_ILRSn)..........................................................................................61

4.3 IRQ................................................................................................................................................................................61

4.3.1 Features.......................................................................................................................................................... 62

4.3.1.1 Configuration options................................................................................................................ 62

4.3.1.2 Edge and level sensitivity.......................................................................................................... 63

4.4 IRQ Memory Map and Register Descriptions.............................................................................................................. 63

4.4.1 Interrupt Pin Request Status and Control Register (IRQ_SC).......................................................................63

Chapter 5

Clock management

5.1 Clock module................................................................................................................................................................65

5.2 System clock distribution..............................................................................................................................................65

5.3 Internal clock source (ICS)........................................................................................................................................... 67

5.4 20 kHz low-power oscillator (LPO)............................................................................................................................. 68

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5.5 Peripheral clock gating................................................................................................................................................. 68

Chapter 6

Power Management

6.1 Introduction...................................................................................................................................................................71

6.2 Features.........................................................................................................................................................................71

6.2.1 Run mode....................................................................................................................................................... 71

6.2.2 Wait mode......................................................................................................................................................72

6.2.3 Stop mode...................................................................................................................................................... 72

6.2.4 Active BDM enabled in stop mode................................................................................................................72

6.2.5 Power modes behaviors................................................................................................................................. 73

6.3 Bandgap reference........................................................................................................................................................ 74

Chapter 7

Signal multiplexing and signal descriptions

7.1 Introduction...................................................................................................................................................................75

7.2 Port control and interrupt module features................................................................................................................... 75

7.3 Signal multiplexing constraints.................................................................................................................................... 75

7.4 Pinout............................................................................................................................................................................76

7.4.1 Signal multiplexing and pin assignments.......................................................................................................76

7.4.2 Signal description table..................................................................................................................................77

7.4.3 Pinout ............................................................................................................................................................ 81

Chapter 8

Port Control (PORT)

8.1 Introduction...................................................................................................................................................................83

8.2 Port data and data direction...........................................................................................................................................84

8.3 Internal pullup/pulldown enable................................................................................................................................... 84

8.4 Input glitch filter........................................................................................................................................................... 85

8.5 Memory map and register definition.............................................................................................................................86

8.5.1 Port A Data Register (PORT_PTAD)............................................................................................................86

8.5.2 Port B Data Register (PORT_PTBD)............................................................................................................ 87

8.5.3 Port C Data Register (PORT_PTCD)............................................................................................................ 87

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8.5.4 Port A Direction Register (PORT_PTADD)................................................................................................. 88

8.5.5 Port B Direction Register (PORT_PTBDD)..................................................................................................89

8.5.6 Port C Direction Register (PORT_PTCDD)..................................................................................................89

8.5.7 Port A Pullup Enable Register (PORT_PTAPE)........................................................................................... 90

8.5.8 Port B Pullup/Pulldown Enable Register (PORT_PTBPE)........................................................................... 91

8.5.9 Port C Pullup Enable Register (PORT_PTCPE)............................................................................................91

8.5.10 Port B High Drive Strength Selection Register (PORT_PTBHD)................................................................ 92

8.5.11 Port Clock Division Register (PORT_FCLKDIV)........................................................................................ 92

8.5.12 Port Filter Register 0 (PORT_IOFLT0).........................................................................................................93

8.5.13 Port Filter Register 1 (PORT_IOFLT1).........................................................................................................94

8.5.14 Port Filter Register 2 (PORT_IOFLT2).........................................................................................................95

Chapter 9

System Integration Module (SIM)

9.1 Chip specific windowed COP.......................................................................................................................................97

9.2 System device identification (SDID)............................................................................................................................98

9.3 Universally unique identification (UUID)....................................................................................................................98

9.4 Reset and system initialization......................................................................................................................................98

9.5 Computer operating properly (COP) watchdog............................................................................................................99

9.6 System options..............................................................................................................................................................100

9.6.1 BKGD pin...................................................................................................................................................... 100

9.6.2 RESET_b pin enable......................................................................................................................................101

9.7 System interconnection.................................................................................................................................................101

9.7.1 Inter Module Crossbar Switch (XBAR).........................................................................................................101

9.7.2 Module to module interconnects....................................................................................................................103

9.8 Memory map and register definition.............................................................................................................................104

9.8.1 System Reset Status Register (SIM_SRS).....................................................................................................105

9.8.2 System Background Debug Force Reset Register (SIM_SBDFR)................................................................107

9.8.3 System Device Identification Register: High (SIM_SDIDH)........................................................................107

9.8.4 System Device Identification Register: Low (SIM_SDIDL).........................................................................108

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9.8.5 System Options Register 1 (SIM_SOPT1).................................................................................................... 108

9.8.6 System Options Register 2 (SIM_SOPT2).................................................................................................... 110

9.8.7 System Port A Pin Multiplexing Control Register: Low (SIM_MUXPTAL)...............................................111

9.8.8 System Port A Pin Multiplexing Control Register: High (SIM_MUXPTAH)..............................................112

9.8.9 System Port B Pin Multiplexing Control Register: Low (SIM_MUXPTBL)............................................... 113

9.8.10 System Port B Pin Multiplexing Control Register: High (SIM_MUXPTBH).............................................. 114

9.8.11 System Port C Pin Multiplexing Control Register: Low (SIM_MUXPTCL)............................................... 116

9.8.12 System Clock Gating Control 1 Register (SIM_SCGC1)..............................................................................116

9.8.13 System Clock Gating Control 2 Register (SIM_SCGC2)..............................................................................117

9.8.14 System Clock Gating Control 3 Register (SIM_SCGC3)..............................................................................119

9.8.15 System Clock Divider Register (SIM_SCDIV).............................................................................................120

9.8.16 System POR Register (SIM_PORREGn)...................................................................................................... 121

9.8.17 Illegal Address Register: High (SIM_ILLAH).............................................................................................. 122

9.8.18 Illegal Address Register: Low (SIM_ILLAL)............................................................................................... 122

9.8.19 Universally Unique Identifier Register 0 (SIM_UUID0).............................................................................. 123

9.8.20 Universally Unique Identifier Register 1 (SIM_UUID1).............................................................................. 123

9.8.21 Universally Unique Identifier Register 2 (SIM_UUID2).............................................................................. 124

9.8.22 Universally Unique Identifier Register 3 (SIM_UUID3).............................................................................. 124

9.8.23 Universally Unique Identifier Register 4 (SIM_UUID4).............................................................................. 125

9.8.24 Universally Unique Identifier Register 5 (SIM_UUID5).............................................................................. 125

9.8.25 Universally Unique Identifier Register 6 (SIM_UUID6).............................................................................. 126

9.8.26 Universally Unique Identifier Register 7 (SIM_UUID7).............................................................................. 126

Chapter 10

Central processor unit

10.1 Introduction...................................................................................................................................................................127

10.1.1 Features.......................................................................................................................................................... 127

10.2 Programmer's Model and CPU Registers..................................................................................................................... 128

10.2.1 Accumulator (A)............................................................................................................................................ 128

10.2.2 Index Register (H:X)......................................................................................................................................129

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10.2.3 Stack Pointer (SP).......................................................................................................................................... 129

10.2.4 Program Counter (PC)................................................................................................................................... 130

10.2.5 Condition Code Register (CCR).................................................................................................................... 130

10.3 Addressing Modes........................................................................................................................................................ 131

10.3.1 Inherent Addressing Mode (INH)..................................................................................................................132

10.3.2 Relative Addressing Mode (REL)..................................................................................................................132

10.3.3 Immediate Addressing Mode (IMM).............................................................................................................132

10.3.4 Direct Addressing Mode (DIR)......................................................................................................................133

10.3.5 Extended Addressing Mode (EXT)................................................................................................................133

10.3.6 Indexed Addressing Mode............................................................................................................................. 134

10.3.6.1 Indexed, No Offset (IX).............................................................................................................134

10.3.6.2 Indexed, No Offset with Post Increment (IX+)..........................................................................134

10.3.6.3 Indexed, 8-Bit Offset (IX1)........................................................................................................134

10.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+).................................................................... 135

10.3.6.5 Indexed, 16-Bit Offset (IX2)......................................................................................................135

10.3.6.6 SP-Relative, 8-Bit Offset (SP1)................................................................................................. 135

10.3.6.7 SP-Relative, 16-Bit Offset (SP2)............................................................................................... 136

10.3.7 Memory to memory Addressing Mode..........................................................................................................136

10.3.7.1 Direct to Direct...........................................................................................................................136

10.3.7.2 Immediate to Direct................................................................................................................... 136

10.3.7.3 Indexed to Direct, Post Increment..............................................................................................136

10.3.7.4 Direct to Indexed, Post-Increment............................................................................................. 137

10.4 Operation modes........................................................................................................................................................... 137

10.4.1 Stop mode...................................................................................................................................................... 137

10.4.2 Wait mode......................................................................................................................................................137

10.4.3 Background mode.......................................................................................................................................... 138

10.4.4 Security mode................................................................................................................................................ 139

10.5 HCS08 V6 Opcodes......................................................................................................................................................141

10.6 Special Operations........................................................................................................................................................ 141

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10.6.1 Reset Sequence.............................................................................................................................................. 141

10.6.2 Interrupt Sequence......................................................................................................................................... 141

10.7 Instruction Set Summary...............................................................................................................................................142

Chapter 11

Flash Memory Module (FTMRH)

11.1 Introduction...................................................................................................................................................................155

11.2 Feature...........................................................................................................................................................................155

11.2.1 Flash memory features...................................................................................................................................155

11.2.2 Other flash module features........................................................................................................................... 156

11.3 Functional description...................................................................................................................................................156

11.3.1 Modes of operation........................................................................................................................................ 156

11.3.1.1 Wait mode..................................................................................................................................156

11.3.1.2 Stop mode.................................................................................................................................. 156

11.3.2 Flash block read access..................................................................................................................................156

11.3.3 Flash memory map.........................................................................................................................................157

11.3.4 Flash initialization after system reset.............................................................................................................157

11.3.5 Flash command operations.............................................................................................................................157

11.3.5.1 Writing the FCLKDIV register..................................................................................................158

11.3.5.2 Command write sequence.......................................................................................................... 160

11.3.6 Flash interrupts...............................................................................................................................................162

11.3.6.1 Description of flash interrupt operation.....................................................................................162

11.3.7 Protection....................................................................................................................................................... 162

11.3.8 Security.......................................................................................................................................................... 165

11.3.8.1 Unsecuring the MCU using backdoor key access......................................................................166

11.3.8.2 Unsecuring the MCU using BDM............................................................................................. 167

11.3.8.3 Mode and security effects on flash command availability.........................................................167

11.3.9 Flash commands.............................................................................................................................................167

11.3.9.1 Flash commands.........................................................................................................................167

11.3.10 Flash command summary.............................................................................................................................. 168

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11.3.10.1 Erase Verify All Blocks command............................................................................................ 169

11.3.10.2 Erase Verify Block command....................................................................................................169

11.3.10.3 Erase Verify Flash Section command........................................................................................170

11.3.10.4 Read once command.................................................................................................................. 171

11.3.10.5 Program Flash command........................................................................................................... 172

11.3.10.6 Program Once command............................................................................................................173

11.3.10.7 Erase All Blocks command........................................................................................................174

11.3.10.8 Erase flash block command....................................................................................................... 174

11.3.10.9 Erase flash sector command.......................................................................................................175

11.3.10.10 Unsecure flash command...........................................................................................................176

11.3.10.11 Verify backdoor access key command.......................................................................................177

11.3.10.12 Set user margin level command.................................................................................................177

11.3.10.13 Set factory margin level command............................................................................................ 179

11.4 Memory map and register definition.............................................................................................................................180

11.4.1 Flash Clock Divider Register (FTMRH_FCLKDIV).................................................................................... 181

11.4.2 Flash Security Register (FTMRH_FSEC)..................................................................................................... 182

11.4.3 Flash CCOB Index Register (FTMRH_FCCOBIX)......................................................................................183

11.4.4 Flash Configuration Register (FTMRH_FCNFG).........................................................................................183

11.4.5 Flash Status Register (FTMRH_FSTAT)...................................................................................................... 184

11.4.6 Flash Protection Register (FTMRH_FPROT)............................................................................................... 185

11.4.7 Flash Common Command Object Register:High (FTMRH_FCCOBHI)......................................................186

11.4.8 Flash Common Command Object Register: Low (FTMRH_FCCOBLO).................................................... 187

11.4.9 Flash Option Register (FTMRH_FOPT)....................................................................................................... 187

Chapter 12

Internal Clock Source (ICS)

12.1 Introduction...................................................................................................................................................................189

12.1.1 Features.......................................................................................................................................................... 189

12.1.2 Block diagram................................................................................................................................................190

12.1.3 Modes of operation........................................................................................................................................ 190

MC9S08SU16 Reference Manual, Rev. 5, 4/2017

10 NXP Semiconductors

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