NXP Semiconductors Freescale KV4 Series Manual de usuario

KV4x Reference Manual

Supports MKV46, MKV45, MKV44, MKV43, MKV41, MKV40 part

numbers

Document Number: KV4XP100M150RM

Rev 2, 02/2015

Preliminary

KV4x Reference Manual, Rev. 2, 02/2015

2Preliminary Freescale Semiconductor, Inc.

Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................61

1.1.1 Purpose...........................................................................................................................................................61

1.1.2 Audience........................................................................................................................................................ 61

1.2 Conventions.................................................................................................................................................................. 61

1.2.1 Numbering systems........................................................................................................................................61

1.2.2 Typographic notation..................................................................................................................................... 62

1.2.3 Special terms..................................................................................................................................................62

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................63

2.2 Module Functional Categories......................................................................................................................................63

2.2.1 ARM® Cortex®-M4 Core Modules..............................................................................................................64

2.2.2 System Modules.............................................................................................................................................65

2.2.3 Memories and Memory Interfaces................................................................................................................. 66

2.2.4 Clocks.............................................................................................................................................................66

2.2.5 Security and Integrity modules...................................................................................................................... 66

2.2.6 Analog modules............................................................................................................................................. 67

2.2.7 Timer modules............................................................................................................................................... 67

2.2.8 Communication interfaces............................................................................................................................. 69

2.2.9 Human-machine interfaces............................................................................................................................ 69

2.3 Orderable part numbers and features............................................................................................................................ 70

Chapter 3

Core overview

3.1 ARM Cortex-M4 Core Configuration.......................................................................................................................... 73

3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 74

3.1.2 System Tick Timer.........................................................................................................................................74

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc. Preliminary 3

Section number Title Page

3.1.3 Debug facilities.............................................................................................................................................. 74

3.1.4 Core privilege levels...................................................................................................................................... 75

3.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 75

3.2.1 Interrupt priority levels.................................................................................................................................. 75

3.2.2 Non-maskable interrupt..................................................................................................................................75

3.2.3 Interrupt vector assignments ......................................................................................................................... 76

3.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................79

3.3.1 Wake-up sources............................................................................................................................................80

3.4 FPU Configuration........................................................................................................................................................80

3.5 JTAG Controller Configuration....................................................................................................................................81

Chapter 4

Memories and Memory Interfaces

4.1 Flash memory types......................................................................................................................................................83

4.2 Flash Memory Sizes......................................................................................................................................................83

4.3 Flash Security............................................................................................................................................................... 84

4.4 Flash Modes..................................................................................................................................................................84

4.5 Erase All Flash Contents...............................................................................................................................................84

4.6 FTFA_FOPT Register...................................................................................................................................................85

4.7 SRAM sizes.................................................................................................................................................................. 85

4.8 SRAM Arrays............................................................................................................................................................... 86

4.9 SRAM retention in low power modes.......................................................................................................................... 87

4.10 System Register file......................................................................................................................................................87

Chapter 5

Memory Map

5.1 Introduction...................................................................................................................................................................89

5.2 System Memory Map....................................................................................................................................................89

5.3 Peripheral Memory Map...............................................................................................................................................90

5.3.1 Read-after-write sequence and required serialization of memory operations................................................90

5.3.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map.......................................................................................... 91

KV4x Reference Manual, Rev. 2, 02/2015

4Preliminary Freescale Semiconductor, Inc.

Section number Title Page

Chapter 6

Clock Distribution

6.1 Introduction...................................................................................................................................................................95

6.2 High-level device clocking diagram............................................................................................................................. 95

6.2.1 Clock definitions............................................................................................................................................96

6.3 Internal clocking requirements..................................................................................................................................... 97

6.3.1 Clock divider values after reset......................................................................................................................98

6.3.2 VLPR mode clocking.....................................................................................................................................99

6.4 Clock Gating.................................................................................................................................................................99

6.5 Module clocks...............................................................................................................................................................100

6.5.1 nano edge module clocking............................................................................................................................101

6.5.2 WDOG clocking............................................................................................................................................ 101

6.5.3 Debug trace clock...........................................................................................................................................102

6.5.4 PMC 1-kHz LPO clock..................................................................................................................................102

6.5.5 PORT digital filter clocking...........................................................................................................................102

6.5.6 LPTMR clocking............................................................................................................................................103

6.5.7 FlexCAN clocking......................................................................................................................................... 103

6.5.8 UART clocking..............................................................................................................................................104

6.6 External clocks .............................................................................................................................................................104

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................105

7.2 Clocking Modes............................................................................................................................................................105

7.2.1 Partial Stop.....................................................................................................................................................105

7.2.2 DMA Wakeup................................................................................................................................................106

7.2.3 Compute Operation........................................................................................................................................107

7.2.4 Peripheral Doze..............................................................................................................................................108

7.3 Power modes.................................................................................................................................................................109

7.4 Module Operation in Low Power Modes......................................................................................................................110

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc. Preliminary 5

Section number Title Page

7.5 Power modes shutdown sequencing............................................................................................................................. 113

7.6 Clock Gating.................................................................................................................................................................113

7.7 Flash Program Restrictions...........................................................................................................................................114

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................115

8.2 Flash Security............................................................................................................................................................... 115

8.3 Security Interactions with other Modules.....................................................................................................................116

8.3.1 Security Interactions with Debug...................................................................................................................116

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................117

9.1.1 References......................................................................................................................................................119

9.2 The Debug Port.............................................................................................................................................................119

9.2.1 JTAG-to-SWD change sequence................................................................................................................... 119

9.3 Debug Port Pin Descriptions.........................................................................................................................................120

9.4 JTAG status and control registers.................................................................................................................................120

9.4.1 MDM-AP Control Register............................................................................................................................121

9.4.2 MDM-AP Status Register.............................................................................................................................. 123

9.5 Debug Resets................................................................................................................................................................ 124

9.6 AHB-AP........................................................................................................................................................................124

9.7 ITM............................................................................................................................................................................... 125

9.8 TPIU..............................................................................................................................................................................125

9.9 DWT............................................................................................................................................................................. 126

9.10 Debug in Low Power Modes........................................................................................................................................ 126

9.10.1 Debug Module State in Low Power Modes...................................................................................................127

9.11 Debug & Security......................................................................................................................................................... 127

Chapter 10

Reset and Boot

10.1 Introduction...................................................................................................................................................................129

KV4x Reference Manual, Rev. 2, 02/2015

6Preliminary Freescale Semiconductor, Inc.

Section number Title Page

10.2 Reset..............................................................................................................................................................................129

10.2.1 Power-on reset (POR).................................................................................................................................... 130

10.2.2 System resets..................................................................................................................................................130

10.2.2.1 External pin reset (PIN)............................................................................................................. 130

10.2.2.2 Low-voltage detect (LVD) reset................................................................................................ 131

10.2.2.3 Computer operating properly (COP) watchdog reset................................................................ 132

10.2.2.4 Low leakage wakeup (LLWU) reset..........................................................................................132

10.2.2.5 Multipurpose clock generator loss-of-clock (LOC) reset.......................................................... 132

10.2.2.6 Software reset (SW)...................................................................................................................133

10.2.2.7 Lockup reset (LOCKUP)........................................................................................................... 133

10.2.2.8 MDM-AP system reset request..................................................................................................133

10.2.3 Debug resets...................................................................................................................................................133

10.2.3.1 JTAG reset................................................................................................................................. 133

10.2.3.2 nTRST reset............................................................................................................................... 134

10.2.3.3 Resetting the Debug subsystem................................................................................................. 134

10.3 Boot...............................................................................................................................................................................135

10.3.1 Boot sources...................................................................................................................................................135

10.3.2 FOPT boot options.........................................................................................................................................135

10.3.3 Boot sequence................................................................................................................................................ 136

Chapter 11

Signal Multiplexing

11.1 Introduction...................................................................................................................................................................139

11.2 Port control and interrupt module features................................................................................................................... 139

11.3 Clock gating..................................................................................................................................................................140

11.4 Signal multiplexing constraints.................................................................................................................................... 141

11.5 KV4x Signal Multiplexing and Pin Assignments.........................................................................................................141

11.6 Pinout diagrams............................................................................................................................................................ 146

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc. Preliminary 7

Section number Title Page

Chapter 12

Port control and interrupts (PORT)

12.1 Introduction...................................................................................................................................................................151

12.2 Overview.......................................................................................................................................................................151

12.2.1 Features.......................................................................................................................................................... 151

12.2.2 Modes of operation........................................................................................................................................ 152

12.2.2.1 Run mode................................................................................................................................... 152

12.2.2.2 Wait mode..................................................................................................................................152

12.2.2.3 Stop mode.................................................................................................................................. 152

12.2.2.4 Debug mode............................................................................................................................... 152

12.3 External signal description............................................................................................................................................153

12.4 Detailed signal description............................................................................................................................................153

12.5 Memory map and register definition.............................................................................................................................153

12.5.1 Pin Control Register n (PORTx_PCRn).........................................................................................................160

12.5.2 Global Pin Control Low Register (PORTx_GPCLR)....................................................................................163

12.5.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................163

12.5.4 Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 164

12.5.5 Digital Filter Enable Register (PORTx_DFER).............................................................................................164

12.5.6 Digital Filter Clock Register (PORTx_DFCR)..............................................................................................165

12.5.7 Digital Filter Width Register (PORTx_DFWR)............................................................................................ 165

12.6 Functional description...................................................................................................................................................166

12.6.1 Pin control......................................................................................................................................................166

12.6.2 Global pin control.......................................................................................................................................... 167

12.6.3 External interrupts..........................................................................................................................................167

12.6.4 Digital filter....................................................................................................................................................168

Chapter 13

System Integration Module (SIM)

13.1 Introduction...................................................................................................................................................................171

13.1.1 Features.......................................................................................................................................................... 171

KV4x Reference Manual, Rev. 2, 02/2015

8Preliminary Freescale Semiconductor, Inc.

Section number Title Page

13.2 Memory map and register definition.............................................................................................................................172

13.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 173

13.2.2 System Options Register 2 (SIM_SOPT2).................................................................................................... 174

13.2.3 System Options Register 4 (SIM_SOPT4).................................................................................................... 176

13.2.4 System Options Register 5 (SIM_SOPT5).................................................................................................... 179

13.2.5 System Options Register 7 (SIM_SOPT7).................................................................................................... 180

13.2.6 System Options Register 8 (SIM_SOPT8).................................................................................................... 182

13.2.7 System Options Register 9 (SIM_SOPT9).................................................................................................... 185

13.2.8 System Device Identification Register (SIM_SDID).....................................................................................186

13.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................188

13.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................190

13.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................192

13.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................194

13.2.13 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................194

13.2.14 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 197

13.2.15 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 198

13.2.16 Unique Identification Register High (SIM_UIDH)....................................................................................... 199

13.2.17 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................199

13.2.18 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 200

13.2.19 Unique Identification Register Low (SIM_UIDL)........................................................................................ 200

13.2.20 System Clock Divider Register 4 (SIM_CLKDIV4).....................................................................................201

13.2.21 Miscellaneous Control Register (SIM_MISCTRL).......................................................................................202

13.2.22 Miscellaneous Control Register 2 (SIM_MISCTRL2)..................................................................................203

13.2.23 WDOG Control Register (SIM_WDOGC)....................................................................................................206

13.2.24 Power Control Register (SIM_PWRC)..........................................................................................................207

13.2.25 ADC Channel 6/7 Mux Control Register (SIM_ADCOPT)..........................................................................209

13.3 Functional description...................................................................................................................................................211

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc. Preliminary 9

Section number Title Page

Chapter 14

Kinetis Flashloader

14.1 Introduction...................................................................................................................................................................213

14.2 Functional Description..................................................................................................................................................214

14.2.1 Memory Maps................................................................................................................................................214

14.2.2 Start-up Process..............................................................................................................................................215

14.2.3 Clock Configuration.......................................................................................................................................217

14.2.4 Flashloader Protocol...................................................................................................................................... 217

14.2.4.1 Command with no data phase.................................................................................................... 217

14.2.4.2 Command with incoming data phase.........................................................................................218

14.2.4.3 Command with outgoing data phase..........................................................................................220

14.2.5 Flashloader Packet Types...............................................................................................................................222

14.2.5.1 Ping packet.................................................................................................................................222

14.2.5.2 Ping Response Packet................................................................................................................ 223

14.2.5.3 Framing Packet.......................................................................................................................... 223

14.2.5.4 Command packet........................................................................................................................225

14.2.5.5 Data packet.................................................................................................................................227

14.2.5.6 Response packet.........................................................................................................................227

14.2.6 Flashloader Command API............................................................................................................................229

14.2.6.1 GetProperty command............................................................................................................... 229

14.2.6.2 SetProperty command................................................................................................................231

14.2.6.3 FlashEraseAll command............................................................................................................ 233

14.2.6.4 FlashEraseRegion command......................................................................................................234

14.2.6.5 FillMemory command................................................................................................................235

14.2.6.6 WriteMemory command............................................................................................................237

14.2.6.7 Read memory command............................................................................................................ 239

14.2.6.8 Execute command......................................................................................................................241

14.2.6.9 Reset command..........................................................................................................................241

KV4x Reference Manual, Rev. 2, 02/2015

10 Preliminary Freescale Semiconductor, Inc.

Este manual sirve para los siguientes modelos

Tabla de contenidos

Otros manuales de Microcontrolador de NXP Semiconductors

NXP Semiconductors

NXP Semiconductors PN7462AU Manual de usuario

NXP Semiconductors

NXP Semiconductors LPC11E Series Manual de usuario

NXP Semiconductors

NXP Semiconductors Kinetis KE1xZ256 Manual de usuario

NXP Semiconductors

NXP Semiconductors i.MX 8M PLUS EVK Manual de usuario

NXP Semiconductors

NXP Semiconductors freescale semiconductor CSM12D Manual de usuario

NXP Semiconductors

NXP Semiconductors S12ZVML-MINIKIT Manual de usuario

NXP Semiconductors

NXP Semiconductors HCS12 Manual de usuario

NXP Semiconductors

NXP Semiconductors LPC1768 Manual de usuario

NXP Semiconductors

NXP Semiconductors IoT ZTB-DK006 Manual de usuario

NXP Semiconductors

NXP Semiconductors LPC1102 Manual de usuario

NXP Semiconductors

NXP Semiconductors LPC824M201JHI33 Manual de usuario

NXP Semiconductors

NXP Semiconductors MPC5777M Guía del usuario

NXP Semiconductors

NXP Semiconductors Freescale TWR-MECH Manual de usuario

NXP Semiconductors

NXP Semiconductors UM10883 Manual de usuario

NXP Semiconductors

NXP Semiconductors S12VR32EVB Manual de usuario

NXP Semiconductors

NXP Semiconductors TWR-K21F120M Manual de usuario

NXP Semiconductors

NXP Semiconductors MRF300AN Manual de usuario

NXP Semiconductors

NXP Semiconductors S32R372141EVB Manual de usuario

NXP Semiconductors

NXP Semiconductors SAFE ASSURE Qorivva MPC5602P Manual de usuario

NXP Semiconductors

NXP Semiconductors MPC57xx Instrucciones de instalación y funcionamiento

NXP Semiconductors

NXP Semiconductors S32R274RRUEVB Manual de usuario

NXP Semiconductors

NXP Semiconductors Freescale 56800TDC Manual de usuario

NXP Semiconductors

NXP Semiconductors S12ZVM-EWP Manual de usuario

NXP Semiconductors

NXP Semiconductors M53015EVB Manual de usuario

Manuales populares de Microcontrolador de otras marcas

AMS

AMS AS7261 Demo Kit Manual de usuario

Novatek

Novatek NT6861 Manual de usuario

Espressif Systems

Espressif Systems ESP8266 SDK Guía de configuración

Nuvoton

Nuvoton ISD61S00 ChipCorder Guía

STMicrolectronics

STMicrolectronics ST7 Assembler Linker Manual de usuario

Texas Instruments

Texas Instruments Chipcon CC2420DK Manual de usuario

Lantronix

Lantronix Intrinsyc Open-Q 865XR SOM Manual de usuario

NEC

NEC 78GK0S/K 1+ Series Instrucciones de instalación y funcionamiento

Mikroe

Mikroe SEMITECH N-PLC Click Instrucciones de instalación y funcionamiento

Intel

Intel Agilex Manual de usuario

Cypress

Cypress CY4607 HX2VL Manual de usuario

DIGITAL-LOGIC

DIGITAL-LOGIC MICROSPACE Manual de usuario

Texas Instruments

Texas Instruments TMS320F2837 D Series Manual de usuario

CYPRES

CYPRES CY14NVSRAMKIT-001 Manual de usuario

Texas Instruments

Texas Instruments INA-DUAL-2AMP-EVM Manual de usuario

Espressif Systems

Espressif Systems ESP8266EX Instrucciones de funcionamiento

Abov

Abov AC33M8128L Manual de usuario

Laird

Laird BL654PA Manual de usuario

NXP Semiconductors freescale KV4 Series Manual de usuario

Manuales populares de Microcontrolador de otras marcas