National Semiconductor ADC14DC105 Manual de usuario

1 http://www.national.com

National Semiconductor

July 27, 2011

Rev 0.10

Evaluation Board User’s Guide

ADC14DC105 Dual 14-Bit, 105MSPS A/D Converter

ADC14DC0 0 Dual 14-Bit, 0MSPS A/D Converter

ADC12DC105 Dual 12-Bit, 105MSPS A/D Converter

ADC12DC0 0 Dual 12-Bit, 0MSPS A/D Converter

2 http://www.national.com

Table of Contents

1.0 Introduction ......................................................................................................................................... 3

2.0 Board ssembly ................................................................................................................................... 3

3.0 Quick Start ........................................................................................................................................... 4

4.0 Functional Description ......................................................................................................................... 4

4.1 nalog Input .......................................................................................................................... 4

4.2 DC reference circuitry ........................................................................................................ 5

4.3 DC clock circuit .................................................................................................................. 5

4.4 Digital Data Output ............................................................................................................... 5

4.5 Data Format/ Duty Cycle Stabilizer ...................................................................................... 5

4.6 Power Supply Connections .................................................................................................... 5

5.0 Installing the DC14C105 Evaluation Board...................................................................................... 5

6.0 Hardware Schematic ............................................................................................................................ 6

7.0 Evaluation Board Layout ..................................................................................................................... 9

8.0 Evaluation Board Bill of Materials ...................................................................................................... 13

1.0 Operating in the Computer Mode ..................................................................................................... 16

2.0 Summary Tables of Test Points, Connectors, and Jumper Settings ................................................. 16

2.1 Test Points .......................................................................................................................... 16

2.2 Connectors .......................................................................................................................... 16

2.3 Jumper settings ................................................................................................................... 16

2.4 Solder Jumper settings ........................................................................................................ 16

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1.0 Introduction

This Evaluation Board may be used to evaluate one of

the A/D Converters : ADC1 DC080, ADC14DC080,

ADC1 DC105, or ADC14DC105. The ADC is one of a

family of 1 and 14 bit dual channel analog to digital

converters that provides data at rates of up to 105MHz.

Further reference in this User’s Guide to the

ADC14DC105 is meant to also include the other listed

parts unless otherwise specified

The evaluation board is designed to be used with the

WaveVision5™ Data Capture Board which is connected

to a personal computer through a USB port and running

WaveVision5™ software, operating under Microsoft

Windows. The software can perform an FFT on the

captured data upon command and, in addition to a

frequency domain plot, shows dynamic performance in

the form of SNR, SINAD, THD SFDR and ENOB. The

latest WaveVision hardware and software is available

through the National Semiconductor website:

http://www.national.com/appinfo/adc/wv4.html

2.0 Board Assembly

The ADC14DC105 Evaluation Board comes pre-

assembled. Refer to the Bill of Materials in Section 8 for

a description of components, to Figure 1 for major

component placement and to Section 6 for the

Evaluation Board schematic.

Figure 1. Major Component and Jumper Locations

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FutureBus

Connector

FutureBus

Connector

Signal

Cond.

Signal

Cond.

Figure 2: Test Set Up

3.0 Quick Start

Refer to Figure 1 for locations of jumpers, test points and

major components. Refer to Figure 2 for the test set up.

The board is configured by default to use a crystal clock

source and internal reference. Refer to Section 4.0 and

the Appendix for more information on jumper settings.

The input network of this board is configured for input

frequencies up to approximately 70MHz. Refer to Section

4.1 for more information about input networks.

You can download the latest version of the WaveVision 5

software from http://www.national.com

1. Apply power to the WaveVision5™ board and

connect it to the computer using a USB cable. See

the WaveVision5™ Board Manual for operation of

that board. Connect the evaluation board to the

WaveVision5™ Data Capture Board. NOTE: power

to the WaveVision5 Data Capture Board should

be applied before the power to the ADC14DC105

Evaluation Board to ensure that the FPGA on the

WaveVison5 Data Capture Board is not damaged.

. Connect a clean +5V power supply to pin of Power

Connector JR1. Pin 1 is ground.

3. Connect a signal from a 50-Ohm source to

connector J9 (Channel A). Be sure to use a

bandpass filter before the Evaluation Board.

4. Adjust the input signal amplitude as needed to

ensure that the signal does not over-range by

examinining a histogram of the output data with the

WaveVision5™ software.

4.0 Functional Description

The ADC14DC105 Evaluation Board schematic is shown

in Section 6. A list of test points and jumper settings can

be found in the Appendix.

4.1 Analog Input

To obtain the best distortion results the analog input

network must be optimized for the signal frequency being

applied. Examples of input networks are shown in

Figures 3 and 4. The ADC14DC105 Evaluation Board

comes configured for input frequencies up to 70MHz as

seen in Figure 4. The input network is intended to accept

a low-noise sine wave signal of up to V peak-to-peak

amplitude. To accurately evaluate the dynamic

performance of this converter, the input test signal will

have to be passed through a high-quality bandpass filter.

For input frequencies above 70MHz the circuit of Figure 4

may be used.

5 http://www.national.com

ADC

Input

10pF

CMO

0.1uF

5Ω

MABACT0039

0.1uF

MABACT0039

Figure 3. Analog Input Network for F

> 70MHz

For input frequencies below 70MHz the circuit of Figure 4

may be used.

ADC

Input

18 pF

CMO

0.1 µF

ADT1-1WT

50Ω0.1 µF

0Ω

Figure 4. Analog Input Network for F

< 70MHz

4.2 ADC reference circuitry

The ADC14DC105 can use an internal or external 1. V

reference. This Evaluation Board is configured to use the

internal reference.

4.3 ADC clock circuit

Solder jumpers are used to select the path of the clock to

the ADC. While not as convenient as pin-type jumpers,

these introduce less noise into the clock signal.

Care must be taken to provide a high quality low jitter

clock source. The board has a Pletronics SM7745 type

crystal clock. It is buffered by U11 (NC7WV1 5) and

applied to the ADC’s clock input pin.

The user can configure the board for an external clock at

connector J1. For this option short the pins of solder

jumper JP4 and open the pins of JP10. It may also be

necessary to remove L5 so the crystal is not powered.

Refer to the schematic for more detail.

4.4 Digital Data Output

The digital output data for Channel A is available at pins

B4 (MSB) through B17 of the WaveVision™ (WV4)

connector J8. The digital output data for Channel B is

available at pins A4 (MSB) through A17 of the

WaveVision™ (WV4) connector J8.

4.5 Data Format/ Duty Cycle Stabilizer

Output data format and the duty cycle stabilizer (DCS)

are controlled by jumper JP17.

Shorting pins 1- of JP17 sets the output format to ’s

complement with DCS Off.

Shorting pins 3-4 of JP17sets the output format to ’s

complement with DCS On.

Shorting pins 5-6 of JP17 sets the output format to offset

binary with DCS On.

Shorting pins 7-8 of JP17 sets the output format to offset

binary with DCS Off. This is the default setting.

4.6 Power Supply Connections

Power to this board is supplied through power connector

JR1. The only supply needed is +5V at pin plus ground

at pin 1.

Voltage and current requirements for the ADC14DC105

Evaluation Board are:

•

+5.0V at 500 mA

5.0 Installing the ADC14DC105 Evaluation Board

The evaluation board requires a single power supply as

described in Section 4.6. NOTE: power to the

WaveVision4 Data Capture Board should be applied

before the power to the ADC14DC105 Evaluation

Board to insure that the FPGA on the WaveVison5

Data Capture Board is not damaged. An appropriate

signal source should be connected to the Signal Input

SMA connector J9 (Channel A) or J5 (Channel B). When

evaluating dynamic performance, an appropriate signal

generator (such as the HP8644B or the R&S SME-03)

with 50 Ohm source impedance should be connected to

the Analog Input connector through an appropriate

bandpass filter as even the best signal generator

available can not produce a signal pure enough to

evaluate the dynamic performance of an ADC.

If this board is used in conjunction with the the

WaveVision5™ Data Capture Board and WaveVision5™

software, a USB cable must be connected between the

Data Capture Board and the host. See the

WaveVision5™ Data Capture Board manual for details.

6 http://www.national.com

6.0 Hardware Schematic

C31

0.01uF

.1uF

DB9

LM1117/TO- 5

VIN

ADJ

VOUT

DB10

VCLK

C59

U13

LM1117/TO- 5

VIN

ADJ

VOUT

R1 4

1 4

R1 3

C110

DB7

Vref t_B

.1uF

DB6

.1uF

C103

0.01uF

C104

.1uF

DB5

R1 0

1 4

DB4

C101

DB3

R1 1

C85

0.01uF

C86

.1uF

C11

.1uF

C87

.1uF

DB1

C15

.1uF

C88

0.01uF

C14

.1uF

C13

1uF

C89

0.01uF

C90

.1uF

C91

.1uF

C41

10uF

C84

0.01uF

+5V

L 4 P

BAT54

R1 5 .1

LP 988AIM- .5

By pass

Delay

GND

Vin

Shutdown/

Error/ 7

Sense 6

Vout 5

C57

0.01uF

C40

4.7u

C 6

0.01uF

C 5

.1uF

ANALOG BYPASSING

DB0

C 7

0.01uF

C 8

.1uF

C 9

0.01uF

C30

.1uF

+5V

C 1

.1uF

C43

.1uF

0.01uF

C19

C 0

10uF

L1JR1

+5V

GND 1

PWR

+3.3V

+2.5V

Output

Output Measurement

DA[0..13]

DB[0..13]

DRDY

Vref t_A

DA[0..13]

DA13

Vref b_A

Vref b_B

DA1

C39

0.01uF

Vref t_B

C44

.1uF

DA11

DA10

Input

Analog Input

VCOM_A

VCOM_B

Vin_A-

Vin_A+

Vin_B+

Vin_B-

DA9

C45

0.01uF

C46

.1uF

DA8

Vref t_A

Vref b_A

DA7

DA6

DA5

DA4

DA3

Oscillator/4smd

GND

OUT 3

VDD 4

C 4

DA1

+5V

DA0

C 3

.1uF

C48

10uF

+5V

L 4 P

BAT54

LP 988AIM-3.3

By pass

Delay

GND

Vin

Shutdown/

Error/ 7

Sense 6

Vout 5

C58

0.01uF

C47

4.7u

C49

0.01uF

C50

.1uF

C51

.1uF

0.01uF

+5V

C53

0.01uF

C54

.1uF

Vref b_B

C55

.1uF

C56

0.01uF

LATCH BYPASSING

+3.3V

C100

DB[0..13]

TP1

GND

TP3

GND

TP4

GND

.1uF

JP14

PD_A

.1uF

External Clock

49.9

C33

.1uF

U11

NC7WV1 5

GND 4

VCC 8

OE1

Y1 6

Y 3

CLK

JP10

jumper/sm

C10

.1uF

DB11

DB1

DB13

JP4

jumper/sm

DB8

JP1

jumper/sm

R19

40. k

JP3

jumper/sm

R14 .1

CLK

1uF

R17

40. k

C35

VCLK

C36

.1uF

1uF

C37

0.01uF

JP17

OF/DCC

R 0

C18

C16

10uF

C17

10uF

R 1

VD VA

JP16

PD_B

CLK

ADC14DC105

VinA-

AGND

VinA+

VinB-

14 VinB+

CLK

OF/DCC

N/C 56

PD_B

Vref b_A

Vref b_B

Vref t_A

Vref t_B

Vref 59

Vcom_A

Vcom_B

DA0 40

DA1 41

DA 4

DA3 43

DA4 44

DA5 45

DA6 46

DA7 47

DA8 48

DA9 49

DA10 5

DA11 53

DA1 54

DA13 55

DB0

DB1

DB3

DB4

DB5

DB6

DB7

DB8 31

DB9 3

DB10 33

DB11 34

DB1 35

DB13 36

DRDY 39

VA 58

VA 60

AGND

PD_A 57

VDR

VDR 38

VDR 50

DRGND

DRGND 37

DRGND 51

C10

.1uF

7 http://www.national.com

C78

.1uF

C75

.1uF

C68

10pF

R117

49.9

C105

100pF

C69

10pF

C70

10pF

C106

.1uF

R 8

49.9

C71

10pF

C107

100pF

C108

.1uF

ADT1-1WT+

1 6

3 4

Vin_A-

R 6

18.7

R30

18.7

Vin_A+

Vin_A-

R 7

DNP

R 9

DNP

C65

DNP

C67

3.3pF

Vin_B-

Vin_B+

R35

18.7

R38

18.7

Vin_B-

R34

DNP

R37

DNP

C77

DNP

C79

3.3pF

Vin_A+

ADT1-1WT+

1 6

3 4

C96

.1uF

INPUT

VCOM_B

49.9

VCOM_B

Vin_B+

C66

.1uF

R119

49.9

VCOM_A

8 http://www.national.com

DA0

DB[0..13]

DA[0..13]

DAR[0..13]

DBB0

RP - 0

8 9

DB0

RP3

RP1- 0

8 9

DBB7

DBR[0..13]

DBB13

DBB6

DBB9

DBB5

DBR0

DBR1

DBB11

DBR

DBB1

DBB8

DBB1

DBB

DBB10

DAB13DAB13

DBB4

DB13

DB1

DB10

DBR13

DBR1

DB11

DBR10

DBR11

DB9

DB7

DB8

DBR5

R66 .1

DB6

R58 .1

DB4

DB5

DBR3DB3

74LCX16 44/SO

1Y1

1Y 3

1Y3 5

1Y4 6

Y 1 8

Y 9

Y 3 11

Y 4 1

3Y1 13

3Y 14

3Y3 16

3Y4 17

4Y1 19

4Y 0

4Y3

4Y4 3

1A4

1A3

1A1

3A4

3A3

3A1

4A4

4A3

4A1

1OE

4OE

4 3OE

5 OE

GND

VCC 7

VCC 18

VCC 31

VCC 4

R69 .1

DBR9

R59 .1

DBR1

DBR13

DBR10

DBR11

DBR4

DBB7

DBB13

R68 .1

DBB11

DBB1

DBB9

DBB10

DBR9

DBB8

R65 .1

DBR7

DBR8

DBR4

DBR6

DBR7

DBR3

DBR0

DBR1

DBR

R70 .1 DBB0

R60 .1

DBB5

DBB6

DBB3

DBB4

R71

DBB1

DBB

DBR8 R61 .1

DBR5

R63 .1

DBR6

R6 .1

DBB[0..13]

R64 .1

R57 .1

DB1

R67 .1

DB[0:13]

BUF_CLK

R99 .1

R10 .1

R101 .1

R103 .1

R105 .1

R104 .1

R100 .1

DRDY

DAB1DAB1

DAB3DAB3

DABDAB

DAB4DAB4

DAB5DAB5

DAB7DAB7

DAB6DAB6

DAB8DAB8

DAB10DAB10

DAB9DAB9

DAB11DAB11

DAB1DAB1

R77 .1

R76 .1

R79 .1

R78 .1

R81 .1

R80 .1

R75 .1

DAR0

DAR1

R45 .1

DAR

DA13

DA1

DA10

DAR1

DAR13

DA11

BUF_CLK

DAR10

DBB3

DAR11

DA9

DAB0DAB0

DA7

DA8

DAR5

R51 .1

R47 .1

DA6

DA3

DA4

DA5

DAR3

74LCX16 44/SO

1Y1

1Y 3

1Y3 5

1Y4 6

Y1 8

Y 9

Y3 11

Y4 1

3Y1 13

3Y 14

3Y3 16

3Y4 17

4Y1 19

4Y 0

4Y3

4Y4 3

1A4

1A3

1A1

3A4

3A3

3A1

4A4

4A3

4A1

1OE

4OE

4 3OE

5 OE

GND

VCC 7

VCC 18

VCC 31

VCC 4

R53 .1

R46 .1

DAR9

DAR13

DAR1

DAR11

DAR4

DAR10

DAB13

DAB7

R55 .1

DAB10

DAB11

DAB1

DAB8

DAB9

R4 .1

DAR9

DAR7

DAR8

DAR6

DAR7

DAR3

DAR4

DAR1

DAR

DAR0 R54 .1

R48 .1

DAB0

DAB4

DAB5

DAB6

DAB1

DAB

DAB3

R49 .1

DAR8

DAR5

R43 .1

DAR6

R50 .1

DAB[0..13]

R44 .1

R41 .1

DA1

R5 .1

C83

.1uF

DA[0:13]

U10

4C0 /SO8

GND

SDA

5SCL

6WP 7

VCC 8

J8 FUTUREBUS_96

A1 A1

B1 B1

C1 C1

D1 D1

A A

A3 A3

A4 A4

A5 A5

A6 A6

A7 A7

A8 A8

A9 A9

A10 A10

A11 A11

A1 A1

A13 A13

A14 A14

A15 A15

A16 A16

A17 A17

A18 A18

A19 A19

A 0 A 0

A 1 A 1

A A

A 3 A 3

A 4 A 4

B B

B3 B3

B4 B4

B5 B5

B6 B6

B7 B7

B8 B8

B9 B9

B10 B10

B11 B11

B1 B1

B13 B13

B14 B14

B15 B15

B16 B16

B17 B17

B18 B18

B19 B19

B 0 B 0

B 1 B 1

B B

B 3 B 3

B 4 B 4

C C

C3 C3

C4 C4

C5 C5

C6 C6

C7 C7

C8 C8

C9 C9

C10 C10

C11 C11

C1 C1

C13 C13

C14 C14

C15 C15

C16 C16

C17 C17

C18 C18

C19 C19

C 0 C 0

C 1 C 1

C C

C 3 C 3

C 4 C 4

D D

D3 D3

D4 D4

D5 D5

D6 D6

D7 D7

D8 D8

D9 D9

D10 D10

D11 D11

D1 D1

D13 D13

D14 D14

D15 D15

D16 D16

D17 D17

D18 D18

D19 D19

D 0 D 0

D 1 D 1

D D

D 3 D 3

D 4 D 4

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7.0 Evaluation Board Layout

Layer 1: Component Side

10 http://www.national.com

Layer 2: Ground

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