National Instruments PXI Express NI PXIe-1065 Manual de usuario

INSTALLATION GUIDE

18-Slot NI PXIe-1065 Backplane

This guide describes installation requirements for the 18-slot

NI PXIe-1065 backplane.

Contents

NI PXIe-1065 Backplane Overview ....................................................... 2

Interoperability with CompactPCI................................................... 3

System Controller Slot..................................................................... 3

Hybrid Peripheral Slots.................................................................... 4

PXI Peripheral Slots......................................................................... 4

PXI Express Peripheral Slots........................................................... 4

System Timing Slot ......................................................................... 5

PXI Local Bus.................................................................................. 6

PXI Trigger Bus............................................................................... 7

System Reference Clock.................................................................. 8

PXIe_SYNC_CTRL ........................................................................ 10

Mechanical Requirements....................................................................... 11

Mounting.......................................................................................... 11

Cooling............................................................................................. 11

Handling.................................................................................................. 12

Dimensions ...................................................................................... 12

Electrical Requirements .......................................................................... 13

PXI Connectors................................................................................ 13

Power ............................................................................................... 14

Connector J205 ......................................................................... 14

Connector J206 ......................................................................... 16

Connector J200 ......................................................................... 17

Connectors J213, J214, J215, and J216 .................................... 17

Backplane Specifications................................................................. 17

System Synchronization Clock (PXI_CLK10, PXIe_CLK100,

PXIe_SYNC100) Specifications................................................... 18

10 MHz System Reference Clock: PXI_CLK10...................... 18

100 MHz System Reference Clock: PXIe_CLK100 and

PXIe_SYNC100 .................................................................... 18

External Clock Source .............................................................. 19

18-Slot NI PXIe-1065 Backplane Installation Guide 2 ni.com

PXIe_SYNC_CTRL..................................................................19

PXI Differential Star Triggers (PXIe-DSTARA,

PXIe-DSTARB, PXIe-DSTARC) ..........................................20

Pinouts .....................................................................................................20

System Controller Slot Pinouts ........................................................21

System Timing Slot Pinouts .............................................................22

Peripheral Slot Pinouts .....................................................................24

Hybrid Slot Pinouts ..........................................................................26

NI PXIe-1065 Backplane Overview

This section provides an overview of the backplane features for the

NI PXIe-1065 chassis. Figure 1 shows the backplane.

Figure 1. 18-Slot NI PXIe-1065 Backplane

©National Instruments Corporation 3 18-Slot NI PXIe-1065 Backplane Installation Guide

Interoperability with CompactPCI

With the NI PXIe-1065, you can use the following devices in a single PXI

Express system:

• PXI Express-compatible products

• CompactPCI Express-compatible 4-Link system controller products

• CompactPCI Express-compatible Type-2 peripheral products

• PXI peripheral products

• Standard CompactPCI peripheral products

System Controller Slot

The system controller slot is slot 1 of the backplane and is a 4-Link

configuration system slot as defined by the CompactPCI Express and

PXI Express specifications. It has three system controller expansion slots

for system controller modules that are wider than one slot. These slots

allow the system controller to expand to the left to prevent the system

controller from using peripheral slots.

The backplane routes a x4 PCI Express link from the system controller

slot to slots 7 and 8, and a x1 PCI Express link to a PCI Express to PCI

Translation Bridge on the backplane. The PCI Express to PCI Translation

Bridge on the backplane provides a 32-bit/33 MHz PCI bus to slots 2 to 7.

The second PCI Translation Bridge provides PCI bus to slots 11, 12, 13, 15,

16, 17, and 18 (not to slot 14).

A x4 link goes to the PXI Express switch and the PCI Express connectivity

of slots 9 to 14 is connected through the switch.

The system controller slot also has connectivity to some PXI features, such

as PXI_CLK10, PXI Star, PXI Trigger Bus, and PXI Local Bus 6.

The system controller can control the power supply with the PS_ON#

signals. A logic low on this line turns on the power supply.

Note The Inhibit Mode switch on the chassis rear panel must be in the Default position

for the system controller to control the power supply. Refer to the Inhibit Mode Switch

section of Chapter 2, Installation and Configuration, in the NI PXIe-1065 User Manual for

details about the Inhibit Mode switch.

18-Slot NI PXIe-1065 Backplane Installation Guide 4 ni.com

Hybrid Peripheral Slots

The backplane includes four hybrid peripheral slots as defined by the PXI-5

PXI Express Hardware Specification: slot 7 and slots 11–13. A hybrid

peripheral slot can accept the following peripheral modules:

• A PXI Express peripheral with a x4 or x1 PCI Express link to the

system slot or through a switch to the system slot.

• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express

link to the system slot or through a switch to the system slot.

• A hybrid-compatible PXI peripheral module modified by replacing the

J2 connector with an XJ4 connector installed in the upper eight rows

of J2. Refer to the PXI Express Specification for details. The PXI

peripheral communicates through the backplane 32-bit PCI bus.

• A CompactPCI 32-bit peripheral on the backplane 32-bit PCI bus.

The hybrid peripheral slots provide full PXI Express functionality and

32-bit PXI functionality except for PXI Local Bus. The hybrid peripheral

slot connects only to PXI Local Bus 6 left and right.

PXI Peripheral Slots

Nine PXI peripheral slots accept PXI or CompactPCI peripherals: slots 2–6

and slots 15–18. These slots are on the backplane 32-bit PCI buses. These

slots offer full PXI functionality, but have no PXI Express features. The

64-bit PCI signals on the P2 connectors are not connected.

PXI Express Peripheral Slots

There are three PXI Express peripheral slots: slots 8–10. Slot 8 is directly

connected to the system slot with a x4 PCI Express link. Slots 9 and 10 are

connected to the system slot through a PCI Express switch. PXI Express

peripheral slots can accept the following modules:

• A PXI Express peripheral with a x4 or x1 PCI Express link to the

system slot or through a switch to the system slot.

• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express

link to the system slot or through a switch to the system slot.

©National Instruments Corporation 5 18-Slot NI PXIe-1065 Backplane Installation Guide

System Timing Slot

The system timing slot is slot 14. The system timing slot accepts the

following peripheral modules:

• A PXI Express system timing module with a x4 or x1 PCI Express link

to the system slot through a PCIe switch.

• A PXI Express peripheral with a x4 or x1 PCI Express link to the

system slot through a PCIe switch.

• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express

link to the system slot through a PCIe switch.

The system timing slot has three dedicated differential pairs

(PXIe_DSTAR) connected from the TP1 and TP2 connectors to the XP3

connector for each PXI Express peripheral or hybrid peripheral slot, as well

as routed back to the XP3 connector of the system timing slot, as shown in

Figure 2. You can use the PXIe_DSTAR pairs for high-speed triggering,

synchronization, and clocking. Refer to the PXI Express Specification for

details.

The system timing slot also has a single-ended (PXI Star) trigger connected

to every slot. Refer to Figure 2 for details.

The system timing slot has a pin (PXI_CLK10_IN) through which a system

timing module can source a 10 MHz clock to which the backplane

phase-locks. Refer to the System Reference Clock section for details.

The system timing slot has a pin (PXIe_SYNC_CTRL) through which a

system timing module can control the PXIe_SYNC100 timing. Refer to the

PXI Express Specification and the PXIe_SYNC_CTRL section for details.

18-Slot NI PXIe-1065 Backplane Installation Guide 6 ni.com

Figure 2. PXIe_DSTAR and PXI Star Connectivity Diagram

PXI Local Bus

The PXI backplane local bus is a daisy-chained bus that connects each

peripheral slot with adjacent peripheral slots to the left and right, as shown

in Figure 3.

The backplane routes the full 13-line PXI Local Bus between adjacent PXI

slots (slots 2–6 and 15–18) and PXI Local Bus 6 between all other slots.

Refer to Figure 3 for details. The left local bus 6 from slot 1 is not routed

anywhere, and the right local bus signals from slot 18 are not routed

anywhere.

Local bus signals may range from high-speed TTL signals to analog signals

as high as 42 V.

XP4

XP3

TP2

TP1

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP2

XP1

PXIe_DSTAR 11

PXIe_DSTAR 8

PXIe_DSTAR 6

PXIe_DSTAR 5

PXIe_DSTAR 3

PXIe_DSTAR 2

PXIe_DSTAR 1

PXIe_DSTAR 4

PXI STAR 3

PXI STAR 1

PXI STAR 2 PXI STAR 9

PXI STAR 7

PXI STAR 6

PXI STAR 5

PXI STAR 4

PXI STAR 8

PX STAR 11

PX DSTAR 10

PXI STAR 13

PXI STAR 12

PXI STAR 15

PXI STAR 14

PXI STAR 16

PXI STAR 0

7H11 HH

12 H

13 14 15

216 17 18

©National Instruments Corporation 7 18-Slot NI PXIe-1065 Backplane Installation Guide

Initialization software uses the configuration information specific to each

adjacent peripheral module to evaluate local bus compatibility.

Figure 3. PXI Trigger Bus and Local Bus Connectivity Diagram

PXI Trigger Bus

All slots on the same PXI bus segment share eight PXI trigger lines. You

can use these trigger lines in a variety of ways. For example, you can use

triggers to synchronize the operation of several different PXI peripheral

modules. In other applications, one module in the system timing slot can

control carefully timed sequences of operations performed on other

modules in the system. Modules can pass triggers to one another, allowing

precisely timed responses to asynchronous external events the system is

monitoring or controlling.

The PXI trigger lines from adjacent PXI trigger bus segments can be routed

in either direction across the PXI trigger bridges through buffers. This

allows you to send trigger signals to, and receive trigger signals from, every

slot in the chassis. You can configure static trigger routing (user-specified

line and directional assignments) through Measurement & Automation

Explorer (MAX). Dynamic routing of triggers (automatic line assignments)

is supported through certain National Instruments drivers such as

NI-DAQmx.

XP4

XP3

TP2

TP1

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP2

XP1

PXI_LB6

PXI_LB (12:0)

PXI

Trigger Bus

Buffer Bridge

PXI

Trigger Bus

Buffer Bridge

PXI Trigger Bus Segment 1 PXI Trigger Bus Segment 2 PXI Trigger Bus Segment 3

7H11 HH

12 H

13 14 15

216 17 18

18-Slot NI PXIe-1065 Backplane Installation Guide 8 ni.com

Note Although you can route any trigger line in either direction, you cannot route it in

more than one direction at a time.

System Reference Clock

The NI PXIe-1065 backplane supplies the PXI 10 MHz system clock signal

(PXI_CLK10) independently driven to each peripheral slot, and

PXIe_CLK100 and PXIe_SYNC100 to the PXI Express slots, hybrid slots,

and system timing slot.

An independent buffer (having a source impedance matched to the

backplane and a skew of less than 1 ns between slots) drives PXI_CLK10

to each peripheral slot. Refer to Figure 4 for the PXI_CLK10 routing

configuration. You can use this common reference clock signal to

synchronize multiple modules in a measurement or control system.

An independent buffer drives PXIe_CLK100 to the PXI Express peripheral

slots, hybrid peripheral slots, and system timing slot. Refer to Figure 4 for

the routing configuration of PXIe_CLK100. These clocks are matched in

skew to less than 100 ps. The differential pair must be terminated on the

peripheral with LVPECL termination for the buffer to drive PXIe_CLK100,

so that when there is no peripheral or a peripheral that does not connect to

PXIe_CLK100, no clock is driven on the pair to that slot.

An independent buffer drives PXIe_SYNC100 to the PXI Express

peripheral slots, hybrid peripheral slots, and system timing slot. Refer to

Figure 4 for the routing configuration of PXIe_SYNC100. The differential

pair must be terminated on the peripheral with LVPECL termination for the

buffer to drive PXIe_SYNC100, so that when there is no peripheral or a

peripheral that does not connect to PXIe_SYNC100, no SYNC100 signal

is driven on the pair to that slot.

©National Instruments Corporation 9 18-Slot NI PXIe-1065 Backplane Installation Guide

Figure 4. Distribution of PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100

PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 have the default timing

relationship described in Figure 5.

Figure 5. System Reference Clock Default Behavior

To synchronize the system to an external clock, you can drive PXI_CLK10

from an external source through the PXI_CLK10_IN pin on the system

timing slot. Refer to Table 11, XP4 Connector Pinout for the System Timing

Slot, for the pinout. When a 10 MHz clock is detected on this pin, the

backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and

PXIe_SYNC100 signals to this external clock and distributes these signals

to the slots. (Refer to Figure 4 for the distribution of PXI_CLK10,

PXIe_CLK100, and PXIe_SYNC100.) Refer to Backplane Specifications

for the specification information for an external clock provided on the

PXI_CLK10_IN pin of the system timing slot.

XP4

XP3

TP2

TP1

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP4

XP3

XP2

XP1

10 MHz

REF IN

10 MHz

REF OUT

PXI_CLK10_IN

PXIe_CLK100

PXIe_SYNC100

PXI_CLK10

7H11 HH

12 H

13 14 15

216 17 18

PXIe_CLK100

PXI_CLK10

PXIe_SYNC100

012345678901234567890123456789

18-Slot NI PXIe-1065 Backplane Installation Guide 10 ni.com

You also can drive a 10 MHz clock on the 10 MHz REF IN pin of connector

J206. When a 10 MHz clock is detected on this connector, the backplane

automatically phase-locks the PXI_CLK10, PXIe_CLK100, and

PXIe_SYNC100 signals to this external clock and distributes these signals

to the slots. (Refer to Figure 4 for the distribution of PXI_CLK10,

PXIe_CLK100, and PXIe_SYNC100.) Refer to Backplane Specifications

for the specification information for an external clock provided on the

10 MHz REF IN pin of connector J206.

If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the

system timing slot and the 10 MHz REF IN pin of connector J206, the

signal on the system timing slot is selected. Refer to Table 1, which

explains how the backplane selects the 10 MHz clocks.

A copy of the backplane PXI_CLK10 is exported to the 10 MHz REF OUT

pin of connector J206. An independent buffer drives this clock. Refer to

Backplane Specifications for the specification information for the 10 MHz

REF OUT signal on connector J206.

PXIe_SYNC_CTRL

PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10.

The frequency of PXIe_SYNC100 is 10/nMHz, where nis a positive

integer. The default for nis 1, giving PXIe_SYNC100 a 100 ns period.

However, the backplane allows nto be programmed to other integers. For

example, setting n= 3 creates a PXIe_SYNC100 with a 300 ns period while

still maintaining its phase relationship to PXI_CLK10. The nvalue can be

any positive integer from 1 to 255.

Table 1. Backplane External Clock Input Truth Table

System Timing Slot

PXI_CLK10_IN

Connector J206

10 MHz REF IN

Backplane PXI_CLK10,

PXIe_CLK100, and PXIe_SYNC100

No clock present No clock present Backplane generates its own clocks

No clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100, and

PXIe_SYNC100 all phase-locked to

connector J206—10 MHz REF IN

10 MHz clock present No clock present PXI_CLK10, PXIe_CLK100, and

PXIe_SYNC100 all phase-locked to

system timing slot—PXI_CLK10_IN

10 MHz clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100, and

PXIe_SYNC100 all phase-locked to

system timing slot—PXI_CLK10_IN

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