Lattice Semiconductor LatticeXP2 Manual de usuario

May 2008

Revision: EB29_01.4

LatticeXP2 Standard Evaluation Board

User’s Guide

LatticeXP2 Standard

Lattice Semiconductor Evaluation Board User’s Guide

Introduction

The LatticeXP2™ Standard Evaluation Board provides a convenient platform to evaluate, test and debug user

designs. The board features a LatticeXP2-17 FPGA in a 484 fpBGA package. The LatticeXP2 I/Os are connected

to a rich variety of interfaces described later in this document.

This document (including the schematics in the appendix) describes LatticeXP2 Standard Evaluation Boards

marked as Rev 000. This marking can be seen on the etching on the back of the printed circuit board, under the

Lattice Semiconductor logo.

The LatticeXP2 is a third-generation non-volatile FPGA device. It combines a Look-up Table (LUT) based FPGA

fabric with Flash Non-volatile cells in a ﬂexiFLASH™ architecture. The ﬂexiFLASH approach provides beneﬁts such

as instant-on, small footprint, on chip storage with FlashBAK™ embedded block memories and Serial TAG memory

and design security. The LatticeXP2 also supports live updates with TransFR™, 128-bit AES Encryption and Dual-

Boot technologies. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase

Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP™ blocks.

For a full description of the LatticeXP2 FPGA, see the Lattice website for data sheets, technical notes, technology

summaries and more: www.latticesemi.com.

Some common uses for the LatticeXP2 Standard Evaluation Board include:

• A Single Board Computer system

• An analog-to-digital, and digital-to-analog mixed signal source/sink

• A platform for evaluating the Input/Output (I/O) characteristics of the FPGA

Features

Key features of the LatticeXP2 Standard Evaluation Board include:

• LatticeXP2 FPGA 484-pin ﬁne pitch Ball Grid Array device (LFXP2-17E-6F484C)

• Single printed circuit board solution

• Eight LEDs for visual feedback

• Seven-segment LED

• Eight-position switch input

• General purpose push buttons

• SRAM memory for microprocessor applications

• Compact Flash connector for adding peripherals

• RS232 DB9 Female connector

• LCD connector with backlight and contrast controls

• IEEE 1149.1 JTAG programming/boundary-scan interface

• Built-in USB download for use with ispVM

software

• Built-in power supply operating from a 5V DC input

• Power supply manager for testing supply sequencing

• Selectable voltage for bank 6 I/O

• Replaceable oscillator for reference clocks

• SMA connectors to LatticeXP2 clock input/general purpose I/O pins

• 100mil center-center test point grid

LatticeXP2 Standard

Lattice Semiconductor Evaluation Board User’s Guide

Other items included with this board:

• USB Cable (for programming)

• AC adapter (5V DC output, international AC input)

Additional Resources

Additional resources for this board can be downloaded from the web at www.latticesemi.com/boards. Navigate to

the appropriate evaluation board to ﬁnd items such as; updated documentation, software, sample designs and

demos, and more. We will continue to add resources to this web page. If you wish to be notiﬁed when additional

resources are available, click the

subscribe to page updates

icon at the top-right of the screen.

General Description

The heart of the board is the LatticeXP2 non-volatile FPGA. The board provides several different interconnections

and support devices that permit it to be used for a variety of purposes. The SRAM, RS232, and CF connector are

useful for microprocessor evaluation functions. The CF connector is also useful for expansion purposes. It provides

the ability to add storage, or communication capabilities to the board.

Other features on the board are useful for evaluation of the LatticeXP2 FPGA or development of more complex

solutions. The A/D, D/A, and digital potentiometer are helpful for mixed signal applications. SMA connections can

be used for the evaluation of high-speed differential signals, and protocols. (

Note: the SMA connectors are not pop-

ulated by default, but SMA connector footprints are available

). The SPI memory showcases the failsafe capabilities

of the LatticeXP2.

The board also acts as a showcase for the small, cost effective ispPAC

-POWR607 Power Manager device. The

ispPAC-POWR607 is a programmable device useful for safely managing the power supply system on the board. It

can be used to sequence and monitor the voltages on the LatticeXP2 Standard Evaluation Board.

Functional Description

The LatticeXP2 Standard Evaluation Board is comprised of several primary functional blocks as shown in Figure 1.

In the descriptions below, locations of components and board features are described relative to a compass symbol

placed adjacent to the Lattice Semiconductor Corp. logo. For example, the 8-position DIP switch is on the south-

west corner of the board, and the RS232 DB9 connector is on the northeast corner of the board.

LatticeXP2 Standard

Lattice Semiconductor Evaluation Board User’s Guide

Figure 1. LatticeXP2 Standard Evaluation Board

Power Supply

The LatticeXP2 Standard Evaluation Board features a single coaxial input connector to apply power. The coaxial

connector is located at the southwest side of the board. A 5V DC source must be applied to power the board.

The 5V input voltage is used to power the ispPAC-POWR607 Power Manager device (U1). The input voltage is reg-

ulated down with a zener diode and a transistor. The Power Manager uses this supply rail to boot and run a power

up sequence. While the LatticeXP2 does not require any speciﬁc order for the voltage rails to be applied, the Power

Manager can be used to try a wide variety of sequence options.

The Power Manager controls the enable inputs of three Bellnix BSV-m DC/DC converters. The Bellnix BSV-m is a

point-of-load power supply. Each point-of-load supply is placed physically near the DC load. In this case the DC

load of interest is the LatticeXP2 FPGA. There are three Bellnix converters on the LatticeXP2 Standard Evaluation

Board. One supplies the LatticeXP2 core voltage, which is 1.2V. Another supplies the VCCAUX, VCCIO1/2/3/4/5/7,

and all other 3.3V logic on the board. The third converter is adjustable from 1.1V to 2.5V and can be used to power

VCCIO6.

The ispPAC-POWR607 is pre-programmed to initialize the power system in a speciﬁc order. The order is arbitrary,

and is not a power-sequencing guideline for the LatticeXP2. The ispPAC-POWR607 starts by turning on the 1.2V

core voltage. It does not turn on any other supply on the board until the 1.2V supply reaches a programmed thresh-

USB Programming

Connector

DIP

Switch

ispPAC-POWR607

SRAM

MachXO

SMA Connector

Footprint

SMA

Connector

Footprint

SMA

Connector

Footprint

DAC

Oscillator

ADC

RS232

PHY

RS232 DB9

Compact Flash

LatticeXP2 FPGA

LatticeXP2 Standard

Lattice Semiconductor Evaluation Board User’s Guide

old. Once the 1.2V supply rail is stable, the Power Manager turns on the 3.3V rail. Once again it waits for the 3.3V

supply rail to stabilize before performing any other action.

The Power Manager, having detected both the 1.2V and 3.3V supplies as stable, turns on the adjustable supply.

Since the adjustable supply is not critical to the operation of the board the Power Manager does not wait for it to

stabilize.

After the board is fully powered, the ispPAC-POWR607 monitors for power-down requests – pin IN1 for a high-

going transition. When IN1 is pulled above V

the Power Manager de-asserts the enable pins on all of the DC con-

version devices, effectively powering the board down. The Power Manager continues to monitor the IN1 input, and

when it is pulled below V

it restarts the board in the same order as described earlier.

U3, U4, and U6, once enabled by the ispPAC-POWR607, supply all power to the board. Adjacent to U3 and U6 are

current sense resistors. These are intended to permit the measurement of the current ﬂowing from each of the

power supplies. The current sense resistors are 10mOhm in value.

Table 1. LatticeXP2 Current Sense Resistors

The LatticeXP2 Standard Evaluation Board also permits the voltage on VCCIO6 to be changed. Using a jumper on

J12 controls the voltage applied to VCCIO6. The voltages that can be supplied are shown in Table 2.

Table 2. LatticeXP2 IO Voltage Selection

Programmability

There are three programmable devices on the board. Of primary interest for the FPGA user is the LatticeXP2. How-

ever, the ispPAC-POWR607 Power Manager, and the MachXO™2280 are also important to the overall operation of

the board.

USB Download Cable

The evaluation board has a download cable built in. The components for the built-in download cable are located in

the southeast corner of the board. The built-in cable consists of a USB Type-B connector, a USB microcontroller,

and a MachXO device.

To use the built-in download cable, simply connect a standard USB cable (included) from J21 to your PC (with

ispVM System installed). The USB Hub on the PC will detect the addition of the USB Function making the built-in

cable available for use with Lattice’s ispVM System software.

The USB cable is connected in parallel to J34. J34 is a 1x10 100mil header that is provided for use with an external

Lattice download cable (available separately). A Lattice parallel port or USB download cable can be attached to the

board using J34.

Use of the built-in cable must be mutually exclusive to use of an external download cable. When using an external

download cable the jumper on J28 must be moved to shunt pins 1-2. This tri-states the MachXO device, preventing

it from interfering with the external download cable.

Resistor Voltage Supply

R12 Vcore

R17 VCCAUX, VCCIO 1/2/3/4/5/7

Jumper

Block J12 VCCIO6 Voltage

1-2 User input from TP14/TP15

3-4 VAdj from U4 (1.1V-2.5V). Use R10 to adjust the output.

5-6 3.3V

LatticeXP2 Standard

Lattice Semiconductor Evaluation Board User’s Guide

Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD®

Cable or USB cable. Always connect an ispDOWNLOAD Cable’s GND pin (black wire), before connecting any

other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeXP2 FPGA and render the

board inoperable.

LatticeXP2 JTAG Access

The default conﬁguration of the LatticeXP2 Standard Evaluation Board connects the built-in JTAG cable/J34 to only

access the LatticeXP2 FPGA. The serial output from the USB cable/J34 is routed directly to the serial input of the

LatticeXP2 FPGA. The serial output from the LatticeXP2 is routed to J29. A jumper on J29 directs the serial output

of the LatticeXP2 back to the USB cable/J34. This is the factory default conﬁguration and is expected to be the pri-

mary JTAG mode for most users.

The board can also be conﬁgured to access the LatticeXP2 FPGA, and a chained evaluation board. A 1x10 cable

(not supplied) can be connected locally to J33 and the opposite end of the cable can be attached to another system

that has a JTAG chain.

Chaining the LatticeXP2 Standard Evaluation Board with another board is accomplished by changing the routing of

the TDI/TDO/TMS/TCK I/Os. Jumpers J29, J30, J31, and J32 determine how the TDI/TDO chain and TMS pins

behave.

Table 3. LatticeXP2 Single/Multi-Board Conﬁguration

J31, when shorted, adds a pull-down resistor to the TCK signal. Only one chained evaluation board should have a

pull-down on TCK.

Figure 2. Single/Multi-Board Jumpers

Jumper

Block LatticeXP2 Board Only

LatticeXP2 Board Plus

Off-board JTAG Chain

J29 1-2 2-3

J30 Open 1-2

J31 1-2 (1K pull-down resistor on TCK) 1-2 (off-board chain does not pull TCK to GND).

Open (off-board chain pulls TCK to GND).

J32 Open 1-2

JTAG

LatticeXP2 + EvalLatticeXP2 Only

Offboard

JTAG Chain

J33

J34

J29

J30

J31

J32

J28

LatticeXP2 Standard

Lattice Semiconductor Evaluation Board User’s Guide

The JTAG port is used for programming the LatticeXP2 and can also be used for programming the off-chip SPI

PROM. The LatticeXP2 FPGA has several modes it can use to get conﬁguration data. Available sources for conﬁg-

uration data are:

• JTAG programming

• On-chip Flash PROM (with automatic failsafe)

• Off-chip SPI PROM (LatticeXP2 fetches conﬁguration data)

• Off-chip SPI interface (LatticeXP2 receives conﬁguration data from a master)

The JTAG interface to the LatticeXP2 provides several methods to program the LatticeXP2 and devices attached to

the LatticeXP2. JTAG programming can be used to program the LatticeXP2 in SRAM mode (volatile). It can also be

used to program the on-chip LatticeXP2 Flash memory (non-volatile). It also provides the ability to program an

attached SPI PROM (U5). The SPI PROM is used for storing failsafe conﬁguration data.

ispPAC-POWR607 JTAG Access

The ispPAC-POWR607 Power Manager comes from the factory with a default power sequence. It may be desired

for evaluation purposes to try other power sequences. Connector J5 is the access point for the ispPAC-POWR607

JTAG I/O. See the Power Supplies and Supply Control section below for the details of using the ispPAC-POWR607.

SPI Slave Connection

The LatticeXP2 has conﬁguration pins that deﬁne how the device will ﬁnd a non-volatile bitstream to conﬁgure

itself. In most cases the conﬁguration pins will be set to have the LatticeXP2 act as a master device and actively

read data from its internal Flash or from the attached SPI PROM.

The LatticeXP2 can also be conﬁgured to act as a slave device, and accept bitstream data from an external master.

The master can be connected to either the JTAG port, or it can be connected to the SPI interface. The LatticeXP2

Standard Evaluation Board provides a 1x10 header, J11, that permits an off-chip SPI master to program the

LatticeXP2 FPGA.

MachXO JTAG Connection

The MachXO’s primary function is to be the USB download cable interface for the LatticeXP2. However, the

MachXO is a PLD, and has some connections to the LatticeXP2. It is possible, therefore, to use the LatticeXP2 and

the MachXO together. The MachXO can be reprogrammed with custom logic using connector J23. The factory pro-

gram for the MachXO is available on-line to restore the device if needed.

LatticeXP2 and Support Interfaces

The LatticeXP2 Standard Evaluation Board provides a variety of support features for evaluating the performance

and functionality of the LatticeXP2 FPGA. A FPGA can be used for a large number of different applications. The

LatticeXP2 Standard Evaluation Board attempts to balance the ability to test I/O and the ability to use interest-

ing/common logic functions.

The evaluation board has features designed to make it easier to locate resources on the board and resources con-

nected to the FPGA.

• Devices are numbered in a consistent fashion. Each device starts at reference designator ‘1’ in the northwest

corner of the board (i.e. R1, C1, U1, L1...). The component number increases by one in a columnar fashion (i.e.

southward). When the south edge of the board is reached, the count resumes slightly east, and at the north side

of the board. Thus, the highest numbered components will always be in the southeast corner of the board. This

same numbering sequence is applied to the secondary side of the printed-circuit board.

• Adjacent to most of the switch inputs, LED outputs, SMA connectors, and test points is the alphanumeric position

of the pin on the LatticeXP2 FPGA. For example: next to the SMA connector J1, in the silkscreen, is the designa-

tor (P1). Thus LatticeXP2 (U7) pin P1 is connected to the center post of J1.

• SMA connectors have an open white rectangle area near them denoting the positive side of a matched pair. The

negative side of the matched pair has a solid ﬁlled white rectangular area.

LatticeXP2 Standard

Lattice Semiconductor Evaluation Board User’s Guide

Push-Buttons and Status LEDs

There are four push-buttons and three LEDs on the south edge of the evaluation board. Switch SW2 and SW3, the

westernmost, are routed to generic LatticeXP2 I/Os. One of these buttons typically acts as a reset switch, providing

a reset pulse to logic inside the LatticeXP2.

SW4, which is near the USB connector, is tied to the LatticeXP2’s PROGRAMn input. Pressing this switch will

cause the LatticeXP2 to reprogram itself, as long as CFG0 is set to V

SW5 is adjacent to SW4 and is the reset button for the built-in USB download cable. Pressing this button will cause

the USB cable to re-enumerate with the USB hub.

In the southeast corner of the board are three status LEDs. These indicate the state of the LatticeXP2’s Done,

INITn, and PROGRAMn I/O pins. During normal operation the Done and the INITn LEDs will illuminate.

Global Output Enable

The LatticeXP2 has a global output enable control. The GOE is routed to J15, and the factory default setting on J15

is to enable the LatticeXP2 outputs. The jumper on J15 can be moved from the default setting (open) to disable (tri-

state) all of the LatticeXP2 I/Os.

Table 4. Global Output Enable

Prototype Grid

The board provides a small 100mil center-center prototype area. The prototype area has a set of plated through-

holes in a 5x8 pattern. There are a total of 16 I/O pins connected in the prototype area. The topmost row is a series

of eight horizontal plated through-holes connected to the ground plane. South of this row is a row of plated through-

holes connected to the LatticeXP2 device. The rows alternate GND/signal/GND/signal/GND from north to south.

Some of the plated through-holes are connected to LatticeXP2 Bank 6. It is possible to modify the I/O voltage on

Bank 6 using J12.

Table 5. Testpoint Connections

LED Displays

In the northwest corner of the board is a set of eight green 0603 form factor LEDs. These LEDs are connected to

IO pins dedicated to driving the LEDs. Table 6 shows the LatticeXP2 I/O pins that control each LED. The LEDs illu-

minate when the corresponding I/O is driven to V

Jumper Block

J15 Output Enable State

Shunt Outputs disabled (tri-state)

Open* Outputs enabled

Bank # LatticeXP2 I/O Bank # LatticeXP2 I/O

6T3 6 U3

6 U2 6 V3

6 R3 6 R4

6 P4 6 M3

6 N2 6 M4

3 W22 3 W20

3 U20 3 V20

3 U21 3 V22

LatticeXP2 Standard

Lattice Semiconductor Evaluation Board User’s Guide

Table 6. LED Pin Assignments

In addition to the discrete chip LEDs there is a single 7-segment display. Like the discrete LEDs, a V

level will

cause a segment to illuminate. The segment order is deﬁned in the Lumex LDS-A304RI Data Sheet.

Table 7. 7-Segment LED Pin Assignments

Switches

The evaluation board provides a set of eight simple toggle switches at the southwest edge of the board. The silk-

screen calls out the alphanumeric location of the I/O on the FPGA. The switch, when in the up position, is pulled to

VCCIO6 through a 10K resistor. When in the down position, the switch is tied to ground.

Table 8. SW1 Switch Pin Assignments

Oscillator and Clock Inputs

FPGA designs are almost without exception created with logic synchronous to some reference frequency. The

LatticeXP2 Standard Evaluation Board provides a built-in oscillator that provides a reference frequency for syn-

chronous FPGA logic. Reference frequencies can be applied to other LatticeXP2 clock inputs as well.

The LatticeXP2 board provides a low-voltage (3.3V) DIP oscillator. The oscillator is installed in a 14-pin DIP socket.

The socket permits the use of either a half-size or full-size DIP oscillator.

LED LatticeXP2 I/O

D2 J2

D3 J1

D4 K2

D5 K1

D6 M2

D7 M1

D8 L4

D9 L3

Segment LatticeXP2 I/O

AJ4

B H4

C F4

D E4

E E3

F H3

G G3

DP F3

Switches LatticeXP2 I/O

SW1-0 AA3

SW1-1 AA2

SW1-2 AA1

SW1-3 Y4

SW1-4 Y3

SW1-5 Y2

SW1-6 Y1

SW1-7 W3

LatticeXP2 Standard

Lattice Semiconductor Evaluation Board User’s Guide

Figure 3. Oscillator Positions

The output from the oscillator is routed to two series resistors. One of the series resistors is connected to a primary

clock input pin. The other resistor is connected to a PLL input pin. It is important to mention that DIP socket pin 8 is

shorted to pin 11, so it is not possible to input two different clock frequencies from the socket. In order to provide a

frequency on the primary clock input that is different from the PLL clock input it is necessary to remove one of the

two series termination resistors, and add a temporary modiﬁcation to inject an electrically isolated clock signal.

Differential/50 Ohm Input/Output

The LatticeXP2 Standard Evaluation Board provides connections to differential I/O pins. The circuit board traces for

these connections are nominally 50-ohm impedance. Some of the differential I/O pins are inputs to primary or PLL

clock drivers. If the built-in oscillator in socket XU1 does not provide the right kind of input clock the SMA connec-

tors listed in Table 9 can be used to provide additional reference clock frequencies.

Table 9. Differential/50 Ohm Trace Pin Assignments

Power Supplies and Supply Control

The LatticeXP2 Standard Evaluation Board operates from a 5V DC input voltage. The input voltage is supplied via

J9, a coaxial DC input jack. The following components operate using the 5V input:

• ispPAC-POWR607 Power Manager

• Bellnix DC/DC converters

Connector Pair LatticeXP2 I/O Clock Input

J1 P1 N

J2 R1 N

J3 Physical connection T1 Y (P)

Silkscreen text W4

J4 Physical connection U1 Y (N)

Silkscreen text Y5

J6 P2 N

J10 P3 N

J7 T2 (3) / R2 (4) N

J8 Physical connection Y5 (3) / W4 (4) N

Silkscreen text U1 (3) / T1 (4)

J24 J22 Y (P)

J25 K22 Y (N)

J26 K21 Y (P)

J27 L21 Y (N)

Full-Size Placement Half-Size Placement

Pin 1

OSC OSC

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