Lattice Semiconductor IspClock5400D Manual de usuario

July 2010

Revision: EB50_01.2

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ispClock5400D Evaluation Board

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User’s Guide

ispClock5400D Evaluation Board

Lattice Semiconductor User’s Guide

Introduction

Thank you for choosing the Lattice Semiconductor ispClock™ device family!

This guide describes how to start using the ispClock5400D Evaluation Board, an easy-to-use platform for evaluat-

ing and designing with the ispClock5406D in-system-programmable differential clock distribution device. The evalu-

ation board can be used stand-alone to review the performance and in-system programmability of the

ispClock5406D device or as a companion board and clock source for LatticeECP3™ FPGA evaluation boards:

• LatticeECP3 Serial Protocol Board

• LatticeECP3 Video Protocol Board

Please visit www.latticesemi.com/products/fpga/ecp3/ecp3evalboards for more information, demonstrations, and

documentation on each LatticeECP3 evaluation board.

About the ispClock5406D Device

This board features an ispClock5406D device that provides in-system-programmable zero delay universal fan-out

buffers for use in clock distribution applications. The on-board ispClock5406D is a 6-output clock distribution IC.

Differential ultra low skew outputs are organized with two banks per group. Each bank may be independently con-

figured to support separate I/O standards (LVDS, LVPECL, HSTL, SSTL, HCSL, and MLVDS) and output fre-

quency. In addition, each output provides independent programmable control of phase and time skew. All

configuration information is stored on-chip in non-volatile E2CMOS®memory.

The ispClock5406D devices provide extremely low propagation delay (zero-delay) from input to output using the

on-chip low jitter high-performance phase locked loop (PLL). A set of four fixed dividers can be used to generate

four frequencies derived from the PLL clock. These dividers are designed in powers of 2 only (2, 4, 8, and 16). The

clock output from any of the V-dividers can then be routed to any clock output pair through the output routing

matrix. The output routing matrix also enables routing of reference clock inputs directly to any output. For additional

details, please refer to the ispClock5400D Family Data Sheet.

Note: Static electricity can severely shorten the lifespan of electronic components.

• Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wristband.

• Store the evaluation board in the anti-static packaging provided.

• Always touch the SMA connector housing to equalize voltage potential between yourself and the board.

Features

The ispClock5400D Evaluation Board package includes:

•ispClock5400D Evaluation Board – The board features the following on-board components and circuits:

ispClock5406D programmable clock (ispPAC-CLK5406D-01SN48I)

– Crystal oscillator circuits

– Can oscillator circuit landing

– Resistor networks

– SMA connectors

–Powerjack

– Test and JTAG interface headers

•Pre-loaded Base Demo – The kit includes a pre-loaded demo design that highlights key performance character-

istics of the ispClock5406D device.

•Lattice ispDOWNLOAD™ Cable (HW-USBN-2A) – The ispDOWNLOAD cable provides a hardware connection

for in-system programming of the ispClock5406D device.

•User’s Guide – Provides information on powering, connecting lab equipment, and using the board as a clock

ispClock5400D Evaluation Board

Lattice Semiconductor User’s Guide

source for various Lattice FPGA evaluation boards. The contents of this user’s guide include demo operation,

top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board con-

nectors, switches and a complete set of schematics.

•QuickSTART Guide – Provides information on connecting the evaluation board, running the pre-loaded evalua-

tion demo.

The contents of this user’s guide include demo operation, programming instructions, top-level functional descrip-

tions of the evaluation board, descriptions of the on-board connectors, switches and a complete set of schematics

of the board. For a complete list of the various connections and interfaces used on the ispClock5400D Evaluation

Board, please refer to the schematics in Appendix A.

The ispClock5400D Evaluation Board is 100% lead free and RoHS compliant as Lattice Semiconductor Corpora-

tion is sensitive to environmental issues.

Additional resources relating to the ispClock5400D Evaluation Board are available on the Lattice web site. Go to:

www.latticesemi/.com/boards and navigate to the appropriate link. Updates to this document can be found there,

as well as sample programs and links to other related items.

Figure 1. ispClock5400D Evaluation Board

Software Requirements

Install the following software before you begin developing designs for the ispClock5400D Evaluation Board:

•PAC-Designer

®5.2 (ispClock5406D support)

•Optional: ispLEVER®/Pro (LatticeECP3 support)

•Optional: ispVM™ System 17.5

ispClock5400D Evaluation Board

Lattice Semiconductor User’s Guide

Hardware Requirements

The following hardware is recommended for evaluation and demonstrations:

• Four matched SMA cables, SMA-to-BNC, 6 inches to 3 feet in length

• ESD strap or proper ESD test environment

• ispClock5400D Evaluation Board

• Lattice ispDOWNLOAD Cable

• AC wall adaptor for 5V DC output

•Optional: LatticeECP3 Serial Protocol Board (LFE3-95EA-SP-EVN)

•Optional: LatticeECP3 Video Protocol Board (LFE3-95EA-V-EVN)

•Optional: BERT Analyzer

•Optional: Agilent 8133A Clock Generator

•Optional: 4-channel, high-speed oscilloscope

Demonstration Designs

A common application of the ispClock5406D and a low-cost CMOS oscillator is to provide a low-jitter clock source

for SERDES-based applications in high-performance communications and computing equipment. The evaluation

board includes three demos that illustrate key applications of the ispClock5406D in the context of clock distribution

applications:

•ispClock5406D Base Demo – A pre-programmed, base demo of ispClock5406D features: low-jitter, time/phase

skew output control and I2C interface.

•Period Jitter Measurement – A demonstration of how to connect and measure ispClock5400D period jitter per-

formance with a signal integrity analyzer.

•SERDES Reference Clock – A co-demonstration with the LatticeECP3 Serial Protocol or I/O Protocol boards.

•Video Reference Clock – A co-demonstration with the LatticeECP3 Video Protocol board.

Note: It is possible that you will obtain your evaluation board after it has been reprogrammed. To restore the factory

default demo and program it with other Lattice-supplied examples, see the Download Demo Designs section of this

document.

Base Demo of the ispClock5406D

The base demo consists of setting up the ispClock5400D Evaluation Board hardware and test equipment to dem-

onstrate key features of the ispClock5406D device. The ability to adjust skew and frequency will be demonstrated

as well as programmable frequency, time and phase delay, reset functions and full dynamic control of internal reg-

isters through the on-board I2C bus interface.

Monitoring Clock Outputs

This section describes the procedure to monitor the evaluation board’s Bank 0 and Bank 2 clock outputs with a dig-

ital oscilloscope. Both banks are configured for LVDS output types.

To monitor clock outputs:

1. If you have not done so already, see the Programming the ispClock5400D Evaluation Board with ispVM section

of this document for details on set-up for the programming cable and applying power to the evaluation board.

ispClock5400D Evaluation Board

Lattice Semiconductor User’s Guide

2. Set DIP switches SW1 3 and 4 ON and all other switches OFF.

The blue LOCK LED lights to indicate the on-chip PLL is stable and locked to a reference clock.

3. Start PAC-Designer.

4. Choose File > Open…

The Open dialog appears.

5. Browse the Base_Demo_CLK5406D.PAC project and choose Open.

The ispPAC-CLK5406D schematic view appears.

Figure 2. ispClock5406D Schematic View

6. Choose File > Save As.

The Save As dialog appears.

7. Specify File name: Base_Demo_CLK5406D_rev.PAC and click Save.

PAC-Designer creates a new revision of the project.

8. Choose View > ispCLK Output Summary.

The Output Summary Sheet appears. The default demo will monitor the LVDS outputs driven by BANK_0 and

BANK_2.

Figure 3. Output Summary Sheet

ispClock5400D Evaluation Board

Lattice Semiconductor User’s Guide

9. If the board is not programmed with the demo project yet, press the Download icon on the top toolbar.

Figure 4. PAC-Designer Top Toolbar

The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.

Figure 5. Frequency Summary Dialog Box

10. Click OK.

PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.

11. Attach high-speed scope leads to the SMA sockets at BANK0 P, N and BANK2 P, N.

12. Set the scope input channel settings to 50 Ohm termination.

For this mode, we use LVDS and the 50 Ohm termination on each scope channel.

The waveforms shown are using 3’ long RG-316 cables with the SMA connectors. If the equipment has high

impedance probes or a differential probe, make sure that the LVDS BANK outputs have 100 Ohm termination

from BANK_P to BANK_N.

When operating properly, you should see four waveforms on the scope as shown in Figure 6. This represents

BANK0 and BANK2 output waveforms for both the BANK_P and BANK_N on each respectively. BANK0_P,N

are shown on the top pair, BANK2_P,N are shown on bottom pair. The full differential output would equal:

[BANK0_P minus BANK0_N] as well as on BANK2.

See the tables in the schematic (Appendix A) showing termination resistor options.

ispClock5400D Evaluation Board

Lattice Semiconductor User’s Guide

Figure 6. Scope Plot - Four Differential Outputs

Note: For user-designed boards and other applications, refer to the data sheet configurations and the schematics

of Appendix A. The schematic shows different resistor combinations for the different output bank settings. In LVDS

mode the schematic uses a single 100 Ohm resistor between each BANK_P and BANK_N pin as a fully differential

output. The demo uses the default factory board assembly with zero Ohm resistors connecting the SMA terminals

directly to the output banks. This approach is for the demo only. Some of the waveforms displayed will only show

the positive side of each BANK output on the scope for simplicity and timing measurements.

Modify Clock Time Skew

This section describes the procedure to modify the time skew of the ispClock5406D output to eliminate the inherent

skew between output BANK_0 and BANK_2 due to device and cable parasitic.

To modify clock time skew:

1. Adjust the scope to display BANK0_P and BANK2_P signals only. Overlap the signals to compare the relative

skew.

ispClock5400D Evaluation Board

Lattice Semiconductor User’s Guide

Figure 7. Scope Plot - Bank 0 and Bank 2 Overlapped

Note that a small inherent skew of the outputs plus any set-up delay in cables is about 50-80ps.

2. In PAC-Designer choose Tools > Design Utilities…

The Design Utilities dialog appears.

3. Choose ispPAC-CLK54_Skew_Editor.exe and click OK.

The ISPPAC-CLK5406D Skew Editor appears.

Figure 8. ispPAC-CLK5406D Skew Editor

The Skew Editor allows you to graphically configure the ispClock5406D output skew. Waveforms are color

coded. All disabled outputs are indicated in gray, while active outputs are indicated in green or white. Skew is

adjusted by dragging the waveform edges with the mouse. Dragging the waveform specified as feedback (high-

lighted in green) will move every other waveform in the opposite direction.

The Phase Skew steps are larger steps than the Time Skew. In the demo design, the “PUD” Phase Unit Delay,

has steps of 0.31 ns and there are 16 steps for each bank. For the demo, the Time Skew step is 18 ps.

ispClock5400D Evaluation Board

Lattice Semiconductor User’s Guide

4. Position the mouse over the rising edge of the Bank2 Time waveform.

The cursor will changes to a double-arrow icon to indicate a waveform edit.

5. Click and hold the Bank 2 Time waveform, then drag it three units to the right.

The Setting field displays 3 and Time Skew (ps) displays 54.00.

6. Click the Write to Schematic button.

PAC-Designer updates the time skew setting of the project.

7. Click the Download icon on the top toolbar.

The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.

8. Click OK.

PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.

9. Note the updated scope display.

This waveform shows the de-skewed outputs.

Figure 9. Scope Plot - De-skewed Outputs

The programmable ispClock5406D Time Skew feature allows the device to account for very small incremental

delays and correct for system/board trace-level effects. The function is used to correct timing delays and line up

edges to either account for PCB layout or to help with clock system timing such as the set-up and hold times of

the circuit being driven.

Experiment with the Time Skew and visualize the results on the scope. The demo design time skew range

allows you to move clock edges from 18 ps to 270 ps. When finished, set back to the Time-Skew that yields the

best results for your set-up.

ispClock5400D Evaluation Board

Lattice Semiconductor User’s Guide

Invert Clock Output

This section describes the procedure to invert the ispClock5406D output. In this procedure you will use the

ispClock5406D Invert feature to invert Bank2 output.

To invert a clock output:

1. From the PAC-Designer schematic view, double-click the BANK_2+/BANK_2- Output Block.

The Output Settings for BANK_2 & BANK_3 dialog box appears.

Figure 10. Output Settings for BANK_2 & BANK_3

2. Choose Inverted = Yes from the BANK_2 section of the dialog and click OK.

PAC-Designer updates the output setting of the project.

3. Click the Download icon on the top toolbar.

The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.

4. Click OK.

PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.

5. Note the updated scope display.

The waveform shows the inverted BANK_2 output.

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