Lattice Semiconductor LatticeECP3 Versa Manual de usuario

July 2013

Revision: EB62_01.6

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LatticeECP3 Versa Evaluation Board

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User’s Guide

LatticeECP3 Versa Evaluation Board

User’s Guide

Introduction

The LatticeECP3™ Versa Evaluation Board allows designers to investigate and experiment with the features of the

LatticeECP3 Field-Programmable Gate Array. The features of the LatticeECP3 Versa Evaluation Board can assist

engineers with rapid prototyping and testing of their specific designs. The LatticeECP3 Versa Evaluation Board is

part of the LatticeECP3 Versa Development Kit. The guide is intended to be referenced in conjunction with demo

user’s guides to demonstrate the LatticeECP3 FPGA.

Figure 1. LatticeECP3 Versa Evaluation Board, Top Side

User

Switches

Status LEDs

USB

Programming

J3 – JTAG

Interface J13 – JTAG

Interface

On-Board

Clock

Management

Expansion Connectors

DDR3

Memory

SERDES Test

SMA Connectors

LED

Display

GSRn &

PROGRAMn

Push-buttons

10/100/1000

RJ-45

Connections

PCI Express x1

SPI Flash

Configuration

Memory

12V DC

Power Input

Features

• Half-length PCI Express form-factor

– Allows demonstration of PCI Express x1 interconnection

• Electrical testing of one full-duplex SERDES channel via SMA connections

• USB-B connection for UART and device programming

• Two RJ45 interfaces to 10/100/1000 Ethernet to GMII

• On-board Boot Flash

– 64M Serial SPI Flash

• DDR3-1333 memory components (64Mb/x16)

• Expansion mezzanine interconnection for prototyping

• 14-segment alpha-numeric display

• Switches, LEDs and displays for demo purposes

• ispVM™ programming support

• On-board reference clock sources

LatticeECP3 Versa Evaluation Board

User’s Guide

The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation

board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics.

Caution: The LatticeECP3 Versa Evaluation Board contains ESD-sensitive components. ESD safe practices should

be followed while handling and using the evaluation board.

LatticeECP3 Device

This board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin-compatible

LatticeECP3 devices in the 484-ball fpBGA (1mm pitch) package. A complete description of this device can be

found in the LatticeECP3 Family Data Sheet.

Note: The connections referenced in this document refer to the LFE3-35EA-8FN484C device.

Applying Power to the Board

The LatticeECP3 Versa Evaluation Board is ready to power on. The board can be supplied with power from a PCI

Express host system or standalone with an external wall power module.

The 12V DC input power source is fused with a surface mounted fuse, as noted in Ta ble 1.

Table 1. Board Power Supply Fuses – (See Appendix B, Figure 12)

Fuse Designator Description

F1 12V Input Supply Fuse

The board may be plugged into a host PC. Only plug the board into a PCI Express slot when the system is powered

off. Once inserted, the PC can be safely powered on.

Using the evaluation board outside of a PC chassis supply requires the factory-supplied wall supply module. Use of

other supplies is not suggested. GME Technology’s GFP181DA-1215B-1 (or equivalent) is provided with the

LatticeECP3 Versa Development Kit.

Figure 2. Power Distribution Scheme – (See Appendix B, Figure 12)

3_3V, +3.3V, 1.35 A, Power Status LED D9

12_0V

(5A fused)

Power Status LED D13

SW 1_5V, +1.5V, 1.1 A, Power Status LED D11

VCC_CORE, +1.2V, 1.35 A, Power Status LED D10

LDO SERDES 1_2V, +1.2V, 1A, Power Status LED D12

2_5V, +2.5V, 1.1 A, Power Status LED D31

Programming/FPGA Configuration

The LatticeECP3 Versa Evaluation Board has a built-in download controller for programming the LatticeECP3

FPGA. The built-in module consists of a USB Type-B connector and a USB UART device. To use the built-in down-

load cable, simply connect a standard USB cable (a USB-B to USB-A cable is included with the LatticeECP3 Versa

Development Kit) from J2 to your PC (with ispVM System software installed). The USB hub on the PC will detect

the addition of the USB function, making the built-in cable available for use with the ispVM System software. The

USB cable is connected in parallel to J3.

LatticeECP3 Versa Evaluation Board

User’s Guide

Alternate ispVM Download Interface

J3 is a 1x10 100mil header that is provided for use with an external Lattice download cable (available separately).

A USB download cable can be attached to the board using J3 to interface with the FPGA (U1).

Note: Resistors R38, R33, R32 and R36 need to be removed.

A separate header is provided to interface to a download cable for the ispClock™5406A clock device (U13). U13 is

not interfaced to the built-in download interface. U13 is factory-programmed for use with the reference designs and

should only be altered for customized designs.

A 10-pin JTAG connector is used in conjunction with the ispVM USB download cable to program and control the

device. A separate 10-pin header (J14) is provided for programming U13.

Table 2. ispVM JTAG Connector Pinout (J3 and J14) – (See Appendix B, Figure 5)

Pin Function Color

1PWR Red

2TDO Brown

3TDI Orange

4N/C —

5N/C —

6TMS Purple

7 GND Black

8TCK White

9N/C —

10 N/C —

ispVM Requirements

Note: An ispDOWNLOAD™ cable is included with Lattice Diamond®design software. This cable is not needed for

the typical use of this board since it includes the built-in download module and only requires the USB cable

included with the board. Standalone ispVM download cables may be purchased separately from Lattice.

After initial board setup, use the following procedure to program the board. Instructions assume that ispVM soft-

ware has been installed on a local PC.

Requirements:

• PC with ispVM System 18.0 (or later) programming software, installed with appropriate drivers (USB driver for

USB cable, Windows 7/XP/2000/NT parallel port driver for ispDOWNLOAD cable).

Note: An option to install these drivers is included as part of the ispVM System setup.

• ispDOWNLOAD cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.). Required only for alternative FPGA

programming and ispClock5406A reprogramming.

LatticeECP3 Versa Evaluation Board

User’s Guide

Board Programming

Configuration Status Indicators

(see Appendix B, Figure 13)

Figure 3. LatticeECP3 Status LEDs and Push-button Controls

The LEDs indicate the configuration status of the LatticeECP3 FPGA.

•D17 (red) illuminated indicates that programming was aborted or reinitialized, driving the INITN output low.

•D20 (green) illuminated indicates the successful completion of configuration by releasing the open collector

DONE output pin.

•D19 (red) illuminated indicates that PROGRAMN is low.

•D18 (red) illuminated indicates that GSRN is low.

PROGRAMN and GSRN

These push-button switches assert/de-assert the logic levels on PROGRAMN (SW2) and GSRN (SW1). Depress-

ing the button drives a logic level “0” to the device.

Programming Serial SPI Flash Memory

A serial SPI (16-pin TSSOP, 64M) Flash memory device (U8) is on-board for non-volatile configuration memory

storage. A STMicro M25P64VMF16 device is populated on-board.

The Serial SPI Flash memory device can be configured easily via its JTAG port. This mode enables the FPGA to

be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.

1. Connect the LatticeECP3 Versa Evaluation Board.

2. In the dialog box, select SPI Flash Programming Mode in the Device Access Option pull-down menu.

LatticeECP3 Versa Evaluation Board

User’s Guide

Figure 4. Device Information Dialog Screen

3. The SPI Serial Flash Device dialog box will open. In this box, select SPI Flash Erase, Program, Verify in the

Operation pull-down menu.

4. Select SPI Serial Flash in the Device Family pull-down menu, STMicro under the Vendor pull-down menu,

SPI-M2564 under the Device pull-down menu, and 16-lead SOIC under the Package submenu.

Figure 5. Select Device Dialog Box

LatticeECP3 Versa Evaluation Board

User’s Guide

Figure 6. Sample SPI Serial Flash Device Dialog Box

5. Click OK in the SPI Serial Flash Device dialog box. Then click OK in the Select Device dialog box. You will

return to the main configuration screen

6. From the main programming window, select Go from the top toolbar. This will begin the SPI Serial Flash pro-

gramming.

On-Board Clock Capabilities

(See Appendix B, Figure 19)

The LatticeECP3 Versa Evaluation Board allows for several clock source options. Some of these options are con-

trolled via the ispClock5406A programmable clock manager device. The ispClock5406A enables the reference

clock from the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board

is in a PCI Express host socket. When the board is not in a PCI Express host socket, the clock will be supplied by a

156.25 MHz clock on-board oscillator. Both clock inputs can be fanned out to the dedicated SERDES reference

inputs, FPGA inputs, and to the expansion connectors. The factory default programming only connects the

SERDES reference clock inputs. Factory-defined demonstration designs will control and manage the clock.

Figure 7. Clock Controller Scheme

Clock Select

FPGA

Clock

PCLKT0

F11

PCLKC0

F12

SERDES

Reference

Clock

Factory Default

Clock Programming

SERDES Reference

Clock Only

Expansion Interface

Clock

REFCLKP

V12

REFCLKN

V11

PCI Express

156.25 MHz

On-board

Oscillator

LatticeECP3 Versa Evaluation Board

User’s Guide

General Purpose Clock Source

An on-board 100MHz LVDS oscillator is provided for general purpose use. This clock source is connected to differ-

ential inputs L5 and K6 and must be used as LVDS inputs to the FPGA. This pin pair also provides optimal interface

to the FPGA PLL for customized use.

The PCI Express add-in card specification requires add-in boards to include capabilities to tell the host of its pres-

ence. The LatticeECP3 Versa Evaluation Board allows this optional connection via a board jumper. The factory

default will have two jumpers installed as shown below for the PRSNT connection to the PCI Express host.

Figure 8. PCI Express PRSNT Control Connection

1 2

3 4

5 6

PCI Express PRSNT

Jumper Selector

SERDES

The LatticeECP3 quad-based SERDES FPGA is utilized on the board for several purposes. The PCSA quad is pro-

visioned to provide a single, full-duplex PCI Express channel. The high-speed signals are connected to the PCI

Express edge connection.

Table 3. PCI Express Channel Interconnections

PETp0 HDINP0 Y15

PETn0 HDINN0 Y14

PERp0 HDOUTP0 AB15

PERn0 HDOUTN0 AB14

Table 4. SMA Test Interconnections

J5 HDINP3 Y8

J6 HDINN0 Y9

J7 HDOUTP3 AB8

J8 HDOUTN3 AB9

FPGA Test Pins

(see Appendix B, Figure 18)

General Purpose DIP Switches

General purpose FPGA pins are available for user applications. FPGA pins are connected to switch SW3, a SPST

slide-actuated DIP switch. The switches are connected to logic level 0 when moved to the ON position. Switch posi-

tion 1 is indicated with a dot. These inputs are within a bank connected to 1.5V. The user must program these

inputs to be the LVCMOS15 type in the design.

LatticeECP3 Versa Evaluation Board

User’s Guide

Figure 9. LatticeECP3 Versa Evaluation Board LEDs and Switches

The designated pins are connected according to Table 5.

Table 5. FPGA Ball to DIP Switch Position

FPGA Ball

Number

SW3 DIP Switch

Position

J7 1

J6 2

H2 3

H3 4

J3 5

K3 6

J2 7

J1 8

General Purpose LEDs

(See Appendix B, Figure 18)

The LEDs provided on the LatticeECP3 Versa Evaluation Board are connected to general purpose FPGA I/Os.

These LEDs provide status for user designs and must be included in the design. The LEDs illuminate when the

FPGA output is driven LOW. Tabl e 6 shows the LED and associated FPGA pins. These pins are within an I/O bank

connected to 3.3V and the user should program these to be LVCMOS33 type outputs in the design.

Table 6. LED Definitions

LED

Number

FPGA Ball

Number

PCB

Designator LED Color

LED0 U19 D21 Green

LED1 U18 D22 Green

LED2 AA21 D24 Ye l l o w

LED3 Y20 D25 Ye l l o w

LED4 W19 D26 Red

LED5 V19 D27 Red

LED6 AA20 D29 Blue

LED7 AB20 D28 Blue

LatticeECP3 Versa Evaluation Board

User’s Guide

Alpha-numeric LED Display

(see Appendix A, Figure 18)

A 14-segment alpha-numeric display is provided on the board (D23). These LED segments are connected to gen-

eral-purpose FPGA I/Os. The LEDs must be included in the FPGA design. The LEDs illuminate when the FPGA

output is driven LOW. Ta bl e 7 shows the LED and associated FPGA pins. These pins are within an I/O bank con-

nected to 3.3V and the user should program these to be LVCMOS33 outputs in the design.

Figure 10. 14-Segment Display

Table 7. Alpha-numeric LED Definitions

Display

fpBGA Ball

Number Display

fpBGA Ball

Number

AV6 JAB3

BU7 KAB4

CY6 LW4

DAa6 MY5

EU8 NAA4

FT8 PAA5

GR9 DP W5

HT9

DDR3 Memory Device

(see Appendix B, Figure 17)

• The LatticeECP3 Versa Evaluation Board is equipped with a SDRAM memory device (1.5V, 64Mb/x16, 96-ball

FBGA, 667 MHz, DDR3-1333) such as the Micron MT41J64M16JT-15E:G device.

• The DDR3 memory includes a 16-bit wide memory controller interface.

• The board includes termination of data, address and command signals. It includes all power and external compo-

nents needed to demonstrate the memory controller of the LatticeECP3 device.

• A 100 MHz on-board clock oscillator is available to provide a DDR3 reference clock.

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