Intersil ISL6442 Manual de usuario

Application Note 1181

Author: Pengju Kong

ISL6442 Dual PWM and Linear Controller Evaluation

Board User Guide

This application note describes how to use the ISL6442EVAL1Z

(Rev. C) board to evaluate the ISL6442 dual switching

regulator, plus one linear regulator. Refer to the schematic,

BOM (Bill of Materials), and board layout (at the end of this

document), as needed. The ISL6442 datasheet is also used as

a reference.

Configuration

The outputs are set up as follows:

•SwitcherV

OUT1 = 1.8V @ 3A (with VIN = 6V)

•SwitcherV

OUT2 = 3.3V @ 3A (with VIN = 6V)

•LinearV

OUT3 = 5.0V @ 0.3A (with VIN3 = 6V)

The outputs are switching at ~1.4MHz rate, based on the

resistor selected on the RT pin.

The current range for the switcher output that is presently

supported is limited by the FETs used. The FDS6912A dual FET

(in SO-8 package) can handle up to 3A. However, the ISL6442

gate drivers are capable of driving discrete upper and lower

FETs for up to 25A output current as well, even though not

supported on this board.

The linear output supports ~1W. The output current capability

of the linear regulator is determined mainly by the power

dissipation of the FET as mounted:

PVOUT3 = (VIN3-VOUT3)*IOUT3.

Quick Start Evaluation

Figure 1 shows a photo of the populated board, and Figure 2

shows a plot of the top layer for reference, and details the

available input and output connections. Two switchers share

one input VIN. The linear regulator has separate turrets for its

input (VIN3) and GND. Each output has turrets for VOUT and

GND, plus a scope probe socket, for low noise waveforms.

Quick Start Setup (Light Load)

For a quick and easy test, one 6V supply is needed. Connect P1

(VIN) and P7 (VIN3) to each other, and to the 6V supply; connect

the supply GND to P2 and P9. Attach light loads to each

output.

Switch on the power supply; all three outputs should turn on to

their expected DC values; use a voltmeter or oscilloscope to

view them. VOUT1 and VOUT2 will have a ramp time of a few

milliseconds (VOUT3 will be much faster).

Note that the IC and all three inputs are sharing one supply

voltage in this simple example. The linear VIN3 can certainly be

different, since it has its own input posts.

Board Features and Modifications

Heavier loads can be evaluated by placing them across the

appropriate output to GND. Resistors, electronic loads, or

FIGURE 1. ISL6442EVAL1Z BOARD PHOTO

LOAD

Iout

Vout

VIN = 6V

VIN3 = 6V VOUT3 LOAD

VOUT2 LOAD

VOUT1 LOAD

VOUT2

test

point

VOUT1

test

point

FIGURE 2. ISL6442EVAL1Z INPUT AND OUTPUT CONNECTIONS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

November 28, 2011

AN1181.1

Application Note 1181

2AN1181.1

November 28, 2011

actual loads can be used. It is STRONGLY recommended that the

power be turned off when attaching loads, due to the tight

spacing of the posts. The switcher outputs should be able to

provide at least 3A; monitor the FET temperature if you try to go

higher, to be sure the conditions will allow it. Make sure the input

power supply can source the amount of input current necessary

to drive the maximum loads to be tested.

The linear VOUT3 is especially sensitive to power dissipation

concerns; it will change as the user varies either the input

voltage, the output voltage, and/or the load current. The

equation used is PVOUT3 = (VIN3-VOUT3)*IOUT3. The PNP bipolar

will also be rated for how well the power is dissipated from the

package and spread out on the board; this is another variable

that the user must keep in mind for their design and layout.

JP1 is used to disable VOUT1, by shorting SS/EN1 to GND. JP2

does the same function for VOUT2.

The switching frequency is controlled by a resistor (R4) on the RT

pin, to GND. Refer to the datasheet for the curve of resistor

values versus frequency.

Each output voltage is determined by a resistor divider from the

output to its FB pin to GND. See the ISL6442 datasheet for the

formulas to calculate the values. Note that there are some

limitations; the switchers can approach 100% duty, but will be

limited by dead time, rDSON of the FETs at maximum load,

switching frequency, etc. The maximum values are limited by the

VIN available (if you want go higher, check the ratings of the FETs,

and other output components to be sure they can handle it). The

minimum output voltage will be just above the 0.6V internal

reference. The maximum output voltage for the linear is limited

by the VIN3 and the LCDR pin (which is biased from 5V). Thus, the

maximum output voltage is close to the 5V set on the board; it is

not recommended to go higher. The minimum voltage will also

be just above the 0.6V internal reference.

Performance Waveforms

These figures depict the ISL6442EVAL1Z performance during

typical operational situations, as well as during fault conditions.

Loading of the output can be most easily done via an electronic

load; however, other methods can work as well.

Figure 3 shows a typical power-up sequence, with all inputs

connected to a single VIN = VIN3 = 6V. When VCC exceeds its

POR rising trip point (~4.4V), the IC is enabled, and the linear

VOUT3 comes up almost immediately. Meanwhile, the two SS/EN

pins start charging (not shown), but the outputs do not start

ramping until the SS/EN pins ~1V; then both switcher outputs

start their soft-start ramps at the same time. In this case, both

outputs track each other initially; this is accomplished by

selecting the ratio of SS/EN capacitors to match their output

voltages. The ramp times shown are on the order of a few

milliseconds, as determined by the SS/EN capacitors on the

board.

Figure 4 shows the detail soft start waveform of PWM1 (PMW2

would be similar). The full SS/EN1 ramp is shown; the output

doesn’t start to ramp until the SS/EN passes the ~1V threshold

for Enable. The output ramps from zero to full scale, while

SS/EN1 ramps from 1.0V to 1.6V. Finally, the EN/SS1 keeps

ramping up to ~3.2V, at which point the ramp is considered done

(the PGOOD timer would start from this point, if both outputs

ramps were done).

FIGURE 3. TYPICAL POWER-UP WAVEFORMS WITH VIN

CH4 VOUT3

(5V/DIV)

CH3 VOUT2

(2V/DIV)

CH2 VOUT1

(2V/DIV)

CH1 VIN

(2V/DIV)

5ms/DIV; VIN3 = VIN

CH1 OUT1

(1V/DIV)

CH1 EN/SS1

(1V/DIV)

2ms/DIV FIGURE 4. PWM1 SOFT-START

~3.2V

Application Note 1181

3AN1181.1

November 28, 2011

Figures 5 and 6 show the PHASE1 signal (which has the same

timing as UGATE1) and the output voltage ripple on VOUT1 at no

load and 3A load. The switching frequency is 1.4 MHz.

Figure 7 shows the overcurrent hiccup mode already in

operation. At time T0, the SS/EN2 is discharged to GND (it may

not have time to reach GND, due to the limited size of the

discharge transistor, plus the size of the timing capacitor). Once

SS/EN2 is below ~1V, the output should shut off, and the load

current goes to zero; this occurs by time T1. Once SS/EN2 rises

above 1V again, the VOUT2 will try to turn on again. If the output

remains shorted, the output current will be limited on each clock

cycle to an average value low enough to keep the dissipation

reasonable.

Conclusion

The ISL6442EVAL1Z evaluation board showcases a simple, but

high-performance dual regulator, providing control in a variety of

applications, with emphasis on computer systems. The

high-current MOSFET drivers of the ISL6442 yield a highly

efficient power conversion solution with a reduced number of

external components in a compact footprint.

Documentation

See the following pages for more detailed information, including:

• “Schematic” of ISL6442EVAL1Z

• Table 1, “BILL OF MATERIALS” on page 5

• “ISL6442EVAL1Z Board Layout” on page 7. Note that this

board layout has not been fully optimized for performance or

minimum board area, primarily due to the various options, test

points, and other features to make testing easier. So while it

follows most of the recommended practices, it could

potentially be improved for any given single application.

References

Datasheet: ISL6442 datasheet

Visit us on the internet, at: http://www.intersil.com

CH1

PHASE1

CH2 (AC)

VOUT1

(20mV/DIV)

FIGURE 5. PWM1 SWITCHING AND RIPPLE WAVEFORMS AT

NO LOAD

(2V/DIV)

0.2µs/DIV; VOUT1 = 1.8V; VIN = 6V

CH1

PHASE1

CH2 (AC)

VOUT1

(20mV/DIV)

FIGURE 6. PWM1 SWITCHING AND RIPPLE WAVEFORMS

AT 3A LOAD

(2V/DIV)

0.2µs/DIV; VOUT1 = 1.8V; VIN = 6V

FIGURE 7. PWM2 OVERCURRENT HICCUP MODE

CH1

SS/EN2

CH4

ILOAD2

CH2

VOUT2

(1V/DIV)

2ms/DIV; VOUT2 = 3.3V; VIN = 6V; ROCSET = 2.15kW

(5A/DIV)

(2V/DIV)

T0 T1

Application Note 1181

4AN1181.1

November 28, 2011

Schematic

SGND

AS CLOSE TO U1 PIN 11 AND PIN 23 AS POSSIBLE.

+1.8V

+3.3V

GND

GROUND & GROUND ARE TIED TOGETHER

NOTES:

SGND

+5.0V

0.3A

GND

+6.0V

VIN

01/24/2007

THEJU BERNARD

6.04K

C24

OPEN

C18

R16

4.7

TP11

TP10

TP9

TP13

C14

C16

R11

C19

C22

C17

C13

R10

C29

C28

C31

C30

C33

R21

R22

C35

C34

R25

R19

R12

P13

P12

P11

C12

R18

C26

C20

C21

C23

C37

C36

R23

R24

R14

TP2

TP7

TP4

TP6

TP1

JP1

JP2

SP2

SP1

SP3

P10

5.11K

VOUT1

FDS6912A

VIN

EVALUATION BOARD

TIM KLEMANN

SCHEMATIC

ISL6442EVAL1Z

~/ISL6442/ISL6442EVAL1ZC

ISL6442

FB1

3.24K

10.5K

5.11K

23.2K

1000PF

DNP

10.2K

0.015UF

0.1UF

EN1

5.49K

ISL6442IAZ

DNP

OPEN

0805 100UF

100UF

10UF

100UF

10UF

OPEN

VOUT2

0.1UF

10UF

8200PF

100PF

0.1UF

1000PF

2.15K

PGOOD

VCC5

EN2

4.7

36.5K

FB2

1.5UH

2.1K

5.11K

OPEN

68UF 10UF

0.1UF

100

FZT749

0.1UF

100UF

VOUT3

0.1UF

OPEN

37.4K

0.1UF

4.7

47PF

TP8

0805

R17

TP5

0.1UF

C10

100UF

1UF

C15

R13

4.7

TP3

VCC5

4.7UF

C11

1000PF

2.15K

10UF

R26

C27

TP12

2.2UH

TP14

FB2

1500PF

R20

VIN3

FDS6912A

100UF

R15

C32

OCSET1

SS1/EN1 BOOT1

VIN

UGATE1

PHASE1

LGATE1

VCC

PGND

LGATE2

PHASE2

UGATE2

BOOT2

PGOOD

OCSET2

SS2/EN2

COMP2

FB2

LCFB

LCDR

SGND

COMP1

FB1

OUT

FILENAME:

SHEET

REV.

DATE:

HRDWR ID

MASK#

TITLE:

ENGINEER:

DATE:

TESTER

UPDATED BY:

RELEASED BY:

DRAWN BY:

654

Application Note 1181

5AN1181.1

November 28, 2011

TABLE 1. BILL OF MATERIALS

ITEM QTY PART REFERENCE VALUE DESCRIPTION PART # MANUFACTURER

1 4 C28-C31 100µF CAP-TANT LOWESR, SMD, D3, 100µF, 10V,

20%, POSCAP, ROHS

10TPB100M SANYO

2 1 C16 68µF CAP, SMD, 6x3.2, 68µF, 10V, 20% POSCAP,

ROHS

10TPB68MC SANYO

3 4 C2, C3, C13, C19 0.1µF CAPACITOR, SMD, 0603, 0.10µF, 50V, 10%,

X7R

Generic

4 1 C18 4.7µF CAPACITOR, SMD, 1206, 4.7µF, 16V, 10%,

X7R, ROHS

Generic

5 3 C17, C32, C33 10µF CAP, SMD, 1210, 10µF, 25V, 20%, X7R,

ROHS

Generic

6 3 C1, C8, C22 100µF CAP, SMD, 8X10.2, 100µF, 25V, 20%, AL.EL,

ROHS

EEE-FC1E101P EEE-FC1E101P

7 2 C9, C10 10µF CAP, SMD, 1210, 10µF, 35V, 10%, X5R,

ROHS

Generic

8 1 C5 100pF CAP, SMD, 0603, 100pF, 50V, 5%, COG,

ROHS

Generic

9 3 C11, C12, C35 1000pF CAP, SMD, 0603, 1000pF, 50V, 10%, X7R,

ROHS

Generic

10 5 C20, C21, C23, C36, C37 0.1µF CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R,

ROHS

Generic

11 1 C34 1500pF CAP, SMD, 0603, 1500pF, 50V, 10%, X7R,

ROHS

Generic

12 1 C6 15nF CAP, SMD, 0603, .015µF, 50V, 10%, X7R,

ROHS

Generic

13 1 C4 47pF CAP, SMD, 0603, 47pF, 50V, 5%, NPO, ROHS Generic

14 1 C7 8200pF CAP, SMD, 0603, 8200pF, 50V, 10%, X7R,

ROHS

Generic

15 1 C15 1µF CAP, SMD, 1206, 1µF, 50V, 10%, X7R, ROHS Generic

16 1 L1 1.5µH COIL-PWR INDUCTOR, SMD, 6.9x6.5m,

1.5µH, 20%, 9A, ROHS

IHLP-2525CZ-ER-

1R5-M01

IHLP-2525CZ-ER-1R5-

M01

17 1 L2 2.2µH COIL-PWR INDUCTOR, SMD, 6.9x6.5m,

2.2µH, 20%, 10A, ROHS

IHLP-2525CZ-ER-

2R2-M01

IHLP-2525CZ-ER-2R2-

M01

18 3 SP1-SP3 CONN-SCOPE PROBE TEST PT, COMPACT,

PCB MNT, ROHS

131-4353-00 131-4353-00

19 13 P1-P13 CONN-TURRET, TERMINAL POST, TH, ROHS 1514-2 1514-2

20 14 TP1-TP14 CONN-MINI TEST POINT, VERTICAL, WHITE,

ROHS

5002 5002

21 2 JP1, JP2 CONN-JUMPER, 2PIN, SHUNT, ROHS SPC02SYAN SPC02SYAN

22 1 U1 IC-PWM/LINEAR CONTROLLER, 24P, QSOP,

ROHS

ISL6442IAZ ISL6442IAZ

23 2 Q1, Q2 TRANSIST-DUAL MOS, N-CHAN, 8P, SOIC,

30V, 6A, ROHS

FDS6912A FDS6912A

24 1 T1 TRANSISTOR, PNP, SMD, SOT223, -25V, -3A,

ROHS

FZT749 FZT749

25 4 R12, R13, R15, R16 4.7ΩRES, SMD, 0603, 4.7Ω, 1/10W, 1%, TF,

ROHS

Generic

Application Note 1181

6AN1181.1

November 28, 2011

26 4 R5, R14, R23, R24 0ΩRESISTOR, SMD, 0603, 0Ω, 1/10W, TF,

ROHS

Generic

27 1 R9 100ΩRES, SMD, 0603, 100Ω, 1/10W, 1%, TF,

ROHS

Generic

28 1 R4 10.2kΩRES, SMD, 0603, 10.2k, 1/10W, 1%, TF,

ROHS

Generic

29 1 R19 10.5kΩRES, SMD, 0603, 10.5k, 1/10W, 1%, TF,

ROHS

Generic

30 1 R1 2.1kΩRES, SMD, 0603, 2.1k, 1/10W, 1%, TF, ROHS Generic

31 2 R7, R8 2.15kΩRES, SMD, 0603, 2.15k, 1/10W, 1%, TF,

ROHS

Generic

32 1 R21 23.2kΩRES, SMD, 0603, 23.2k, 1/10W, 1%, TF,

ROHS

Generic

33 1 R25 3.24kΩRES, SMD, 0603, 3.24k, 1/10W, 1%, TF,

ROHS

Generic

34 1 R3 36.5kΩRES, SMD, 0603, 36.5k, 1/10W, 1%, TF,

ROHS

Generic

35 1 R10 37.4kΩRES, SMD, 0603, 37.4k, 1/10W, 1%, TF,

ROHS

Generic

36 3 R6, R20, R22 5.11kΩRES, SMD, 0603, 5.11k, 1/10W, 1%, TF,

ROHS

Generic

37 1 R2 5.49kΩRES, SMD, 0603, 5.49k, 1/10W, 1%, TF,

ROHS

Generic

38 1 R26 6.04kΩRES, SMD, 0603, 6.04k, 1/10W, 1%, TF,

ROHS

Generic

TABLE 1. BILL OF MATERIALS (Continued)

ITEM QTY PART REFERENCE VALUE DESCRIPTION PART # MANUFACTURER

Application Note 1181

7AN1181.1

November 28, 2011

ISL6442EVAL1Z Board Layout

FIGURE 8. TOP SILKSCREEN FIGURE 9. TOP LAYER

FIGURE10.2NDLAYER FIGURE11.3RDLAYER

Application Note 1181

Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is

cautioned to verify that the Application Note or Technical Brief is current before proceeding.

For information regarding Intersil Corporation and its products, see www.intersil.com

AN1181.1

November 28, 2011

FIGURE 12. BOTTOM LAYER FIGURE 13. BOTTOM SILKSCREEN

ISL6442EVAL1Z Board Layout (Continued)

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