Intel Stratix 10 GX Manual de usuario

Intel® Stratix® 10 GX Transceiver

Signal Integrity Development Kit

User Guide

UG-20047

2017.10.11

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Contents

1 Overview......................................................................................................................... 4

1.1 General Board Description....................................................................................... 4

1.2 Recommended Operating Conditions......................................................................... 4

1.3 Handling the Development Board..............................................................................4

2 Getting Started................................................................................................................ 5

2.1 Installing the Quartus Prime software........................................................................5

2.2 Installing the Development Board............................................................................. 5

2.3 Installing the Intel FPGA Download Cable Driver......................................................... 6

3 Development Board Setup............................................................................................... 7

3.1 Setting up the Development Board............................................................................7

3.2 Factory Default Switch and Jumper Settings............................................................... 8

4 Board Components.........................................................................................................11

4.1 Board Overview.................................................................................................... 11

4.2 Stratix 10 GX FPGA............................................................................................... 14

4.3 MAX V CPLD System Controller............................................................................... 20

4.4 FPGA Configuration............................................................................................... 23

4.4.1 FPGA Programming over Embedded USB-Blaster........................................... 23

4.4.2 FPGA Programming from Flash Memory........................................................24

4.4.3 FPGA Programming over External USB-Blaster.............................................. 26

4.5 Status Elements................................................................................................... 27

4.6 Setup Elements.................................................................................................... 28

4.7 User Input-Output Components.............................................................................. 29

4.7.1 User-Defined Pushbuttons.......................................................................... 29

4.7.2 User-Defined DIP Switch............................................................................ 30

4.7.3 User-Defined LEDs.................................................................................... 30

4.7.4 Character LCD.......................................................................................... 31

4.8 Clock Circuits....................................................................................................... 31

4.8.1 Transceiver Dedicated Clocks...................................................................... 31

4.8.2 General-Purpose Clocks............................................................................. 32

4.8.3 Embedded USB-Blaster Clock..................................................................... 34

4.9 Transceiver Channels.............................................................................................34

4.10 Communication Ports...........................................................................................37

4.11 Flash Memory..................................................................................................... 38

5 System Power................................................................................................................ 42

5.1 Power Guidelines.................................................................................................. 42

5.2 Power Supply....................................................................................................... 42

5.3 Power Management...............................................................................................43

5.4 Power Distribution System..................................................................................... 44

5.5 Thermal Limitations and Protection Guidelines.......................................................... 46

6 Board Test System......................................................................................................... 47

6.1 Preparing the Board.............................................................................................. 48

6.2 Running the Board Test System.............................................................................. 48

6.3 Using the Board Test System.................................................................................. 49

6.3.1 The Configure Menu.................................................................................. 49

Contents

Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

6.3.2 The System Info Tab................................................................................. 50

6.3.3 The GPIO Tab........................................................................................... 51

6.3.4 The Flash Tab........................................................................................... 52

6.3.5 The FMCA Tab...........................................................................................54

6.3.6 The FMCB Tab...........................................................................................60

6.3.7 The LPBK Tab........................................................................................... 65

6.3.8 The MXP Tab............................................................................................ 69

6.3.9 The SMA Tab............................................................................................ 72

6.3.10 The QSFP and SFP+ Tab...........................................................................75

6.3.11 The CFP4 Tab..........................................................................................78

6.3.12 Power Monitor.........................................................................................81

6.3.13 Clock Controller...................................................................................... 82

7 Board Update Portal.......................................................................................................85

7.1 Connecting to the Board Update Portal.....................................................................85

7.2 Using the Board Update Portal................................................................................ 86

A Additional Information.................................................................................................. 87

A.1 Safety and Regulatory Information..........................................................................87

A.1.1 Safety Warnings....................................................................................... 88

A.1.2 Safety Cautions........................................................................................ 89

A.2 Compliance and Conformity Information.................................................................. 91

B Revision History.............................................................................................................92

B.1 User Guide Revision History................................................................................... 92

Contents

Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

1 Overview

1.1 General Board Description

The Intel® Intel Stratix® 10 GX Transceiver Signal Integrity Development Kit is a

complete design environment that includes both hardware and software you need to

develop Intel Stratix 10 GX FPGA designs.

The following list describes what you can accomplish with the kit:

• Evaluate transceiver performance up to 17.4 Gbps for L-Tile and 28.3 Gbps for H-

Tile version.

• Generate and check pseudo-random binary sequence (PRBS) patterns

• Dynamically change differential output voltage (VOD) pre-emphasis and

equalization settings to optimize transceiver performance for your channel

• Perform jitter analysis

• Verify physical medium attachment (PMA) compliance to PCI Express* (PCIe*),

1G/10G/40G/100G Ethernet and other major standards.

Related Links

Stratix 10 Support

1.2 Recommended Operating Conditions

The recommended operating conditions for this development kit are:

• Recommended ambient operating temperature range: 0C to 45C

• Maximum ICC load current: 130 A

• Maximum ICC load transient percentage: 30%

• FPGA maximum power supported by the supplied heatsink/fan: 200 W

1.3 Handling the Development Board

When handling the board, it is important to observe static discharge precautions.

Caution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-

static handling precautions when touching the board.

Caution: This development kit should not be operated in a Vibration Environment.

1 Overview

and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other

countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in

accordance with Intel's standard warranty, but reserves the right to make changes to any products and services

at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Intel. Intel

customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

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2 Getting Started

2.1 Installing the Quartus Prime software

The Intel Quartus® Prime design software is a multiplatform design environment that

easily adapts to your specific needs in all phases of FPGA, CPLD, and SoC designs. The

Intel Quartus Prime software delivers the highest performance and productivity for

Intel FPGAs, CPLDs, and SoCs.

Design software must enable dramatically increased design productivity in order to

take advantage of devices with multi-million logic elements with increased capabilities

that provide designers with an ideal platform to meet next-generation design

opportunities.

The new Intel Quartus Prime Design Suite® design software includes everything

needed to design for Intel FPGAs, SoCs and CPLDs from design entry and synthesis to

optimization, verification and simulation. The Intel Quartus Prime Design Suite

software includes an additional Spectra-Q® engine that is optimized for Intel Stratix

10 and future devices. The Spectra-Q engine enables new levels of design productivity

for next generation programmable devices with a set of faster and more scalable

algorithms, a hierarchical database infrastructure and a unified compiler technology.

Intel Quartus Prime Pro Edition

The Intel Quartus Prime Design Suite software is available in three editions based on

specific design requirements: Pro, Standard, and Lite Edition.

The Intel Quartus Prime Pro Edition is optimized to support the advanced features in

Intel's next generation FPGAs and SoCs and requires a paid license.

Included in the Intel Quartus Prime Pro Edition are the Intel Quartus Prime software,

Nios® II EDS and the MegaCore IP Library.

To install Intel's development tools, download the Intel Quartus Prime Pro Edition

software from the Quartus Prime Pro Edition page in the Download Center of Intel's

website.

2.2 Installing the Development Board

To install the Intel Stratix 10 GX Transceiver Signal Integrity Development Board,

perform the following steps: