Intel Agilex Manual de usuario
Intel® Agilex™ Clocking and PLL User
Guide
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Contents
1. Intel® Agilex™ Clocking and PLL Overview...................................................................... 3
1.1. Clock Networks Overview........................................................................................3
1.2. PLLs Overview.......................................................................................................3
2. Intel Agilex Clocking and PLL Architecture and Features................................................ 4
2.1. Clock Networks Architecture and Features.................................................................4
2.1.1. Clock Network Architecture......................................................................... 4
2.1.2. Clock Resources........................................................................................ 6
2.1.3. Clock Control Features................................................................................6
2.2. PLLs Architecture and Features................................................................................9
2.2.1. PLL Features............................................................................................. 9
2.2.2. PLL Usage...............................................................................................10
2.2.3. PLL Locations.......................................................................................... 10
2.2.4. PLL Architecture.......................................................................................11
2.2.5. PLL Control Signals.................................................................................. 11
2.2.6. PLL Feedback Modes.................................................................................12
2.2.7. Clock Multiplication and Division.................................................................17
2.2.8. Programmable Phase Shift........................................................................ 18
2.2.9. Programmable Duty Cycle......................................................................... 18
2.2.10. PLL Cascading........................................................................................18
2.2.11. PLL Input Clock Switchover......................................................................19
2.2.12. PLL Reconfiguration and Dynamic Phase Shift.............................................24
2.2.13. PLL Calibration.......................................................................................24
3. Intel Agilex Clocking and PLL Design Considerations.................................................... 26
3.1. Guideline: Clock Switchover.................................................................................. 26
3.2. Guideline: Timing Closure..................................................................................... 27
3.3. Guideline: Resetting the PLL..................................................................................27
3.4. Guideline: Configuration Constraints.......................................................................28
4. Document Revision History for the Intel Agilex Clocking and PLL User Guide............... 29
Contents
Intel® Agilex™ Clocking and PLL User Guide Send Feedback
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1. Intel® Agilex™ Clocking and PLL Overview
1.1. Clock Networks Overview
Intel® Agilex™ devices contain dedicated resources for distributing signals throughout
the fabric. These resources are typically used for clock signals and other signals with
low-skew requirements. In Intel Agilex devices, these resources are implemented as a
programmable clock routing network, which allows for the implementation of various
low-skew clock trees.
Related Information
Use Global Clock Network Resources, Design Recommendations User Guide (Intel
Quartus® Prime Pro Edition)
Provides more information about clock assignments in the Intel Quartus® Prime
software.
1.2. PLLs Overview
Phase-locked loops (PLLs) provide robust clock management and synthesis for device
clock management, external system clock management, and high-speed I/O
interfaces.
The Intel Agilex device family contains the following I/O PLLs for core applications.
The I/O PLLs can only function as integer PLLs.
•Fabric-feeding I/O PLLs—three C counter outputs available and do not support PLL
cascading
•I/O bank I/O PLLs—seven C counter outputs available and support PLL cascading
The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/
deserializer (SERDES) blocks in the I/O banks. Each I/O bank contains two I/O bank
I/O PLLs and one fabric-feeding I/O PLL.
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
2. Intel Agilex Clocking and PLL Architecture and Features
2.1. Clock Networks Architecture and Features
2.1.1. Clock Network Architecture
Each Intel Agilex device is divided into a number of evenly sized clock sectors.
Figure 1. Clock Sector Floorplan for Intel Agilex Devices
This figure shows an example of the clock sectors in an Intel Agilex device, which is implemented as an array
of sectors—5 rows and 6 columns in this example. I/O banks are at the top and bottom of the Intel Agilex
device.
Clock Sector
I/O Bank Row
I/O Bank Row
2.1.1.1. Clock Network Hierarchy
The Intel Agilex clock network is organized in a hierarchy with 3 levels.
Figure 2. Clock Network Hierarchy
Programmable
Clock Routing SCLK 632
32
Row Clock
First Level Second Level Third Level
Clock Source
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
2.1.1.2. Clock Sector
Each clock sector has dedicated sector clock (SCLK) network and row clock network
that can be accessed by the programmable clock routing. On each side of the clock
sector, there is a channel that contains 64 unidirectional wires in bidirectional pairs,
where only one wire in each pair can be used at one time. At each corner, there is a
set of programmable clock switch multiplexer that can route between these clock
wires.
A signal on a vertical clock wire can enter the sector to its left or right via clock tap
multiplexers. The clock tap multiplexer drives a sector clock, which distributes the
signal to each row in the clock sector. In each row, there are six row clock resources
that route to all core functional blocks, PLLs, and I/O interfaces in the sector, and to
adjacent transceivers.
Figure 3. Dedicated Clock Resources Within a Clock Sector
3232
32
6
32
32
32
32
32
32
32
32
Clock Switch
Multiplexers
Row Clock
(Covers Each Core
Logic Row in Sector)
SCLK
Clock Tap
Multiplexers
Horizontal Clock
Vertical Clock
32 32
32 32
2.1.1.3. Programmable Clock Routing
The Intel Quartus® Prime software automatically configures the clock switch
multiplexer, clock tap multiplexer, SCLK multiplexer, and row clock multiplexers to
generate skew-balanced clock trees. The resulting routing path distributes the signal
from the clock source to all target destinations in one or more clock sectors.
The Intel Quartus Prime software creates efficiently balanced clock tress of various
sizes, ranging from a single clock sector to the entire device, as shown in the following
figure. By default, the Intel Quartus Prime software automatically determines the size
and location of the clock tree. Alternatively, you can directly constrain the clock tree
size and location by using either a Clock Region Assignment or Logic Lock Regions.
The total insertion delay for the clock network depends on the number of clock
resources needed to implement the clock tree, increasing with the number of clock
sectors reached and the distance of the furthest clock destination from the clock
source. As delay increases, the worst-case skew for crossing clock sectors using
different clock tree branches grows, potentially degrading the maximum performance.
For very high-speed clock sources, it is advantageous to reduce the number of clock
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sectors driven, which reduces the clock skew, and to reduce the distance between the
clock source and the furthest destination, which reduces both clock skew and total
clock insertion delay.
2.1.2. Clock Resources
Table 1. Programmable Clock Routing Resources for Intel Agilex Devices
Number of Resources Available Source of Clock Resource
64 unidirectional programmable clock routing
at the boundary of each clock sector
For transceiver bank:
• Physical medium attachment (PMA) and physical coding sublayer
(PCS) TX and RX clocks per channel
• PMA and PCS TX and RX divide clocks per channel
• Hard IP core clock output signals
•REFCLK pins
• Core signals (1)
For I/O bank:
•I/O PLL C counter outputs
•I/O PLL M counter outputs for feedback
• Phase aligner counter outputs
• Dynamic phase alignment (DPA) clock output
• Clock input pins
• Core signals (1)
For more information about the clock input pins connections, refer to the pin
connection guidelines.
Related Information
Intel Agilex Device Family Pin Connection Guidelines
2.1.3. Clock Control Features
The following figure shows the high level description of the Intel Agilex clock control
features—clock gating and clock divider. The clock from the I/O PLL output can be
gated dynamically. These clock signals along with other clock sources go to the
periphery distributed clock multiplexer (DCM). In the periphery DCM, the clock signal
can either pass straight through, be gated by the root clock gate, or be divided by the
clock divider.
The Intel Quartus Prime software routes the clock signal on the programmable clock
routing to reach each clock sector. The clock signal can be gated in each sector by the
SCLK gates. The clock enters the SCLK network followed by the row clock network,
and eventually reaches the registers in the core. The LAB registers have a built-in
functional clock enable feature, as shown in the following figure.
(1) Core signals drive directly to programmable clock routing through clock switch multiplexers in
the clock sector instead of the periphery DCM block.
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Figure 4. Clock Gating and Clock Divider in Intel Agilex Clock Network
C Counters
I/O PLL Clock
Gates
I/O
PLL
LAB Level
Gating Signal
D Q
I/O Bank Periphery DCM Block
SCLK
Root Clock
Gate Programmable
Clock Routing
Clock Gate
Clock Gate
Clock Gate
Clock
Divider Row Clock
2.1.3.1. Clock Gating
2.1.3.1.1. Root Clock Gate
There is one root clock gate per I/O bank and transceiver bank. This gate is a part of
the periphery DCM.
2.1.3.1.2. Sector Clock Gate
Every sector of the device has 32 SCLKs. Each SCLK has a clock gate and bypassable
clock gate path. The SCLK gates are controlled by clock enable inputs from the core
logic. The Intel Quartus Prime software can route up to eight unique clock enable
signals to the 32 SCLKs in a sector.
Intel recommends using the clock gate with a negative latch to provide glitch free
gating on the output clock signal (outclk). The clock gate captures the enable signal
(clkena) on the next rising edge of the input clock signal (inclk). The following
timing diagram shows the relationship of the outclk with respect to inclk and
clkena.
Figure 5. Clock Gating Timing Diagram
clkena
outclk
inclk
The clock signal going into the SCLK network in a sector can only reach the core logic
in that sector. When you instantiate a SCLK gate in your design, the Intel Quartus
Prime software automatically duplicates the SCLK gate to create a clock gate in every
sector to which the clock signal is routed.
The SCLK gate is suitable for cycle-specific clock gating for high-frequency clocks. The
timing of the enable path to the SCLK gate is analyzed by the Intel Quartus Prime
software.
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Related Information
•Clock Sector on page 5
Provides a diagram that shows the dedicated clock resources within a clock
sector.
•Clock Control Features on page 6
Provides a diagram that shows the resources within a SCLK.
2.1.3.1.3. I/O PLL Clock Gate
You can dynamically gate each output counter of the Intel Agilex I/O PLL. This I/O PLL
clock gate provides a useful alternative to the root clock gate. The root clock gate can
gate only 1 of 7 output counters.
However, the I/O PLL clock gate is not cycle-specific. When you use the I/O PLL clock
gate, expect a delay of several clock cycles between the assertion or deassertion of
the clock gate and the corresponding change to the clock signal. The number of delay
cycles is non-deterministic because the enable signal must be synchronized into the
clock domain of the output clock, ensuring a glitch-free gate.
2.1.3.1.4. LAB Clock Gate
The Intel Agilex LAB register has built-in clock gating functionality. The register clock
enable mechanism is a hardened data feedback, as shown in the Clock Gating and
Clock Divider in Intel Agilex Clock Network diagram. The LAB clock gate offers no
associated power savings because this is a purely functional clock enable.
The analysis and synthesis phases of the Intel Quartus Prime software infer a LAB
clock gate from a behavioral description of clock gating in the register transfer level
(RTL). If a physical clock gate is desired, you must instantiate it explicitly.
Related Information
Clock Control Features on page 6
Provides the Clock Gating and Clock Divider in Intel Agilex Clock Network diagram.
2.1.3.2. Clock Divider
There is one clock divider per I/O bank and transceiver bank. The clock divider is a
part of the periphery DCM block and is located close to the root clock gate. The
outputs of the clock divider cannot be gated by the root clock gate in the same
periphery DCM block. However, this limitation does not apply to the SCLK gate. The
clock divider output in the periphery DCM block can drive a SCLK gate after going
through the programmable clock routing.
The clock divider has three outputs as follows:
• First output—passes through the input clock.
• Second output—divides the input clock by two.
• Third output—divides the input clock by four.
These three clock outputs are edge-aligned at the output of the clock divider.
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Figure 6. Clock Divider Timing Diagram
clk_div4
clk_div2
clk_div1
inclk
Related Information
Clock Control Features on page 6
Provides a diagram that shows the root clock gate and clock divider in the
periphery DCM block.
2.2. PLLs Architecture and Features
2.2.1. PLL Features
Table 2. PLL Features in Intel Agilex Devices—Preliminary
Feature I/O Bank I/O PLL Fabric-Feeding I/O
PLL
Integer PLL Yes Yes
Number of C output counter 7 3
M counter divide factor range 4 to 160 4 to 160
N counter divide factor range 1 to 110 1 to 110
C counter divide factor range 1 to 510 1 to 510
Dedicated external clock outputs Yes Yes
Dedicated clock input pins Yes Yes
External feedback input pin Yes Yes
Source synchronous compensation (2)Yes Yes
Direct compensation Yes Yes
Normal compensation (2)Yes Yes
Zero-delay buffer compensation Yes Yes
External feedback compensation Yes Yes
LVDS compensation Yes —
Voltage-controlled oscillator (VCO) output drives the DPA clock Yes —
Phase shift resolution (3) 78.125 ps 78.125 ps
continued...
(2) Non-dedicated feedback path option is available for this compensation mode.
(3) The smallest phase shift is determined by the VCO period divided by eight. For degree
increments, the Intel Agilex device can shift all output frequencies in increments of at least
45°. Smaller degree increments are possible depending on the frequency and divide
parameters.
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Feature I/O Bank I/O PLL Fabric-Feeding I/O
PLL
Programmable duty cycle Yes Yes
Power down mode Yes Yes
Bandwidth setting Low, medium, and
high
Medium and high
2.2.2. PLL Usage
I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can
use the I/O PLLs to:
• Reduce the number of required oscillators on the board
• Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies
from a single reference clock source
• Simplify the design of external memory interfaces and high-speed LVDS interfaces
• Ease timing closure because the I/O PLLs are tightly coupled with the I/Os
• Compensate for clock network delay
• Zero delay buffering
2.2.3. PLL Locations
Figure 7. I/O PLL Locations in I/O Bank
General-Purpose I/O Bank
I/O Bank
I/O PLL
Sub Bank
Fabric-Feeding
I/O PLL
I/O Bank
I/O PLL
Sub Bank
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