Infineon PSoC 4 Manual del operador

 
Application Note Please read the Important Notice and Warnings at the end of this document 001-84858 Rev. *N 
www.infineon.com page 1 of 45 2021-03-23 
AN84858 
 
PSoC 4 Programming Using an External 
Microcontroller (HSSP) 
About this document 
Scope and purpose 
AN84858 shows you how to implement PSoC™4 device programming with an external microcontroller by using 
modular C code. In this process, called Host Sourced Serial Programming (HSSP), the host microcontroller 
programs PSoC 4 through the serial wire debug (SWD) interface. The C code is written so that it can be ported to 
any microcontroller with minimal changes, speeding up HSSP application development for PSoC 4. 
More code examples? We heard you. 
To access an ever-growing list of hundreds of PSoC code examples, please visit our code examples web page. 
You can also explore the video training library here. 
 
Table of contents 
About this document....................................................................................................................... 1 
Table of contents............................................................................................................................ 1 
1Introduction .......................................................................................................................... 3 
1.1 Types of Programmers............................................................................................................................3 
1.2 Terms and Definitions.............................................................................................................................3 
2HSSP Firmware Architecture ................................................................................................... 5 
2.1 SWD Protocol Physical Layer ..................................................................................................................6 
2.2 SWD Protocol Packet Layer.....................................................................................................................6 
2.3 Fetching Programming Data...................................................................................................................6 
2.4 HSSP Programming Steps.......................................................................................................................7 
2.5 HSSP Timeout Parameters .....................................................................................................................7 
2.6 HSSP Programming Data........................................................................................................................8 
2.7 Main Application Code ............................................................................................................................8 
2.8 HSSP Error Status....................................................................................................................................8 
3Hardware Connections for HSSP Programming ........................................................................10 
4Porting the HSSP Application to a Host Programmer.................................................................11 
4.1 Files That Must Be Ported .....................................................................................................................11 
4.2 Code Changes Required While Porting.................................................................................................11 
5Calculating HSSP Timeout Parameters ....................................................................................13 
5.1 DEVICE_ACQUIRE_TIMEOUT.................................................................................................................13 
5.2 SROM_POLLING_TIMEOUT ...................................................................................................................14 
5.3 XRES_PULSE_100US .............................................................................................................................15 
6Interface for Receiving HSSP Programming Data ......................................................................17 
7HSSP Timing Validation .........................................................................................................19 
8Power Cycle Mode Programming.............................................................................................20 
9Testing the Example Projects .................................................................................................21 
9.1 For CY8CKIT-038 PSoC 4 Development Kit...........................................................................................21 

 
Application Note 2 of 45 001-84858 Rev. *N 
 2021-03-23 
PSoC 4 Programming Using an External Microcontroller (HSSP) 
 
Table of contents 
2 For Kits with Onboard PSoC 5LP Programmer (KitProg).....................................................................21 
3 For Kits with Onboard PSoC 5LP Programmer (KitProg2)...................................................................25 
Tips and Tricks for Debugging HSSP Issues...............................................................................29 
Summary .............................................................................................................................30 
Related Documentation .........................................................................................................31 
1 Application Notes..................................................................................................................................31 
2 Programming Specifications ................................................................................................................31 
3 Architecture Technical Reference Manuals..........................................................................................31 
4 Web Page ...............................................................................................................................................31 
List of Attached Projects ........................................................................................................32 
Appendix A: Hex File Parser Application...................................................................................33 
1 Using the Hex File Parser Application...................................................................................................33 
2 Adding the Generated Files to PSoC Creator Example Project............................................................34 
2.1 Using the HexImage.c, HexImage.h Files for the PSoC 4xxxL/ PSoC 41x8_BLE/ 42x8_BLE/ 41XXS 
Plus Family Devices:.........................................................................................................................36 
Appendix B: Status Codes for SROM Request ............................................................................37 
Appendix C: Bit Field Definitions of HSSP Error Status Register ..................................................39 
1 Bits[2:0] –SWD Acknowledge Response (SWD ACK [2:0])....................................................................39 
2 Bit 3 –SWD Read Data Parity Error .......................................................................................................39 
3 Bit 4 –Port Acquire Timeout.................................................................................................................39 
4 Bit 5 –SROM Polling Timeout Error ......................................................................................................40 
5 Bit 6 –Verification Failure .....................................................................................................................40 
6 Bit 7 –Transition Error ..........................................................................................................................40 
Appendix D: HSSP Functions...................................................................................................41 
Revision history.............................................................................................................................44 
 
 
 
 

Application Note 3 of 45 001-84858 Rev. *N

2021-03-23

PSoC 4 Programming Using an External Microcontroller (HSSP)

Introduction

1Introduction

PSoC 4 device programming refers specifically to the programming of the nonvolatile memory in PSoC 4 by

using an external host programmer. The host can be the programmer supplied by Infineon (CY8CKIT-002

MiniProg3), a third-party programmer, or a custom programmer (for example, an onboard microcontroller).

This application note explains how to implement a host programmer to program a PSoC 4 device. For more

information on the PSoC 4 architecture and to learn how to create projects for PSoC 4 using the PSoC Creator™

software, see AN79953 –Getting Started with PSoC 4.

1.1 Types of Programmers

The type of device programmer you choose depends on the stage of product development:

Prototyping: A programmer must be able to perform the following functions:

1. Program the device.

2. Debug the device to troubleshoot the application.

The programmers used during prototyping must also interact with the integrated design environment (IDE)—

for example, PSoC Creator™—to accomplish the programming and debugging operations. A few examples are

MiniProg3 or the PSoC 5LP Prototyping Kit, which can be used as a low-cost programmer/debugger.

Production: You require a programmer that can program multiple devices. It parses the hex file to extract the

necessary information and implements programming through the programming interface, such as SWD.

There are two major categories of programmers:

•In-system programmers can program the target device directly on the end-application PCB. You can

connect the external programmer to the device’s programming pins to do in-system programming.

•Socket programmers require the target device to be placed on the programmer hardware socket for

programming. After programming, solder the target device to the end-application PCB. Most third-party

production programmers are of the socket type.

In both in-system and socket programming, the programmer implements an HSSP algorithm and generates

signals to program the hex file’s data.

This application note provides the C code to implement an HSSP programmer. You can easily port this C code

to any host microcontroller with minimal changes. By porting, you reduce the time required to develop HSSP

applications for PSoC 4 devices. The project provided with this application note uses a PSoC 5LP device as a

host programmer to program the target device.

Before reading this application note, review the programming specifications document of the respective device

listed in the Related Documentation section. This document explains the programming interface,

programming algorithm, hardware connection, and electrical timing specifications required to program PSoC 4

devices. This application note is a practical implementation of the programming specifications.

1.2 Terms and Definitions

•Serial wire debug (SWD): Developed by ARM, the SWD protocol uses only two wires—SWDCLK (clock) and

SWDIO (bidirectional data line)—to program and debug.

•Debug access port (DAP): DAP is the program/debug interface between SWD and the CPU in PSoC 4 It

includes a debug port (DP) and an access port (AP).

−DP is responsible for the physical connection to the programmer/debugger.

−AP provides the interface between the DAP module and the Cortex-M0 CPU, the flash memory, and so on.

Application Note 4 of 45 001-84858 Rev. *N

2021-03-23

PSoC 4 Programming Using an External Microcontroller (HSSP)

Introduction

•HSSP: HSSP refers to the programming of the target device on the board using a host microcontroller. The

target is programmed through the SWD interface. In this application note, HSSP uses a bit-banging

implementation to program the target device. Bit-banging programming refers to the technique in which

programming pins are manipulated using a software code that resides in the host programmer.

•Differences between bootloading and HSSP: In embedded systems, bootloaders are also used to update the

system firmware. Bootloading and HSSP differ in the following key aspects:

−Bootloaders are used to update the flash memory of the device over a standard communication protocol.

Bootloaders can update only a specific portion of the flash memory, known as the bootloadable area.

−On the other hand, HSSP supports complete programming of the flash memory in the target device.

−Bootloaders can use any standard communication interface (such as, USB, I2C, SPI, and UART) to update

the firmware, while HSSP uses an SWD or JTAG interface to program the flash. PSoC 4 supports only SWD

interfaces.

Application Note 5 of 45 001-84858 Rev. *N

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PSoC 4 Programming Using an External Microcontroller (HSSP)

HSSP Firmware Architecture

2HSSP Firmware Architecture

HSSP for the target device is implemented in multiple layers using modular C code. These layers are as follows:

1. SWD Protocol Physical layer

2. SWD Protocol Packet layer

3. HSSP Programming Steps layer

See Figure 1 for the flow of control among these layers.

Note: See the A_Hssp_Programmer project, which uses PSoC 5LP as the external host programmer,

attached with this application note for the implementation of this firmware.

Figure 1 HSSP Firmware Architecture

The HSSP Programming Steps layer uses the “Fetching Programming Data” interface to extract the

programming data from the source of the data (for example, the hex file data provided by any communication

interface—I2C, SPI, UART, or USB or host flash—as Figure 1 shows. In addition, the “HSSP Programming Step”

layer uses the HSSP Timeout Parameters interface to configure timeouts in its programming APIs.

Host Programmer

SWDIO

SWDCK

XRES(1)

Target PSoC 4

device

RegisterDefines.h,

SWD_PhysicalLayer.h,

SWD_PhysicalLayer.c

SWD Protocol Physical Layer

SWD_PacketLayer.h,

SwdPacketLayer.c

SWD_UpperPacketLayer.h,

Swd_UpperPacketLayer.c

SWD Protocol Packet Layer

Timeout.h,

Timeout.c

HSSP Timeout

Parameters

ProgrammingSteps.h,

ProgrammingSteps.c

HSSP Programming Steps

DataFetch.h,

DataFetch.c

Fetching Programming

Data

HexImage.h,

HexImage.c

Programming

Data

main.c

Main application code

Device Acquire

Verify Silicon ID

Erase all Flash

Checksum Privileged Calculation

Program Flash

Exit HSSP Programming mode

Verify Flash

Program Protection Settings

Verify Protection Settings

Verify Checksum

HSSP Implementation Flow

10.

(1)For power cycle mode programming, device power rails need to be

toggled instead of the reset (XRES) pin

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PSoC 4 Programming Using an External Microcontroller (HSSP)

HSSP Firmware Architecture

All layers used in the firmware architecture, as shown in Figure 1, are discussed in the following sections.

2.1 SWD Protocol Physical Layer

Files that constitute the SWD Protocol Physical layer are described:

Table 1 SWD Protocol Physical Layer Files

Source Files

Description

RegisterDefines

(.hfile)

This file defines the port number, pin number, input/output register, and drive mode

SWD_PhysicalLayer

(.c and .hfiles)

These files contain macros and functions to manipulate the programming pins. The

pins are defined in the RegisterDefines.h file.

The codes in these files are written for PSoC 5LP as the host microcontroller. If these files are ported to any

other host microcontroller, then you should modify all the functions and macros appropriately.

Note: See “Pin Names and Requirements” in the programming specifications of the respective device

listed in the Related Documentation section for details on the pin configurations on the host side.

2.2 SWD Protocol Packet Layer

Files that constitute the SWD Protocol Packet layer are described:

Table 2 SWD Protocol Packet Layer Files

Source Files

Description

SWD_PacketLayer

(.cand .hfiles)

These files define the packet routines for sending the SWD Read and

SWD Write packets per the SWD protocol.

SWD_UpperPacketLayer

(.cand .hfiles)

These files use the functions defined in SWD_PacketLayer to

implement functions that directly read and write to the DAP register

and CPU address space.

The functions defined in this layer are called directly by the functions in the ProgrammingSteps.c file.

All of these SWD packet functions operate on three global variables—swd_PacketHeader,

swd_PacketAck, and swd_PacketData[]—that are accessed by the functions in the top layer files, as

Figure 1 shows.

2.3 Fetching Programming Data

Files used for fetching the programming data to the upper layer functions are described:

Table 3 Data Fetch Layer File

Source File

Description

DataFetch

(.cand .hfiles)

These files contain the routines to fetch the programming data from the HexImage.c file

and then pass that data to the functions in the ProgrammingSteps.c file.

The programming data includes flash row data, flash protection data, chip protection

data, Silicon ID, checksum, and the total number of flash rows.

Modify the definitions of the functions based on the method that you use to get the HSSP programming data.

Application Note 7 of 45 001-84858 Rev. *N

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PSoC 4 Programming Using an External Microcontroller (HSSP)

HSSP Firmware Architecture

Note: See the section Interface for Receiving HSSP Programming Data for information on how to

modify the HSSP source code.

2.4 HSSP Programming Steps

This layer includes the files named ProgrammingSteps.c and ProgrammingSteps.h. These files contain the top-

level functions of the HSSP application. These functions are described in sequence as follows:

1. Device Acquire: In this step, the device is acquired by sending a specific sequence through the SWD

interface after a device reset. As a result, the host programmer can control the Cortex-M0 CPU and other

system resources, such as SRAM and registers. The PSoC 40xx, PSoC 4xx7_BLE, PSoC 40xxS PSoC 41xxS and

PSoC 4100PS family of devices requires the internal main oscillator (IMO) frequency to be set at 48 MHz

before flash erase/write operations. This operation is also included in the Device Acquire routine for these

devices.

Note: Some of the devices in the PSoC 4000 family do not have a dedicated reset (XRES) pin, and have to

be reset by toggling the device power rails. This is referred to as Power Cycle Mode programming.

Refer to the Power Cycle Mode Programming section for details on the changes required for

modifying the code to support power cycle mode programming.

2. Verify Silicon ID: This step verifies that the acquired device is the same as the one for which the hex file was

generated.

3. Erase All Flash: This step erases all user rows and corresponding flash protection.

4. Checksum Privileged Calculation: After all the user rows are erased, this step calculates the checksum of

the privileged rows, which is used to verify the checksum of the user rows in Step 9.

5. Program Flash: In this step, flash is programmed using the programming data in the hex file and SROM API

calls.

6. Verify Flash: This step is used to verify the flash data programmed in the previous step with the data in the

hex file. This step is optional but highly recommended.

7. Program Protection Settings: In this step, row protection settings and chip protection settings from the

hex file are written to the specific flash area.

8. Verify Protection Settings: Both protection settings are matched with the settings in the hex file.

9. Verify Checksum: This step matches the checksum of the user data in the flash with the checksum in the

hex file. It uses the checksum of the privileged rows calculated in step 4.

10.Exit HSSP Programming Mode: This step releases the target device from programming mode.

Each of these steps is described by functions made up of basic SWD instructions. See the programming

specifications document of the respective device listed in the Related Documentation section for detailed

information.

The functions declared in the ProgrammingSteps.h file access the functions, definitions, and global variables

from three layers: SWD Protocol Packet layer, DataFetch layer, and Timeout layer. The functions provided in the

ProgrammingSteps.c and ProgrammingSteps.h files cover all the steps required to program the target device.

2.5 HSSP Timeout Parameters

Table 4 Timeout Layer Files

Source File

Description

Timeout (.c and .h

files)

These files contain the timestamp definitions and the delay routines used in HSSP.

Application Note 8 of 45 001-84858 Rev. *N

2021-03-23

PSoC 4 Programming Using an External Microcontroller (HSSP)

HSSP Firmware Architecture

Timestamp definitions are derived from the electrical timing specifications provided in the Device

Programming Specifications. The values of these timestamp parameter definitions in Timeout.h are for a

PSoC 5LP host programmer running at a clock frequency of 63 MHz.

Timestamp definitions and the delay routine are used in the function definitions in the ProgrammingSteps.c

file.

To learn how to calculate the timestamp parameters for a specific host programmer, see the section

Calculating HSSP Timeout Parameters.

2.6 HSSP Programming Data

Files that contain the programming data to be stored in the host programmer are described:

Table 5 Files Containing the Programming Data

Source Files

Description

HexImage

(.cand .hfiles)

These files contain the data to be programmed into the target device.

They also store the target device parameters used in HSSP programming, such as silicon ID,

checksum, total number of flash rows, and number of bytes per flash row.

The data in these files is stored in PSoC 5LP flash memory as an array of constants.

These files are generated by the C# application Hex File Parser, which is provided with this application note.

This application generates these files by taking the target device hex file as the input. The details of this

application are provided in Appendix A.

For details on the hex file format, see “Appendix B. Intel Hex File Format” in the programming specifications

document of the respective device listed in the Related Documentation section of this document.

For host programmers that lack the memory capacity to store the programming data in the on-chip memory,

the HexImage.c and HexImage.h files are not required. In such cases, the HSSP programming data is typically

sent to the host as packets through a communication interface, such as I2C, UART, or USB.

Note: See the section Interface for Receiving HSSP Programming Data for information on modifying

the HSSP source code according to the method used to get the programming data.

2.7 Main Application Code

The main.c file is the main application code that calls the top-level HSSP programming steps in the sequence

shown in Figure 1. The function ProgramDevice() in main.c executes all the steps. Each step must be

executed successfully before you can proceed to the next step.

The HSSP operation is aborted if a FAILURE is returned after any step. The error status returned by the

ReadHsspErrorStatus()function is used to identify the cause of the error. The status of the HSSP

operation, along with the error status register, is displayed on a character LCD in the attached HSSP project.

Note: The character LCD and Pin_Start routines are specific to the PSoC 5LP host programmer and,

therefore, should be modified as required for any other host programmer.

2.8 HSSP Error Status

When any of the top-level steps in the HSSP application returns a failure status, the

ReadHsspErrorStatus() function is called from the main application code to get the details of the error.

Application Note 9 of 45 001-84858 Rev. *N

2021-03-23

PSoC 4 Programming Using an External Microcontroller (HSSP)

HSSP Firmware Architecture

This function returns the status byte. Use the status byte to infer error details from the bit field definitions.

See Figure 2 for the bit fields returned by this function.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SWD ACK [2:0] response

SWD Read Data

Parity Error

SROM Polling Timeout

Port Acquire Timeout

Transition Error

Verification Failure

Figure 2 HSSP Error Status Register

Table 6 describes the bit field definitions of this status register.

Table 6 HSSP Error Status Register

Bit

Field Name

Description

[2:0]

SWD ACK

These three bits store the acknowledge response of previous SWD

transactions.

SWD Read Data Parity

Error

If this bit is set, it indicates a parity error in the data received by the host.

Port Acquire Timeout

If this bit is set, it indicates that the device was not acquired within the

timeout window.

SROM Polling Timeout

If this bit is set, It indicates that SROM operations exceed 1 second.

Verification Failure

This bit is set in multiple steps. Depending upon the step where failure

occurred, the reason can be inferred.

Transition Error

If this bit is set, it indicates that the chip protection settings read from the

chip and the hex file indicates a wrong transition.

To learn more about this register and for a detailed explanation of the bit fields, see Appendix C: Bit Field

Definitions of HSSP Error Status Register.

Application Note 10 of 45 001-84858 Rev. *N

2021-03-23

PSoC 4 Programming Using an External Microcontroller (HSSP)

Hardware Connections for HSSP Programming

3Hardware Connections for HSSP Programming

HSSP programming in PSoC 4 uses the SWD interface pins (SWDIO and SWDCK) and the external reset pin

(XRES). The host programmer pin drive mode requirements are explained in the “Physical Layer”section in the

programming specifications document listed in the Related Documentation section of this document. Figure

3shows the basic hardware connection required between the host programmer and the target device.

Host

Programmer PSoC 40xx

VDD VDDD

SWDCK

XRES

SWDIO

GND

SWDCK ( P3[1]] )

XRES(1)

SWDIO ( P3[0] )

GND

VSSD

1.8 V –5.5 V

0.1 uF

Host

Programmer PSoC 4xxx/

PSoC 4xxxM/

PSoC 4xxxL/PSoC 40xxS/PSoC

41xxS/ PSoC 4100PS/ PSoC

4100S Plus

VDD VDDD

SWDCK

XRES

SWDIO

GND

SWDCK ( P3[3]] )

XRES

SWDIO ( P3[2] )

VDD

GND

VSSD

1.8 V –5.5 V

0.1 uF

Host

Programmer PSoC 4xx7_BLE/

PSoC 4xx8_BLE

VDD VDDD

SWDCK

XRES

SWDIO

GND

SWDCK ( P0[7] )

XRES

SWDIO ( P0[6] )

VDD

GND

VSSD

1.8 V –5.5 V

0.1 uF

(1) Toggle VDDD pin for devices

that do not have an XRES pin

Figure 3 Basic Host/Target Connections

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