GE MiCOM P40 Agile Manual de usuario

GE Energy Connections

Grid Solutions

MiCOM P40 Agile

P14D

Technical Manual

Feeder Management IED

Hardware Version: A

Software Version: 60

Publication Reference: P14D-TM-EN-8

Contents

Chapter 1 Introduction 1

1 Chapter Overview 3

2 Foreword 4

2.1 Target Audience 4

2.2 Typographical Conventions 4

2.3 Nomenclature 5

2.4 Compliance 5

3 Product Scope 6

3.1 Ordering Options 6

4 Features and Functions 7

4.1 Protection Functions 7

4.2 Control Functions 8

4.3 Measurement Functions 9

4.4 Communication Functions 9

5 Logic Diagrams 10

6 Functional Overview 11

Chapter 2 Safety Information 13

1 Chapter Overview 15

2 Health and Safety 16

3 Symbols 17

4 Installation, Commissioning and Servicing 18

4.1 Lifting Hazards 18

4.2 Electrical Hazards 18

4.3 UL/CSA/CUL Requirements 19

4.4 Fusing Requirements 19

4.5 Equipment Connections 20

4.6 Protection Class 1 Equipment Requirements 20

4.7 Pre-energisation Checklist 21

4.8 Peripheral Circuitry 21

4.9 Upgrading/Servicing 22

5 Decommissioning and Disposal 23

6 Regulatory Compliance 24

6.1 EMC Compliance: 2014/30/EU 24

6.2 LVD Compliance: 2014/35/EU 24

6.3 R&TTE Compliance: 2014/53/EU 24

6.4 UL/CUL Compliance 24

6.5 ATEX Compliance: 2014/34/EU 24

Chapter 3 Hardware Design 27

1 Chapter Overview 29

2 Hardware Architecture 30

2.1 Memory and Real Time Clock 30

3 Mechanical Implementation 31

3.1 Housing Variants 31

3.2 20TE Rear Panel 32

3.3 30TE Rear Panel 32

4 Terminal Connections 35

4.1 I/O Options 35

5 Front Panel 36

5.1 20TE Front Panel 36

5.2 30TE Front Panel 37

5.3 Keypad 37

5.4 Liquid Crystal Display 38

5.5 USB Port 38

5.6 Fixed Function LEDs 39

5.7 Function Keys 39

5.8 Programable LEDs 39

Chapter 4 Software Design 41

1 Chapter Overview 43

2 Software Design Overview 44

3 System Level Software 45

3.1 Real Time Operating System 45

3.2 System Services Software 45

3.3 Self-Diagnostic Software 45

3.4 Startup Self-Testing 45

3.4.1 System Boot 45

3.4.2 System Level Software Initialisation 46

3.4.3 Platform Software Initialisation and Monitoring 46

3.5 Continuous Self-Testing 46

4 Platform Software 47

4.1 Record Logging 47

4.2 Settings Database 47

4.3 Interfaces 47

5 Protection and Control Functions 48

5.1 Acquisition of Samples 48

5.2 Frequency Tracking 48

5.3 Fourier Signal Processing 48

5.4 Programmable Scheme Logic 49

5.5 Event Recording 49

5.6 Disturbance Recorder 50

5.7 Fault Locator 50

5.8 Function Key Interface 50

Chapter 5 Configuration 51

1 Chapter Overview 53

2 Settings Application Software 54

3 Using the HMI Panel 55

3.1 Navigating the HMI Panel 56

3.2 Getting Started 56

3.3 Default Display 57

3.4 Default Display Navigation 58

3.5 Password Entry 59

3.6 Processing Alarms and Records 59

3.7 Menu Structure 60

3.8 Changing the Settings 61

3.9 Direct Access (The Hotkey menu) 62

3.9.1 Setting Group Selection Using Hotkeys 62

3.9.2 Control Inputs 62

3.9.3 Circuit Breaker Control 63

3.10 Function Keys 63

4 Date and Time Configuration 65

4.1 Time Zone Compensation 65

4.2 Daylight Saving Time Compensation 65

5 Settings Group Selection 66

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ii P14D-TM-EN-8

Chapter 6 Current Protection Functions 67

1 Chapter Overview 69

2 Overcurrent Protection Principles 70

2.1 IDMT Characteristics 70

2.1.1 IEC 60255 IDMT Curves 71

2.1.2 European Standards 73

2.1.3 North American Standards 74

2.1.4 IEC and IEEE Inverse Curves 76

2.1.5 Differences Between the North american and European Standards 77

2.1.6 Programmable Curves 77

2.2 Principles of Implementation 77

2.2.1 Timer Hold Facility 78

3 Phase Overcurrent Protection 80

3.1 Phase Overcurrent Protection Implementation 80

3.2 Non-Directional Overcurrent Logic 81

3.3 Directional Element 82

3.3.1 Directional Overcurrent Logic 84

3.4 Phase Overcurrent Settings for Model H 84

3.5 Application Notes 85

3.5.1 Parallel Feeders 85

3.5.2 Ring Main Arrangements 86

3.5.3 Setting Guidelines 86

3.5.4 Setting Guidelines (Directional Element) 87

4 Voltage Dependent Overcurrent Element 88

4.1 Voltage Dependent Overcurrent Protection Implementation 88

4.1.1 Voltage Controlled Overcurrent Protection 88

4.1.2 Voltage Restrained Overcurrent Protection 89

4.2 Voltage Dependent Overcurrent Logic 90

4.3 Application Notes 90

4.3.1 Setting Guidelines 90

5 Current Setting Threshold Selection 92

6 Negative Sequence Overcurrent Protection 93

6.1 Negative Sequence Overcurrent Protection Implementation 93

6.2 Non-Directional Negative Sequence Overcurrent Logic 94

6.3 Directional Element 94

6.3.1 Directional Negative Sequence Overcurrent Logic 94

6.4 Application Notes 95

6.4.1 Setting Guidelines (Current Threshold) 95

6.4.2 Setting Guidelines (Time Delay) 95

6.4.3 Setting Guidelines (Directional element) 95

7 Earth Fault Protection 97

7.1 Earth Fault Protection Elements 97

7.2 Non-directional Earth Fault Logic 98

7.3 IDG Curve 98

7.4 Directional Element 99

7.4.1 Residual Voltage Polarisation 99

7.4.2 Negative Sequence Polarisation 101

7.5 Application Notes 102

7.5.1 Setting Guidelines (Directional Element) 102

7.5.2 Peterson Coil Earthed Systems 103

7.5.3 Setting Guidelines (Compensated networks) 106

8 Sensitive Earth Fault Protection 107

8.1 SEF Protection Implementation 107

8.2 Non-directional SEF Logic 107

8.3 EPATR B Curve 108

8.4 Directional Element 108

8.4.1 Wattmetric Characteristic 109

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P14D-TM-EN-8 iii

8.4.2 Icos phi / Isin phi characteristic 110

8.4.3 Directional SEF Logic 112

8.5 Application Notes 112

8.5.1 Insulated Systems 112

8.5.2 Setting Guidelines (Insulated Systems) 114

9 Cold Load Pickup 116

9.1 Implementation 116

9.2 CLP Logic 116

9.3 Application Notes 117

9.3.1 CLP for Resistive Loads 117

9.3.2 CLP for Motor Feeders 117

9.3.3 CLP for Switch Onto Fault Conditions 117

10 Selective Logic 118

10.1 Selective Logic Implementation 118

10.2 Selective Logic Diagram 118

11 Timer Setting Selection 120

12 Thermal Overload Protection 121

12.1 Single Time Constant Characteristic 121

12.2 Dual Time Constant Characteristic 121

12.3 Thermal Overload Protection Implementation 122

12.4 Thermal Overload Protection Logic 122

12.5 Application Notes 122

12.5.1 Setting Guidelines for Dual Time Constant Characteristic 122

12.5.2 Setting Guidelines for Single Time Constant Characteristic 124

13 Broken Conductor Protection 126

13.1 Broken Conductor Protection Implementation 126

13.2 Broken Conductor Protection Logic 126

13.3 Application Notes 126

13.3.1 Setting Guidelines 126

14 Blocked Overcurrent Protection 128

14.1 Blocked Overcurrent Implementation 128

14.2 Blocked Overcurrent Logic 128

14.3 Blocked Earth Fault Logic 128

14.4 Application Notes 129

14.4.1 Busbar Blocking Scheme 129

15 Second Harmonic Blocking 131

15.1 Second Harmonic Blocking Implementation 131

15.2 Second Harmonic Blocking Logic (POC Input) 132

15.3 Application Notes 132

15.3.1 Setting Guidelines 132

16 Load Blinders 133

16.1 Load Blinder Implementation 133

16.2 Load Blinder Logic 134

17 Neutral Admittance Protection 136

17.1 Neutral Admittance Operation 136

17.2 Conductance Operation 136

17.3 Susceptance Operation 137

18 High Impedance Fault Detection 139

18.1 High Impedance Fault Protection Implementation 139

18.1.1 Fundamental Analysis 139

18.1.2 Component Harmonic Analysis 140

18.1.3 Directional Analysis 140

18.1.4 Summary 141

18.2 High Impedance Fault Protection Logic 142

Chapter 7 Restricted Earth Fault Protection 143

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iv P14D-TM-EN-8

1 Chapter Overview 145

2 REF Protection Principles 146

2.1 Resistance-Earthed Star Windings 147

2.2 Solidly-Earthed Star Windings 147

2.3 Through Fault Stability 148

2.4 Restricted Earth Fault Types 148

2.4.1 Low Impedance REF Principle 148

2.4.2 High Impedance REF Principle 149

3 Restricted Earth Fault Protection Implementation 151

3.1 Restricted Earth Fault Protection Implementation 151

3.2 Low Impedance REF 151

3.2.1 Setting the Bias Characteristic 151

3.2.2 Delayed Bias 152

3.2.3 Transient Bias 152

3.3 High Impedance REF 152

3.3.1 High Impedance REF Calculation Principles 152

4 Application Notes 154

4.1 Star Winding Resistance Earthed 154

4.2 Low Impedance REF Protection Application 155

4.2.1 Setting Guidelines for Biased Operation 155

4.2.2 Low Impedance REF Scaling Factor 155

4.2.3 Parameter Calculations 155

4.3 High Impedance REF Protection Application 156

4.3.1 High Impedance REF Operating Modes 156

4.3.2 Setting Guidelines for High Impedance Operation 157

Chapter 8 CB Fail Protection 161

1 Chapter Overview 163

2 Circuit Breaker Fail Protection 164

3 Circuit Breaker Fail Implementation 165

3.1 Circuit Breaker Fail Timers 165

3.2 Zero Crossing Detection 165

4 Circuit Breaker Fail Logic 167

5 Undercurrent and ZCD Logic for CB Fail 169

6 CB Fail SEF Protection Logic 170

7 CB Fail Non Current Protection Logic 171

8 Circuit Breaker Mapping 172

9 Application Notes 173

9.1 Reset Mechanisms for CB Fail Timers 173

9.2 Setting Guidelines (CB fail Timer) 173

9.3 Setting Guidelines (Undercurrent) 174

Chapter 9 Current Transformer Requirements 175

1 Chapter Overview 177

2 CT requirements 178

2.1 Phase Overcurrent Protection 178

2.1.1 Directional Elements 178

2.1.2 Non-directional Elements 178

2.2 Earth Fault Protection 179

2.2.1 Directional Elements 179

2.2.2 Non-directional Elements 179

2.3 SEF Protection (Residually Connected) 179

2.3.1 Directional Elements 179

2.3.2 Non-directional Elements 179

2.4 SEF Protection (Core-Balanced CT) 180

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P14D-TM-EN-8 v

2.4.1 Directional Elements 180

2.4.2 Non-directional Elements 180

2.5 Low Impedance REF Protection 180

2.6 High Impedance REF Protection 180

2.7 High Impedance Busbar Protection 181

2.8 Use of Metrosil Non-linear Resistors 181

2.9 Use of ANSI C-class CTs 183

Chapter 10 Voltage Protection Functions 185

1 Chapter Overview 187

2 Undervoltage Protection 188

2.1 Undervoltage Protection Implementation 188

2.2 Undervoltage Protection Logic 189

2.3 Application Notes 190

2.3.1 Undervoltage Setting Guidelines 190

3 Overvoltage Protection 191

3.1 Overvoltage Protection Implementation 191

3.2 Overvoltage Protection Logic 192

3.3 Application Notes 192

3.3.1 Overvoltage Setting Guidelines 192

4 Rate of Change of Voltage Protection 194

4.1 Rate of Change of Voltage Protection Implementation 194

4.2 Rate of Change of Voltage Logic 194

5 Residual Overvoltage Protection 196

5.1 Residual Overvoltage Protection Implementation 196

5.2 Residual Overvoltage Logic 197

5.3 Application Notes 197

5.3.1 Calculation for Solidly Earthed Systems 197

5.3.2 Calculation for Impedance Earthed Systems 198

5.3.3 Neutral Voltage Displacement (Nvd) Protection Applied To Condenser Bushings (Capacitor Cones) 199

5.3.4 Setting Guidelines 203

6 Negative Sequence Overvoltage Protection 204

6.1 Negative Sequence Overvoltage Implementation 204

6.2 Negative Sequence Overvoltage Logic 204

6.3 Application Notes 204

6.3.1 Setting Guidelines 204

7 Positive Sequence Undervoltage Protection 206

7.1 Positive Sequence Undervoltage Implementation 206

7.2 Positive Sequence Undervoltage Logic 206

8 Positive Sequence Overvoltage Protection 207

8.1 Positive Sequence Overvoltage Implementation 207

8.2 Positive Sequence Overvoltage Logic 207

9 Moving Average Voltage Functions 208

9.1 Moving Average Undervoltage Logic 208

9.2 Moving Average Overvoltage Logic 209

9.3 Moving Average Zero Sequence Voltage Logic 209

9.4 Moving Average Positive Sequence Voltage Logic 209

9.5 Moving Average Negative Sequence Voltage Logic 210

9.6 Moving Average Undervoltage Blocking PSL 210

10 Voltage Vector Shift Protection 211

10.1 Application Notes 211

10.2 Voltage Vector Shift Calculations 211

Chapter 11 Frequency Protection Functions 215

1 Chapter Overview 217

Contents P14D

vi P14D-TM-EN-8

2 Frequency Protection Overview 218

2.1 Frequency Protection Implementation 218

3 Underfrequency Protection 219

3.1 Underfrequency Protection Implementation 219

3.2 Underfrequency Protection Logic 219

3.3 Application Notes 219

3.3.1 Setting Guidelines 219

4 Overfrequency Protection 221

4.1 Overfrequency Protection Implementation 221

4.2 Overfrequency Protection Logic 221

4.3 Application Notes 221

4.3.1 Setting Guidelines 221

5 Independent R.O.C.O.F Protection 223

5.1 Indepenent R.O.C.O.F Protection Implementation 223

5.2 Independent R.O.C.O.F Protection Logic 223

5.3 Application Notes 224

5.3.1 Setting Guidelines 224

6 Frequency-supervised R.O.C.O.F Protection 225

6.1 Frequency-supervised R.O.C.O.F Implementation 225

6.2 Frequency-supervised R.O.C.O.F Logic 226

6.3 Application Notes 226

6.3.1 Frequency-Supervised R.O.C.O.F Example 226

6.3.2 Setting Guidelines 227

7 Average Rate of Change of Frequency Protection 228

7.1 Average R.O.C.O.F Protection Implementation 228

7.2 Average R.O.C.O.F Logic 229

7.3 Application Notes 229

7.3.1 Setting Guidelines 229

8 Load Shedding and Restoration 231

8.1 Load Restoration Implementation 231

8.2 Holding Band 231

8.3 Load Restoration Logic 233

8.4 Application Notes 234

8.4.1 Setting Guidelines 234

Chapter 12 Power Protection Functions 235

1 Chapter Overview 237

2 Overpower Protection 238

2.1 Overpower Protection Implementation 238

2.2 Overpower Logic 238

2.3 Application Notes 239

2.3.1 Forward Overpower Setting Guidelines 239

2.3.2 Reverse Power Considerations 239

2.3.3 Reverse Overpower Setting Guidelines 239

3 Underpower Protection 241

3.1 Underpower Protection Implementation 241

3.2 Underpower Logic 242

3.3 Application Notes 242

3.3.1 Low Forward Power Considerations 242

3.3.2 Low Forward Power Setting Guidelines 242

4 Sensitive Power Protection 244

4.1 Sensitive Power Protection Implementation 244

4.2 Sensitive Power Measurements 244

4.3 Sensitive Power Logic 245

4.4 Application Notes 245

4.4.1 Sensitive Power Calculation 245

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P14D-TM-EN-8 vii

4.4.2 Sensitive Power Setting Guidelines 247

5 Wattmetric Directional Earth Fault Protection 248

5.1 WDE Implementation 249

5.2 WDE Logic 249

Chapter 13 Autoreclose 251

1 Chapter Overview 253

2 Introduction to 3-phase Autoreclose 254

3 Implementation 255

4 Autoreclose Function Inputs 256

4.1 CB Healthy 256

4.2 Block AR 256

4.3 Reset Lockout 256

4.4 AR Auto Mode 256

4.5 AR LiveLine Mode 256

4.6 Telecontrol Mode 256

4.7 Live/Dead Ccts OK (Live/Dead Circuits OK) 256

4.8 AR Sys Checks (AR System Checks) 256

4.9 Ext AR Prot Trip (External AR Protection Trip) 257

4.10 Ext AR Prot Start (External AR Protection Start) 257

4.11 DAR Complete (Delayed Autoreclose Complete) 257

4.12 CB in Service (Circuit Breaker in Service) 257

4.13 AR Restart 257

4.14 DT OK To Start (Dead Time OK to Start) 257

4.15 DeadTime Enabled 257

4.16 AR Init TripTest (Initiate Trip Test) 258

4.17 AR Skip Shot 1 258

4.18 Inh Reclaim Time (Inhibit Reclaim Time) 258

5 Autoreclose Function Outputs 259

5.1 AR In Progress 259

5.2 DAR In Progress 259

5.3 Sequence Counter Status DDB signals 259

5.4 Successful Close 259

5.5 AR In Service 259

5.6 AR Blk Main Prot (Block Main Protection) 259

5.7 AR Blk SEF Prot (Block SEF Protection) 259

5.8 Reclose Checks 259

5.9 DeadTime In Prog 260

5.10 DT Complete (Dead Time Complete) 260

5.11 AR Sync Check (AR Synchronisation Check) 260

5.12 AR SysChecks OK (AR System Checks OK) 260

5.13 Auto Close 260

5.14 Protection Lockt (Protection Lockout) 260

5.15 Reset Lckout Alm (Reset Lockout Alarm) 260

5.16 Reclaim In Prog 260

5.17 Reclaim Complete 260

6 Autoreclose Function Alarms 261

6.1 AR No Sys Check 261

6.2 AR CB Unhealthy 261

6.3 AR Lockout 261

7 Autoreclose Operation 262

7.1 Operating Modes 262

7.1.1 Four-Position Selector Switch Implementation 263

7.1.2 Operating Mode Selection Logic 264

7.2 Autoreclose Initiation 264

7.2.1 Start Signal Logic 265

Contents P14D

viii P14D-TM-EN-8

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