Epson S5U13506P00C100 Manual de usuario

S1D13506 LCD/CRT/TV Controller

S5U13506P00C100 PCI Evaluation

Board User Manual

Document Number: X25B-G-014-02

Status: Revision 2.0

Issue Date: 2009/03/02

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners.

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Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 Non-PCI Host Interface Support . . . . . . . . . . . . . . . . . . . . . . . 14

4.2.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 LCD Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.1 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3.2 Buffered LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4 CRT/TV Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.1 CRT/TV Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.2 CRT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.3 TV Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . 21

5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.1 EPSON LCD/CRT Controllers (S1D13506) . . . . . . . . . . . . . . . . . . 31

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1 Introduction

This manual describes the setup and operation of the S5U13505P00C100 PCI Evaluation

Board. The S5U13506P00C100 is designed as an evaluation platform for the S1D13506

Color LCD/CRT/TV Controller chip.

This document is updated as appropriate. Please check the Epson Research and Devel-

opment website at http://www.erd.epson.com for the latest revision of this document before

beginning any development.

We appreciate your comments on our documentation. Please contact us via email at

documentati[email protected].

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2 Features

The S5U13506P00C100 features the following:

• S1D13506 Color LCD/CRT/TV controller chip

• PCI bus operation using on-board PCI bridge

• Headers for connecting to a 3.3V host bus interface (5V host bus interface also possible

with modifications to the board)

• 1Mx16 EDO DRAM

• Configuration options

• Headers for S1D13506 current consumption measurements

• 4/8-bit 3.3V or 5V monochrome passive LCD panel support

• 4/8/16-bit 3.3V or 5V color passive LCD panel support

• 9/12/18-bit 3.3V or 5V TFT/D-TFD LCD panel support

• Embedded RAMDAC for CRT and TV support

• Software initiated Power Save Mode

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3 Installation and Configuration

The S5U13506P00C100 is designed to support as many platforms as possible. The board

incorporates a DIP switch and several jumpers which allow both evaluation board and

S1D13506 LCD controller settings to be configured for a specified evaluation platform.

3.1 Configuration DIP Switches

The S1D13506 LCD controller has 16 configuration inputs (MD[15:0]) which are read on

the rising edge of RESET#. Where appropriate, the S5U13506P00C100 hard-wires some

of these configuration inputs, but in order to configure the S1D13505 for multiple host bus

interfaces an eight-position DIP switch is required. The following figure shows the location

of DIP switch S1 on the S5U13506P00C100 board.

Figure 3-1: Configuration DIP Switch (S1) Location

DIP Switch - S1

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The following DIP switch settings configure the S1D13506.

The following table shows the Host Bus Interface options available. The host bus interface

is selected according to the evaluation platform to be used.

Table 3-1: Configuration DIP Switch Settings

Switch Signal Value of this pin at rising edge of RESET# is used to configure:

Closed/On=1 Open/Off=0

S1-1 MD15 WAIT# is always driven. WAIT# is tristated when S1D13506 is not selected

S1-2 MD1

See Table 3-2:, “Host Bus Interface Selection” on page 8S1-3 MD2

S1-4 MD3

S1-5 MD4 Little Endian Big Endian

S1-6 MD5 WAIT# is active high WAIT# is active low

S1-7 MD11 See Table 3-2:, “Host Bus Interface Selection” on page 8

S1-8 MD12 BUSCLK input divided by 2 BUSCLK input not divided

= Required configuration when used in a PCI environment

Table 3-2: Host Bus Interface Selection

MD11 MD3 MD2 MD1 Host Bus Interface

0000 SH-4/SH-3

0 0 0 1 MC68K Bus 1

0 0 1 0 MC68K Bus 2

0 0 1 1 Generic

0100 Reserved

0101 MIPS/ISA

0110 PowerPC

0111 PCCard

1 1 1 1 Philips PR31500/PR31700 / Toshiba TX3912

= Required configuration when used in a PCI environment

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3.2 Configuration Jumpers

The S5U13505B00C has seven jumper blocks which configure various board settings. The

jumper positions for each function are shown below.

JP1 - BUSCLK Selection

JP1 selects the source for BUSCLK.

When the jumper is at position 1-2, the BUSCLK source is provided by the oscillator at U2

(default setting).

When the jumper is at position 2-3, the BUSCLK source is provided by the non-PCI host

system.

Note

When used in a PCI environment, JP1 must be set to the 1-2 position.

Figure 3-2: Configuration Jumper (JP1) Location

Table 3-3: Jumper Settings

Jumper Function Position 1-2 Position 2-3 Jumper Off

JP1 BUSCLK Selection BUSCLK from U2 oscillator BUSCLK from H2 header n/a

JP2 CLKI Selection CLKI from U3 oscillator CLKI is the same as BUSCLK n/a

JP3 VDD current Normal operation n/a Current measurement for

VDD

JP4 DACVDD current Normal operation n/a Current measurement for

DACVDD

JP5 LCD Panel Voltage +5V LCDVCC +3.3V LCDVCC n/a

JP6 Panel Enable Polarity LCDPWR active high LCDPWR active low n/a

JP7 PCI FPGA enable Disable FPGA for non-PCI

host n/a Enable FPGA for PCI host

JP8 IREF for CRT/TV DAC 4.6mA for CRT 9.2mA for TV n/a

= Default configuration

JP1

BUSCLK

BUSCLK from

Oscillator (U2) from H2

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JP2 - CLKI Selection

JP2 selects the source for CLKI.

When the jumper is at position 1-2, the CLKI source is provided by the oscillator at U3

(default setting).

When the jumper is at position 2-3, the CLKI source is the same as BUSCLK (provided by

the non-PCI host system).

Figure 3-3: Configuration Jumper (JP2) Location

JP3 - VDD current

JP3 allows the measurement of S1D13505 VDD current consumption.

When the jumper is at position 1-2, the evaluation board is operating normally (default

setting).

When no jumper is installed, VDD current consumption can be measured by connecting an

ammeter to JP3.

Figure 3-4: Configuration Jumper (JP3) Location

JP2

CLKI from

Oscillator (U3)

CLKI same

as BUSCLK

JP3

CoreVDDNormal

Operation Measurement

Tabla de contenidos

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