Epson S1D13709 Manual de usuario

S1D13709

Embedded Memory Graphics LCD Controller

S5U13709P00C100 Evaluation

Board User Manual Rev.1.0

Document Number: xa8a-g-001

Status: Revision 1.0

Issue Date: July 31 2014

SEIKO EPSON CORPORATION

Evaluation board/kit and Development tool important notice

1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or

development purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for

finished products.

2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer

product. The user should use it properly and in a safe manner. Seiko Epson dose not assume any responsibility or

liability of any kind of damage and/or fire caused by the use of it. The user should cease to use it when any abnormal

issue occurs even during proper and safe use.

3. The part used for this evaluation board/kit or development tool may be changed without any notice.

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of

Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not

assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use

in any product or circuit and, further, there is no representation that this material is applicable to products requiring high

level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by

implication or otherwise, and there is no representation or warranty that anything made in accordance with this material

will be free from any patent or copyright infringement of a third party. When exporting the products or technology

described in this material, you should comply with the applicable export control laws and regulations and follow the

procedures required by such laws and regulations. You are requested not to use, to resell, to export and/or to otherwise

dispose of the products (and any technical information furnished, if any) for the development and/or manufacture of

weapon of mass destruction or for other military purposes.

All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.

Table of Contents

1. Introduction……………………………………................................................4

2. Features……………………………………………………………………………5

3. Installation and Configuration…………………………………………………6

3.1. Switches………………………………………………………….…………6

3.2. Configuration Jumpers…………………………………………………….8

3.3. Power Supply………………………………………………..……………10

3.3.1 HIOVDD, NIOVDD, COREVDD, PLLVDD……………….….…10

3.3.2 Backlight Power Supply for LCD panel…………………………10

4. Connectors……………………………………………………………………….11

4.1 P1, P2 Host Interface Connector.............................................................12

4.2 H1, H2 Host Interface Connector………………………….……….………12

4.3 H3, H4 Panel Interface Connector..........................................................12

5. Technical Description…………………………………………….....…………13

5.1 Current measurement.............................................................................13

5.2 Clock source select……………………………………….……...………….13

5.3 Hardware reset……………………………………………......…….……….13

6. Parts List……………………………………………………………….…...……14

7. Schematic Diagram………………………………………………………..……16

8. S5U13709C00P100 Board Layout………………………………………...….20

9. Reference……………………………………………………………………...…21

9.1 Documents……………………………..……………………………..…..21

9.2 Document Sources……………………………..………………………..21

Appendix A Installation Guide for the S5U13U00C00P00.....……..…………22

A.1 Installation and connecting……………….…………………………………22

Appendix B Using the panel I/F board…………….……………………….……25

B.1 connecting the panel I/F board……………….……………………….……25

S5U13709 Evaluation Board User Manual

1 Introduction

This manual describes the setup and operation of the S5U13709P00C100 Rev.1.0 Evaluation

Board. This evaluation board is designed as an evaluation platform for the S1D13709 Embedded

Memory Graphics LCD Controller.

The S5U13709P00C100 Evaluation Board can be used with the USB Interface Board

(S5U13U00P00C100), thus providing an easy connection to Personal Computer with a USB

interface.

This user manual is updated as appropriate. Please check the Epson Electronics America

Website at vdc.epson.com for the latest revision of this document before beginning any

development.

We appreciate your comments on our documentation. Please contact us via email

at [email protected]son.com

4 EPSON S5U13709P00C100 Evaluation Board User Manual Rev. 1.00

S5U13709 Evaluation Board User Manual

2 Features

The S5U13709P00C100 Evaluation Board includes the following features:

•80-pin TQFP14 S1D13709 Embedded Memory Graphics LCD Controller

•2.0mm pitch 40pin connector (x2) for USB Interface Board. (S5U13U00P00C100)

•2.54mm pitch 34pin connector (x2) for connecting other host interface.

•2.54mm pitch 40pin connector (x2) for panel interface.

•Clock source can be selected from two types.

Use on-board 24MHz crystal oscillator or set crystal in the 14pin socket.

•SW1, SW2 are switches to change the configuration for the S1D13709.

•On-board voltage regulator (LM1117MPX-3.3) with 3.3V output for HIOVDD/NIOVDD.

•On-board white LED driver (TPS61161A) for the panel backlight power supply.

5 EPSON S5U13709P00C100 Evaluation Board User Manual Rev. 1.00

S5U13709 Evaluation Board User Manual

3 Installations and Configuration

3.1 Switches

The S5U13709P00C100 Evaluation Board incorporates DIP switches (SW1, SW2), which allow

configuration of the board. For switch locations on the evaluation board, see Figure 3-1:

“Configuration DIP Switches Location”.

Figure 3-1: Configuration DIP Switches (SW1), (SW2) Location

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S5U13709 Evaluation Board User Manual

The 12-position DIP switch (SW1) is used to configure the S1D13709 for different host bus

interfaces and for TFT panel or STN panel for TFT-LCD Automatic Setting Mode.

Table 3-1a: Summary of Configuration Options

S5U13709P00C100

SW1-[12:1]

Configuration

S1D13709

Configuration State

1 (ON) 0 (OFF)

SW1-[12]

TESTEN Not use Normal use “GND”

SW1-[11]

CNF10 CLKI (XCG1) frequency is 24MHz

This setting is available only when the TFT-LCD Automatic

Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)

CLKI (XCG1) frequency is 20MHz

SW1-[10]

CNF9 TFT Interface Output Drive is [email protected]

(8mA@5V)

This setting is available only when the TFT-LCD Automatic

Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)

TFT Interface Output Drive is [email protected]

(3mA@5V)

SW1-[9]

CNF8 All output video signals change at rising edge

of FPSHIFT

This setting is available only when the TFT-LCD Automatic

Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)

All output video signals change at the

falling edge of FPSHIFT

SW1-[8:6]

CNF[7:5]

CNF7 CNF6 CNF5 TFT-LCD Automatic Setting Mode

0 0 0 Disable (Manual setting)

0 0 1 S1D13700S/W:QVGA→TFT: QVGA

0 1 0 S1D13700S/W:QVGA→TFT: WQVGA

0 1 1 S1D13700S/W:QVGA→TFT: VGA

1 0 0 S1D13700S/W:QVGA→TFT: WVGA

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

When the STN interface is used (REG[34h] bit0 = 0), CNF[7:5]

should be 000.

TFT interface is used. (TFT-LCD Automatic

Setting Mode Disable)

Or STN interface is used. (REG[34h] bit0

= 0)

SW1-[5]

CNF4 Indirect Addressing Mode:

1-bit address bus, 8-bit data bus

9pin are used

Direct Addressing Mode:

16bit address bus, 8-bit data bus

24pin are used.

SW1-[4:3]

CNF[3:2]

Select the host bus interface as follows:

CNF3 CNF2 Host Bus

0 0 GenericBus

0 1 Reserved

1 0 M6800FamilyBusInterface

1 1 MC68KFamilyBusInterface

Select the host bus interface as “Generic

Bus”.

SW1-[2:1]

CNF[1:0]

Select the XSCL cycle time (XSCL:CLOCK

Input) as follows:

For 1bpp mode (REG[20h] bit 1-0 = 00)

CNF1 CNF0 XSCL Cycle Time

0 0 4:1

0 1 8:1

1 0 16:1

1 1 Reserved

For 2bpp mode (REG[20h] bit 1-0 = 01)

CNF1 CNF0 XSCL Cycle Time

0 0 8:1

0 1 16:1

1 0 32:1

1 1 Reserved

For 4bpp mode (REG[20h] bit 1-0 = 10)

CNF1 CNF0 XSCL Cycle Time

0 0 16:1

0 1 32:1

1 0 64:1

1 1 Reserved

When the TFT Interface is used (REG[34h] bit0 = 1), CNF[1:0]

should be 00.

For 1bpp mode (REG[20h] bit 1-0 = 00)

CNF1 CNF0 XSCL Cycle Time

0 0 4:1

For 2bpp mode (REG[20h] bit 1-0 = 01)

CNF1 CNF0 XSCL Cycle Time

0 0 8:1

For 4bpp mode (REG[20h] bit 1-0 = 10)

CNF1 CNF0 XSCL Cycle Time

0 0 16:1

=defaultsetting

7 EPSON S5U13709P00C100 Evaluation Board User Manual Rev. 1.00

S5U13709 Evaluation Board User Manual

The 2-position DIP switch (SW2) is used to configure for production test only. For normal use this

switch state should be set to "ON".

Table 3-1b: Summary of Configuration Options

S5U13709P00C100

SW2-[2:1]

Configuration

S1D13709

Pin Configuration State

1 (ON) 0 (OFF)

SW2-[1] CORECE Normal use Not use

SW2-[2] PLLCE Normal use Not use

=defaultsetting

3.2 Configuration Jumpers

The S5U13709P00C100 Evaluation Board includes the following 2-pin, 3-pin and 8-pin jumper

blocks which are used to control function and for power consumption measurement. For jumper

locations on the evaluation board, see Figure 3-2: “Configuration Jumper Location”

Figure 3-2: Configuration Jumper Location

8 EPSON S5U13709P00C100 Evaluation Board User Manual Rev. 1.00

S5U13709 Evaluation Board User Manual

Table 3-2a: 2-Pin Jumper Settings

Jumper Position1-2 No Jumper

JP1 COREVDD power supply COREVDD no power

Connect a current meter for power

measurement

JP3 PLLVDD power supply PLLVDD no power

Connect a current meter for power

measurement

JP5 HIOVDD power supply HIPVDD no power

Connect a current meter for power

measurement

JP6 NIOVDD power supply NIOVDD no power

Connect a current meter for power

measurement

JP11 Use OSC clock source Disable OSC clock source

=defaultsettings

Table 3-2b: 3-Pin Jumper Settings

Jumper Position1-2 Position2-3

JP2 Select power supply HIOVDD Select power supply NIOVDD

JP4 Select power supply HIOVDD Select power supply NIOVDD

JP7 Select clock source OSC1 Select clock source P1-4pin

(S5U13U00P00C100)

JP8 Select clock input OSCI Select clock input MCLK

JP9 Select HIOVDD Voltage 3.3V Select HIOVDD Voltage 5.0V

JP10 Select NIOVDD Voltage 3.3V Select NIOVDD Voltage 5.0V

JP12 Reset# pulse supply from SW3 Reset# pulse supply from P1-21pin,

H1-30pin

=defaultsetting

Table 3-2c: 8-Pin Jumper Settings

Jumper Position Function

Position1-2 No Jumper TPS61161A Enable

Position3-4 No Jumper Vout = 20mA

Position5-6 No Jumper Vout = 40mA ( and Position3-4)

Position7-8 No Jumper Vout = 60mA (And position3-4/5-6)

=defaultsetting

9 EPSON S5U13709P00C100 Evaluation Board User Manual Rev. 1.00

S5U13709 Evaluation Board User Manual

3.3 Power Requirement

3.3.1 HIOVDD, NIOVDD, COREVDD, PLLVDD

The S5U13709P00C100 Evaluation Board is designed to generate HIOVDD, NIOVDD,

COREVDD and PLLVDD from 5V via the S5U13U00P00C100 USB Interface Board. 5V must be

supplied from the S5U13U00P00C100. JP1 on the S5U13U00P00C100 USB Interface Board

should be set to position 2-3. 3.3V power supply is generated by one voltage regulator (U3) and

fixed output. HIOVDD and NIOVDD can be selected 3.3V or 5V using jumper JP9 and JP10.

COREVDD is possible to select HIOVDD, NIOVDD or LDOVDD0. PLLVDD are possible to select

HIOVDD, NIOVDD or LDOVDD1. If use the LDOVDD0 and LDOVDD1, it is external input from

JP1 and JP3. Refer to Table 3-2a and 3-2b on page 9.

3.3.2 Backlight Power Supply for LCD Panel

The S5U13709P00C100 Evaluation Board has an incorporated White LDE Driver Controller

(TPS61161A) for the panel backlight. White LED Driver Controller drives the panel at a constant

current. The S5U13709P00C100 Evaluation Board is possible to change the output current

(20mA, 40mA, 60mA/ Max 38V). Please set J1 with the specifications of the panel. Refer to

Table 3-2c on page 9.

10 EPSON S5U13709P00C100 Evaluation Board User Manual Rev. 1.00

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