Cypress 7C185-15 Manual de usuario

8K x 8 Static RAM

CY7C185

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-05043 Rev. *A Revised September 13, 2002

185

Features

• High speed

—15ns

•Fastt

DOE

• Low active power

—715 mW

• Low standby power

—220 mW

• CMOS for optimum speed/power

• Easymemoryexpansion withCE1,CE2,andOE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

Functional Description[1]

The CY7C185 is a high-performance CMOS static RAM orga-

nized as 8192 words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE1),an active HIGH

chip enable (CE2), and active LOW output enable (OE) and

three-state drivers. This device has an automatic power-down

feature(CE1orCE2),reducingthepowerconsumptionby70%

when deselected. The CY7C185 is in a standard 300-mil-wide

DIP, SOJ, or SOIC package.

An active LOW write enable signal (WE) controls the writ-

ing/reading operation of the memory. When CE1and WE in-

puts are both LOW and CE2is HIGH, data on the eight data

input/output pins (I/O0through I/O7) is written into the memory

location addressed by the address present on the address

pins (A0through A12). Reading the device is accomplished by

selecting the device and enabling the outputs, CE1and OE

active LOW, CE2active HIGH, while WE remains inactive or

HIGH. Under these conditions, the contents of the location ad-

dressed by the information on address pins are present on the

eight data input/output pins.

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable

(WE) is HIGH. A die coat is used to insure alpha immunity.

Logic Block Diagram Pin Configurations

A10

A11

A12

I/O0

VCC

CE2

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

A10

A11

A12

I/O0

I/O1

I/O2

GND

256 x 32 x 8

ARRAY

INPUT BUFFER

COLUMN DECODER

ROW DECODER

SENSE AMPS

POWER

DOWN

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

CE1

CE2

Top View

DIP/SOJ/SOIC

Selection Guide[2]

7C185-15 7C185-20 7C185-25 7C185-35

Maximum Access Time (ns) 15 20 25 35

Maximum Operating Current (mA) 130 110 100 100

Maximum Standby Current (mA) 40/15 20/15 20/15 20/15

Note:

1. ForguidelinesonSRAMsystemdesign,pleasereferto the‘SystemDesignGuidelines’Cypressapplicationnote,availableonthe internetatwww.cypress.com.

2. For military specifications, see the CY7C185A data sheet.

CY7C185

Document #: 38-05043 Rev. *A Page 2 of 11

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State[3] ............................................ –0.5V to +7.0V

DC Input Voltage[3].........................................–0.5V to +7.0V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.................................................... >200 mA

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ±10%

Industrial –40°C to +85°C 5V ±10%

Electrical Characteristics Over the Operating Range

7C185-15 7C185-20

Parameter Description Test Conditions Min. Max. Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC +

0.3V 2.2 VCC +

0.3V V

VIL Input LOW Voltage[3] –0.5 0.8 –0.5 0.8 V

IIX Input Load Current GND ≤VI≤VCC –5+5 –5+5 µA

IOZ Output Leakage

Current GND ≤VI ≤VCC,

Output Disabled –5+5 –5+5 µA

IOS Output Short

Circuit Current[4] VCC = Max.,

VOUT = GND –300 –300 mA

ICC VCC Operating

Supply Current VCC = Max.,

IOUT = 0 mA 130 110 mA

ISB1 Automatic

Power-Down Current Max. VCC, CE1≥VIH or CE2 ≤VIL

Min. Duty Cycle = 100% 40 20 mA

ISB2 Automatic

Power-Down Current Max. VCC, CE1≥VCC –0.3V,

or CE2 ≤0.3V

VIN ≥VCC –0.3V or VIN ≤0.3V

15 15 mA

Notes:

3. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.

4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

CY7C185

Document #: 38-05043 Rev. *A Page 3 of 11

Electrical Characteristics Over the Operating Range (continued)

7C185-25 7C185-35

Parameter Description Test Conditions Min. Max. Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC +

0.3V 2.2 VCC +

0.3V V

VIL Input LOW Voltage[3] –0.5 0.8 –0.5 0.8 V

IIX Input Load Current GND ≤VI≤VCC –5+5 –5+5 µA

IOZ Output Leakage

Current GND ≤VI ≤VCC,

Output Disabled –5+5 –5+5 µA

IOS Output Short

Circuit Current[4] VCC = Max.,

VOUT = GND –300 –300 mA

ICC VCC Operating

Supply Current VCC = Max.,

IOUT = 0 mA 100 100 mA

ISB1 Automatic

Power-Down Current Max. VCC, CE1≥VIH or CE2 ≤VIL

Min. Duty Cycle = 100% 20 20 mA

ISB2 Automatic

Power-Down Current Max. VCC, CE1≥VCC –0.3V

or CE2 ≤0.3V

VIN ≥VCC –0.3V or VIN ≤0.3V

15 15 mA

Capacitance[5]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = 5.0V 7pF

COUT Output Capacitance 7pF

Note:

5. Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

R1 481Ω

3.0V

OUTPUT

R1 481Ω

255Ω

30 pF GND

90% 90%

10%

≤5ns ≤5ns

OUTPUT

255Ω

5pF

(a) (b)

OUTPUT 1.73V

INCLUDING

JIG AND

SCOPE

INCLUDING

JIGAND

SCOPE

10%

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

167Ω

CY7C185

Document #: 38-05043 Rev. *A Page 4 of 11

Switching Characteristics Over the Operating Range[6]

7C185-15 7C185-20 7C185-25 7C185-35

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

tRC Read Cycle Time 15 20 25 35 ns

tAA Address to Data Valid 15 20 25 35 ns

tOHA Data Hold from Address Change 3 5 5 5 ns

tACE1 CE1LOW to Data Valid 15 20 25 35 ns

tACE2 CE2HIGH to Data Valid 15 20 25 35 ns

tDOE OE LOW to Data Valid 8 9 12 15 ns

tLZOE OE LOW to Low Z 3 3 3 3 ns

tHZOE OE HIGH to High Z[7] 7 8 10 10 ns

tLZCE1 CE1LOW to Low Z[8] 3 5 5 5 ns

tLZCE2 CE2HIGH to Low Z 3 3 3 3 ns

tHZCE CE1HIGH to High Z[7, 8]

CE2LOW to High Z 7 8 10 10 ns

tPU CE1LOW to Power-Up

CE2to HIGH to Power-Up 0 0 0 0 ns

tPD CE1HIGH to Power-Down

CE2 LOW to Power-Down 15 20 20 20 ns

Write Cycle[9]

tWC Write Cycle Time 15 20 25 35 ns

tSCE1 CE1LOW to Write End 12 15 20 20 ns

tSCE2 CE2HIGH to Write End 12 15 20 20 ns

tAW Address Set-up to Write End 12 15 20 25 ns

tHA Address Hold from Write End 0 0 0 0 ns

tSA Address Set-up to Write Start 0 0 0 0 ns

tPWE WE Pulse Width 12 15 15 20 ns

tSD Data Set-up to Write End 810 10 12 ns

tHD Data Hold from Write End 0 0 0 0 ns

tHZWE WE LOW to High Z[7] 7 7 7 8 ns

tLZWE WE HIGH to Low Z 3 5 5 5 ns

Notes:

6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

IOL/IOH and 30-pF load capacitance.

7. tHZOE, tHZCE, and tHZWE are specified with CL= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.

8. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.

9. The internal write time of the memory is defined by the overlap of CE1LOW, CE2HIGH, and WE LOW. All 3 signals must be active to initiate a write and either

signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of thesignalthatterminatesthewrite.

CY7C185

Document #: 38-05043 Rev. *A Page 5 of 11

Switching Waveforms

10. Device is continuously selected. OE, CE1= VIL. CE2= VIH.

11. WE is HIGH for read cycle.

12. Data I/O is High Z if OE = VIH, CE1= VIH, WE = VIL,or CE2=VIL.

13. The internal write time of the memory is defined by the overlap of CE1LOW, CE2HIGH and WE LOW. CE1and WE must be LOW and CE2must be HIGH

to initiate write. A write can be terminated by CE1or WE going HIGH or CE2going LOW. The data input set-up and hold timing should be referenced to the

rising edge of the signal that terminates the write.

14. During this period, the I/Os are in the output state and input signals should not be applied.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

Read Cycle No.1[10,11]

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE IMPEDANCE

ICC

ISB

tHZOE tHZCE

tPD

HIGH

DATA OUT

VCC

SUPPLY

CURRENT

CE1

CE2

Read Cycle No.2[12,13]

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

tHZOE

DATA IN VALID

CE1

CE2

DATA I/O

tSCEI

tSCE2

ADDRESS

NOTE 14

[11,13]

Write Cycle No. 1 (WE Controlled)

CY7C185

Document #: 38-05043 Rev. *A Page 6 of 11

Notes:

15. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

16. If CE1goes HIGH or CE2goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.

Switching Waveforms (continued)

tWC

tAW

tSA

tHA

tHD

tSD

tSCE1

DATA I/O

ADDRESS

CE1

DATA IN VALID

tSCE2

CE2

rite Cycle No. 2 (CE Controlled)[13,14,15]

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE

DATA IN VALID

tSCE1

tSCE2

CE1

CE2

ADDRESS

DATA I/O

Write Cycle No. 3 (WE Controlled, OE LOW)[13,14,15,16]

NOTE 14

CY7C185

Document #: 38-05043 Rev. *A Page 7 of 11

Typical DC and AC Characteristics

–55 25 125

1.2

1.0

0.8

OUTPUT SOURCE CURRENT (mA)

AMBIENT TEMPERATURE (°C)

0.6

0.4

0.2

0.0

NORMALIZED I, I

ISB

VCC=5.0V

VIN=5.0V

ICC

1.2

1.4

1.0

0.6

0.4

0.2

4.0 4.5 5.0 5.5 6.0

1.6

1.4

1.2

1.0

0.8

–55 25 125

NORMALIZED tAA

120

100

0.0 1.0 2.0 3.0 4.0

SUPPLY VOLTAGE (V)

NORMALIZED SUPPLY CURRENT

vs. SUPPLY VOLTAGE

NORMALIZED ACCESS TIME

vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE

0.0

0.8

1.4

1.3

1.2

1.1

1.0

0.9

4.0 4.5 5.0 5.5 6.0

NORMALIZED tAA

SUPPLY VOLTAGE (V)

NORMALIZED ACCESS TIME

vs. SUPPLY VOLTAGE

120

140

100

0.0 1.0 2.0 3.0 4.0

OUTPUT SINK CURRENT (mA)

OUTPUT VOLTAGE (V)

OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE

NORMALIZED I, I

CC SB

ICC

VCC =5.0V

TA=25°C

VCC =5.0V

TA=25°C

ISB

TA=25°C

0.6

0.8

3.0

2.5

2.0

1.5

1.0

0.5

0.0 1.0 2.0 3.0 4.0

NORMALIZED IPO

SUPPLY VOLTAGE (V)

TYPICAL POWER-ON CURRENT

vs. SUPPLY VOLTAGE 30.0

25.0

20.0

15.0

10.0

5.0

0 200 400 600 800

DELTA t (ns)

CAPACITANCE (pF)

TYPICAL ACCESS TIME CHANGE

vs. OUTPUT LOADING 1.25

1.00

0.75

10 20 30 40

NORMALIZED ICC

CYCLE FREQUENCY (MHz)

NORMALIZED ICC vs. CYCLE TIME

0.0 5.0 0.0 1000 0.50

VCC =4.5V

TA=25°C

VCC =5.0V

TA=25°C

VCC =0.5V

CY7C185

Document #: 38-05043 Rev. *A Page 8 of 11

Truth Table

CE1CE2WE OE Input/Output Mode

H X X X High Z Deselect/Power-Down

X L X X High Z Deselect/Power-Down

L H H L Data Out Read

L H L X Data In Write

L H H H High Z Deselect

Address Designators

Address

Name Address

Function Pin

Number

A4 X3 2

A5 X4 3

A6 X5 4

A7 X6 5

A8 X7 6

A9 Y1 7

A10 Y4 8

A11 Y3 9

A12 Y0 10

A0 Y2 21

A1 X0 23

A2 X1 24

A3 X2 25

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

15 CY7C185-15PC P21 28-Lead (300-Mil) Molded DIP Commercial

CY7C185-15SC S21 28-Lead Molded SOIC

CY7C185-15VC V21 28-Lead Molded SOJ

CY7C185-15VI V21 28-Lead Molded SOJ Industrial

20 CY7C185-20PC P21 28-Lead (300-Mil) Molded DIP Commercial

CY7C185-20SC S21 28-Lead Molded SOIC

CY7C185-20VC V21 28-Lead Molded SOJ

CY7C185-20VI V21 28-Lead Molded SOJ Industrial

25 CY7C185-25PC P21 28-Lead (300-Mil) Molded DIP Commercial

CY7C185-25SC S21 28-Lead Molded SOIC

CY7C185-25VC V21 28-Lead Molded SOJ

CY7C185-25VI V21 28-Lead Molded SOJ Industrial

35 CY7C185-35PC P21 28-Lead (300-Mil) Molded DIP Commercial

CY7C185-35SC S21 28-Lead Molded SOIC

CY7C185-35VC V21 28-Lead Molded SOJ

CY7C185-35VI V21 28-Lead Molded SOJ Industrial

CY7C185

Document #: 38-05043 Rev. *A Page 9 of 11

Package Diagrams

51-85014-*B

28-Lead (300-Mil) Molded DIP P21

28-Lead (300-Mil) Molded SOIC S21

51-85026-*A

CY7C185

Document #: 38-05043 Rev. *A Page 10 of 11

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nordoes it conveyor imply any license underpatent orother rights.Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

All product and company names mentioned in this document may be the trademarks of their respective holders.

Package Diagrams (continued)

28-Lead (300-Mil) Molded SOJ V21

51-85031-*B

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