Cypress Semiconductor CY7C68013A Manual de usuario

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

EZ-USB FX2LP™ USB Microcontroller

High-Speed USB Peripheral Controller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 •408-943-2600

Document #: 38-08032 Rev. *L Revised February 8, 2008

1. Features (CY7C68013A/14A/15A/16A)

■USB 2.0 USB IF high-speed certified (TID # 40460272)

■Single chip integrated USB 2.0 transceiver, smart SIE, and

enhanced 8051 microprocessor

■Fit, form and function compatible with the FX2

❐Pin compatible

❐Object-code-compatible

❐Functionally compatible (FX2LP is a superset)

■Ultra Low power: ICC no more than 85 mA in any mode

❐Ideal for bus and battery powered applications

■Software: 8051 code runs from:

❐Internal RAM, which is downloaded via USB

❐Internal RAM, which is loaded from EEPROM

❐External memory device (128 pin package)

■16 KBytes of on-chip Code/Data RAM

■Four programmable BULK/INTERRUPT/ISOCHRONOUS

endpoints

❐Buffering options: double, triple, and quad

■Additional programmable (BULK/INTERRUPT) 64 byte

endpoint

■8-bit or 16-bit external data interface

■Smart Media Standard ECC generation

■GPIF (General Programmable Interface)

❐Enables direct connection to most parallel interfaces

❐Programmable waveform descriptors and configuration reg-

isters to define waveforms

❐SupportsmultipleReady(RDY)inputsandControl(CTL)out-

puts

■Integrated, industry standard enhanced 8051

❐48 MHz, 24 MHz, or 12 MHz CPU operation

❐Four clocks per instruction cycle

❐Two USARTS

❐Three counter/timers

❐Expanded interrupt system

❐Two data pointers

■3.3V operation with 5V tolerant inputs

■Vectored USB interrupts and GPIF/FIFO interrupts

■Separate data buffers for the Setup and Data portions of a

CONTROL transfer

■Integrated I2C controller, runs at 100 or 400 kHz

■Four integrated FIFOs

❐Integrated glue logic and FIFOs lower system cost

❐Automatic conversion to and from 16-bit buses

❐Master or slave operation

❐Uses external clock or asynchronous strobes

❐Easy interface to ASIC and DSP ICs

■Available in Commercial and Industrial temperature grade (all

packages except VFBGA)

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1.1 Features (CY7C68013A/14A only)

■CY7C68014A: Ideal for battery powered applications

❐Suspend current: 100 μA (typ)

■CY7C68013A: Ideal for non-battery powered applications

❐Suspend current: 300 μA (typ)

■Available in five lead-free packages with up to 40 GPIOs

❐128-pinTQFP(40GPIOs),100-pinTQFP(40GPIOs),56-pin

QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VF-

BGA (24 GPIOs)

1.2 Features (CY7C68015A/16A only)

■CY7C68016A: Ideal for battery powered applications

❐Suspend current: 100 μA (typ)

■CY7C68015A: Ideal for non-battery powered applications

❐Suspend current: 300 μA (typ)

■Available in lead-free 56-pin QFN package (26 GPIOs)

❐2 more GPIOs than CY7C68013A/14A enabling additional

features in same footprint

Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB

FX2LP™(CY7C68013A/14A) is a low power version of the

EZ-USB FX2™ (CY7C68013), which is a highly integrated, low

powerUSB2.0 microcontroller.ByintegratingtheUSB2.0 trans-

ceiver, serial interface engine (SIE), enhanced 8051 microcon-

troller, and a programmable peripheral interface in a single chip,

Cypress has created a cost effective solution that provides

superior time-to-market advantages with low power to enable

bus powered applications.

The ingenious architecture of FX2LP results in data transfer

rates of over 53 Mbytes per second, the maximum allowable

USB 2.0 bandwidth, while still using a low cost 8051 microcon-

troller in a package as small as a 56 VFBGA (5mm x 5mm).

Because it incorporates the USB 2.0 transceiver, the FX2LP is

more economical, providing a smaller footprint solution than

USB 2.0 SIE or external transceiver implementations. With

EZ-USB FX2LP, the Cypress Smart SIE handles most of the

USB 1.1 and 2.0 protocol in hardware, freeing the embedded

microcontroller for application specific functions and decreasing

development time to ensure USB compatibility.

The General Programmable Interface (GPIF) and Master/Slave

Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and

glueless interface to popular interfaces such as ATA, UTOPIA,

EPP, PCMCIA, and most DSP/processors.

The FX2LP draws less current than the FX2 (CY7C68013), has

double the on-chip code/data RAM, and is fit, form and function

compatible with the 56, 100, and 128 pin FX2.

Five packages are defined for the family: 56VFBGA, 56 SSOP,

56 QFN, 100 TQFP, and 128 TQFP.

Address (16)

x20

PLL

/0.5

/1.0

/2.0

8051 Core

12/24/48 MHz,

four clocks/cycle

VCC

1.5k

D+

D–

Address (16) / Data Bus (8)

FX2LP

GPIF

Smart

USB

1.1/2.0

Engine

USB

2.0

XCVR

16 KB

RAM

4 kB

FIFO

Integrated

full-speed and

Additional IOs (24)

ADDR (9)

CTL (6)

RDY (6)

8/16

Data (8)

24 MHz

Ext. XTAL

Enhanced USB core

Simplifies 8051 code “Soft Configuration”

Easy firmware changes FIFO and endpoint memory

(master or slave operation)

Up to 96 MBytes/s

burst rate

General

programmable I/F

to ASIC/DSP or bus

standards such as

ATAPI, EPP, etc.

Abundant IO

including two USARTS

High performance micro

using standard tools

with lower-power options

Master

connected for

full-speed

ECC

XCVR

high-speed

Logic Block DiagramLogic Block Diagram

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2. Applications

■Portable video recorder

■MPEG/TV conversion

■DSL modems

■ATA interface

■Memory card readers

■Legacy conversion devices

■Cameras

■Scanners

■Home PNA

■Wireless LAN

■MP3 players

■Networking

The “Reference Designs” section of the Cypress web site

provides additional tools for typical USB 2.0 applications. Each

reference design comes complete with firmware source and

object code, schematics, and documentation. Visit the Cypress

web site for more information.

3. Functional Overview

3.1 USB Signaling Speed

FX2LP operates at two of the three rates defined in the USB

Specification Revision 2.0, dated April 27, 2000:

■Full-speed, with a signaling bit rate of 12 Mbps

■High-speed, with a signaling bit rate of 480 Mbps.

FX2LP does not support the low speed signaling mode of

1.5 Mbps.

3.2 8051 Microprocessor

The 8051 microprocessor embedded in the FX2LP family has

256 bytes of register RAM, an expanded interrupt system, three

timer/counters, and two USARTs.

3.2.1 8051 Clock Frequency

FX2LP has an on-chip oscillator circuit that uses an external 24

MHz (±100 ppm) crystal with the following characteristics:

■Parallel resonant

■Fundamental mode

■500-μW drive level

■12-pF (5% tolerance) load capacitors

An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,

as required by the transceiver/PHY and internal counters divide

it down for use as the 8051 clock. The default 8051 clock

frequency is 12 MHz. The clock frequency of the 8051 can be

changed by the 8051 through the CPUCS register, dynamically.

The CLKOUT pin, which can be three-stated and inverted using

internal control bits, outputs the 50% duty cycle 8051 clock, at

the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.

3.2.2 USARTS

FX2LP contains two standard 8051 USARTs, addressed via

Special Function Register (SFR) bits. The USART interface pins

are available on separate IO pins, and are not multiplexed with

port pins.

UART0 and UART1 can operate using an internal clock at

230 KBaud with no more than 1% baud rate error. 230 KBaud

operation is achieved by an internally derived clock source that

generates overflow pulses at the appropriate time. The internal

clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and 12

MHz) such that it always presents the correct frequency for 230

KBaud operation.[1]

3.2.3 Special Function Registers

Certain 8051 SFR addresses are populated to provide fast

access to critical FX2LP functions. These SFR additions are

shown in Table 1 on page 4. Bold type indicates non standard,

enhanced 8051 registers. The two SFR rows that end with “0”

and “8” contain bit addressable registers. The four IO ports A to

D use the SFR addresses used in the standard 8051 for ports 0

to 3, which are not implemented in FX2LP. Because of the faster

and more efficient SFR addressing, the FX2LP IO ports are not

addressable in external RAM space (using the MOVX

instruction).

3.3 I2C Bus

FX2LP supports the I2C bus as a master only at 100-/400- KHz.

SCL and SDA pins have open-drain outputs and hysteresis

inputs. These signals must be pulled up to 3.3V, even if no I2C

device is connected.

3.4 Buses

All packages, 8-bit or 16-bit “FIFO” bidirectional data bus, multi-

plexed on IO ports B and D. 128-pin package: adds 16-bit

output-only 8051 address bus, 8-bit bidirectional data bus.

Figure 1. Crystal Configuration

12 pf

24 MHz

20 × PLL

C1 C2

12-pF capacitor values assumes a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

Note

1. 115 KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.

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3.5 USB Boot Methods

During the power up sequence, internal logic checks the I2C port

for the connection of an EEPROM whose first byte is either 0xC0

or0xC2. Iffound, it usesthe VID/PID/DIDvaluesin theEEPROM

in place of the internally stored values(0xC0),or it boot-loads the

EEPROM contents into internal RAM (0xC2). If no EEPROM is

detected, FX2LP enumerates using internallystored descriptors.

The default ID values for FX2LP are VID/PID/DID (0x04B4,

0x8613, 0xAxxx where xxx = Chip revision).[2]

3.6 ReNumeration™

Because the FX2LP’s configuration is soft, one chip can take on

the identities of multiple distinct USB devices.

When first plugged into USB, the FX2LP enumerates automati-

cally and downloads firmware and USB descriptor tables over

the USB cable. Next, the FX2LP enumerates again, this time as

a device defined by the downloaded information. This patented

twostep process calledReNumeration™happens instantlywhen

the device is plugged in, without a hint that the initial download

step has occurred.

Two control bits in the USBCS (USB Control and Status) register,

control the ReNumeration process: DISCON and RENUM. To

simulate a USB disconnect, the firmware sets DISCON to 1. To

reconnect, the firmware clears DISCON to 0.

Before reconnecting, the firmware sets or clears the RENUM bit

to indicate whether the firmware or the Default USB Device

handles device requests over endpoint zero: if RENUM = 0, the

Default USB Device handles device requests; if RENUM = 1, the

firmware services the requests.

3.7 Bus-powered Applications

The FX2LP fully supports bus powered designs by enumerating

with less than 100 mA as required by the USB 2.0 specification.

3.8 Interrupt System

3.8.1 INT2 Interrupt Request and Enable Registers

FX2LP implements an autovector feature for INT2 and INT4.

There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)

vectors. See EZ-USB Technical Reference Manual (TRM) for

more details.

3.8.2 USB Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To

save the code and processing time that is required to identify the

individual USB interrupt source, the FX2LP provides a second

level of interrupt vectoring, called Autovectoring. When a USB

interrupt is asserted, the FX2LP pushes the program counter

onto its stack then jumps to the address 0x0043 where it expects

to find a “jump” instruction to the USB Interrupt service routine.

Table 1. Special Function Registers

x8x 9x Ax Bx Cx Dx Ex Fx

0IOA IOB IOC IOD SCON1 PSW ACC B

1SP EXIF INT2CLR IOE SBUF1

2DPL0 MPAGE INT4CLR OEA

3DPH0 OEB

4DPL1 OEC

5DPH1 OED

6DPS OEE

7PCON

8 TCON SCON0 IE IP T2CON EICON EIE EIP

9 TMOD SBUF0

ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L

BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H

CTH0reserved EP68FIFOFLGS TL2

DTH1AUTOPTRH2 GPIFSGLDATH TH2

ECKCON AUTOPTRL2 GPIFSGLDATLX

Freserved AUTOPTRSET-UP GPIFSGLDATLNOX

Table 2. Default ID Values for FX2LP

Default VID/PID/DID

Vendor ID 0x04B4 Cypress Semiconductor

Product ID 0x8613 EZ-USB FX2LP

Device release 0xAnnn Depends on chip revision

(nnn = chip revision where first

silicon = 001)

Note

2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.

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The FX2LP jump instruction is encoded as follows:

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP

the high byte (“page”) of a jump-table address is preloaded at the

location 0x0044, the automatically inserted INT2VEC byte at

0x0045 directs the jump to the correct address out of the 27

addresses within the page.

3.8.3 FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual USB

interrupt sources, the FIFO/GPIF interrupt is shared among 14

individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the

USB Interrupt, can employ autovectoring. Table 4 shows the

priority and INT4VEC values for the 14 FIFO/GPIF interrupt

sources.

Table 3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Priority INT2VEC Value Source Notes

1 00 SUDAV Setup Data Available

2 04 SOF Start of Frame (or microframe)

3 08 SUTOK Setup Token Received

4 0C SUSPEND USB Suspend request

5 10 USB RESET Bus reset

6 14 HISPEED Entered high-speed operation

7 18 EP0ACK FX2LP ACK’d the CONTROL Handshake

8 1C reserved

9 20 EP0-IN EP0-IN ready to be loaded with data

10 24 EP0-OUT EP0-OUT has USB data

11 28 EP1-IN EP1-IN ready to be loaded with data

12 2C EP1-OUT EP1-OUT has USB data

13 30 EP2 IN: buffer available. OUT: buffer has data

14 34 EP4 IN: buffer available. OUT: buffer has data

15 38 EP6 IN: buffer available. OUT: buffer has data

16 3C EP8 IN: buffer available. OUT: buffer has data

17 40 IBN IN-Bulk-NAK (any IN endpoint)

18 44 reserved

19 48 EP0PING EP0 OUT was Pinged and it NAK’d

20 4C EP1PING EP1 OUT was Pinged and it NAK’d

21 50 EP2PING EP2 OUT was Pinged and it NAK’d

22 54 EP4PING EP4 OUT was Pinged and it NAK’d

23 58 EP6PING EP6 OUT was Pinged and it NAK’d

24 5C EP8PING EP8 OUT was Pinged and it NAK’d

25 60 ERRLIMIT Bus errors exceeded the programmed limit

26 64

27 68 reserved

28 6C reserved

29 70 EP2ISOERR ISO EP2 OUT PID sequence error

30 74 EP4ISOERR ISO EP4 OUT PID sequence error

31 78 EP6ISOERR ISO EP6 OUT PID sequence error

32 7C EP8ISOERR ISO EP8 OUT PID sequence error

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If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP

the high byte (“page”) of a jump-table address is preloaded at

location 0x0054, the automatically inserted INT4VEC byte at

0x0055 directs the jump to the correct address out of the 14

addresses within the page. When the ISR occurs, the FX2LP

pushes the program counter onto its stack then jumps to address

0x0053, where it expects to find a “jump” instruction to the ISR

Interrupt service routine.

3.9 Reset and Wakeup

3.9.1 Reset Pin

The input pin, RESET#, resets the FX2LP when asserted. This

pinhas hysteresis andisactiveLOW. Whena crystalis usedwith

the CY7C680xxA the reset period must allow for the stabilization

of the crystal and the PLL. This reset period must be approxi-

mately 5 ms after VCC reaches 3.0V. If the crystal input pin is

driven by a clock signal the internal PLL stabilizes in 200 μs after

VCC has reached 3.0V.[3]

Figure 2 on page 7 shows a power on reset condition and a reset

applied during operation. A power on reset is defined as the time

reset that is asserted while power is being applied to the circuit.

A powered reset is when the FX2LP powered on and operating

and the RESET# pin is asserted.

Cypress provides an application note which describes and

recommends power on reset implementation. For more infor-

mation about reset implementation for the FX2 family of products

visit http://www.cypress.com.

Table 4. Individual FIFO/GPIF Interrupt Sources

Priority INT4VEC Value Source Notes

1 80 EP2PF Endpoint 2 Programmable Flag

2 84 EP4PF Endpoint 4 Programmable Flag

3 88 EP6PF Endpoint 6 Programmable Flag

4 8C EP8PF Endpoint 8 Programmable Flag

5 90 EP2EF Endpoint 2 Empty Flag

6 94 EP4EF Endpoint 4 Empty Flag

7 98 EP6EF Endpoint 6 Empty Flag

8 9C EP8EF Endpoint 8 Empty Flag

9 A0 EP2FF Endpoint 2 Full Flag

10 A4 EP4FF Endpoint 4 Full Flag

11 A8 EP6FF Endpoint 6 Full Flag

12 AC EP8FF Endpoint 8 Full Flag

13 B0 GPIFDONE GPIF Operation Complete

14 B4 GPIFWF GPIF Waveform

Note

3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 μs.

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3.9.2 Wakeup Pins

The 8051 puts itself and the rest of the chip into a power down

mode by setting PCON.0 = 1. This stops the oscillator and PLL.

When WAKEUP is asserted by external logic the oscillator

restarts after the PLL stabilizes, and the 8051 receives a wakeup

interrupt. This applies whether or not FX2LP is connected to the

USB.

TheFX2LPexitsthe power down (USBsuspend)stateusingone

of the following methods:

■USB bus activity (if D+/D– lines are left floating, noise on these

lines may indicate activity to the FX2LP and initiate a wakeup)

■External logic asserts the WAKEUP pin

■External logic asserts the PA3/WU2 pin

The second wakeup pin, WU2, can also be configured as a

general purpose IO pin. This enables a simple external R-C

network to be used as a periodic wakeup source. WAKEUP is by

default active LOW.

3.10 Program/Data RAM

3.10.1 Size

The FX2LP has 16 KBytes of internal program/data RAM, where

PSEN#/RD# signals are internally ORed to enable the 8051 to

access it as both program and data memory. No USB control

registers appear in this space.

Two memory maps are shown in the following diagrams:

Figure 3 on page 8 shows the Internal Code Memory, EA = 0

Figure 4 on page 9 shows the External Code Memory, EA = 1.

3.10.2 Internal Code Memory, EA = 0

This mode implements the internal 16 KByte block of RAM

(starting at 0) as combined code and data memory. When

external RAM or ROM is added, the external read and write

strobes are suppressed for memory spaces that exist inside the

chip. This enables the user to connect a 64 KByte memory

without requiring address decodes to keep clear of internal

memory spaces.

Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM

spaces have the following access:

■USB download

■USB upload

■Setup data pointer

■I2C interface boot load.

3.10.3 External Code Memory, EA = 1

The bottom 16 KBytes of program memory is external and

therefore the bottom 16 KBytes of internal RAM is accessible

only as a data memory.

Figure 2. Reset Timing Plots

VIL

3.3V

3.0V

TRESET

VCC

RESET#

Power on Reset

TRESET

VCC

RESET# VIL

Powered Reset

3.3V

Table 5. Reset Timing Values

Condition TRESET

Power on Reset with Crystal 5 ms

Power on Reset with External

Clock 200 μs + Clock stability time

Powered Reset 200 μs

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Figure 3. Internal Code Memory, EA = 0

Inside FX2LP Outside FX2LP

7.5 KBytes

USB regs and

4K FIFO buffers

(RD#,WR#)

0.5 KBytes RAM

Data (RD#,WR#)*

(OK to populate

data memory

here—RD#/WR#

strobes are not

active)

40 KBytes

External

Data

Memory

(RD#,WR#)

(Ok to populate

data memory

here—RD#/WR#

strobes are not

active)

16 KBytes RAM

Code and Data

(PSEN#,RD#,WR#)*

48 KBytes

External

Code

Memory

(PSEN#)

(OK to populate

program

memory here—

PSEN# strobe

is not active)

*SUDPTR, USB upload/download, I2C interface boot access

FFFF

E200

E1FF

E000

3FFF

0000 Data Code

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Figure 4. External Code Memory, EA = 1

3.11 Register Addresses

Inside FX2LP Outside FX2LP

7.5 KBytes

USB regs and

4K FIFO buffers

(RD#,WR#)

0.5 KBytes RAM

Data (RD#,WR#)*

(OK to populate

data memory

here—RD#/WR#

strobes are not

active)

40 KBytes

External

Data

Memory

(RD#,WR#)

(Ok to populate

data memory

here—RD#/WR#

strobes are not

active)

16 KBytes

RAM

Data

(RD#,WR#)*

64 KBytes

External

Code

Memory

(PSEN#)

*SUDPTR, USB upload/download, I2C interface boot access

FFFF

E200

E1FF

E000

3FFF

0000 Data Code

FFFF

E800

E7BF

E740

E73F

E700

E6FF

E500

E4FF

E480

E47F

E400

E200

E1FF

E000

E3FF

EFFF 2 KBytes RESERVED

64 Bytes EP0 IN/OUT

64 Bytes RESERVED

8051 Addressable Registers

Reserved (128)

128 bytes GPIF Waveforms

512 bytes

8051 xdata RAM

F000

(512)

Reserved (512)

E780 64 Bytes EP1OUT

E77F

64 Bytes EP1IN

E7FF

E7C0

4 KBytes EP2-EP8

buffers

(8 x 512)

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3.12 Endpoint RAM

3.12.1 Size

■3× 64 bytes (Endpoints 0 and 1)

■8 × 512 bytes (Endpoints 2, 4, 6, 8)

3.12.2 Organization

■EP0

■Bidirectional endpoint zero, 64 byte buffer

■EP1IN, EP1OUT

■64 byte buffers, bulk or interrupt

■EP2, 4, 6, 8

■Eight512bytebuffers,bulk,interrupt,orisochronous.EP4and

EP8 can be double buffered; EP2 and 6 can be either double,

triple, or quad buffered. For high-speed endpoint configuration

options, see Figure 5.

3.12.3 Setup Data Buffer

A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data

from a CONTROL transfer.

3.12.4 Endpoint Configurations (High -speed Mode)

Endpoints0 and 1arethe same for everyconfiguration.Endpoint

0 is the only CONTROL endpoint, and endpoint 1 can be either

BULK or INTERRUPT.

The endpoint buffers can be configured in any 1 of the 12 config-

urations shown in the vertical columns. When operating in the

full-speed BULK mode only the first 64 bytes of each buffer are

used. For example, in high-speed, the max packet size is 512

bytes but in full-speed it is 64 bytes. Even though a buffer is

configured to a 512 byte buffer, in full-speed only the first 64

bytes are used. The unused endpoint buffer space is not

available for other operations. An example endpoint configu-

ration is the EP2–1024 double buffered; EP6–512 quad buffered

(column 8).

Figure 5. Endpoint Configuration

512

1024

512

EP2 EP2 EP2

EP6

EP8 EP8

EP0 IN&OUT

EP1 IN

EP1 OUT

1024

EP6 1024

512

EP8

512

EP6

512

EP2

512

EP4

512

EP2

512

EP4

512

EP2

512

EP4

512

EP2

512

EP2

512

EP2

512

1024

EP2

1024

EP2

1024

EP2

1024

512

EP6

1024

EP6

512

EP8

512

EP6

512

EP6

1024

EP6

512

EP8

512

EP6

512

12345678910 11 12

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