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Cromemco BlART Communication Processor Instruction Manual
Introduction
INTRODUCTION
This manual provides installation, operating, and programming instructions for
Cromemco's BIART communications processor board. The BIART board is a
second generation, co-processing subsystem which interfaces two serial
channels and a bi-directional parallel port to a host S-100/IEEE-696 bus. A
typical BlART application might consist of interfacing two computer terminals
or modems and a Centronics-compatible parallel printer to the host system.
Unlike earlier serial interface boards, which merely formatted and exchanged
individual data characters, the BlART features a sophisticated dual channel
Z-SCC serial communications circuit, plus an independent Z80B processor with
6"4 'Xbytes of memory. Because the BIART performs all protocol and error
detection/recovery functions, buffers large amounts of serial data, and passes
only pre-processed data over the host bus, the host CPU is relieved of many
I/O functions, and system throughput is dramatically increased.
The BIART is a versatile serial subsystem, compatible with both Z80 Cromix
version 11.27 and higher, and 68000 Cromix version 20.63 and higher. Under
program control, it can switch its internal memory configuration from 16 Kbytes
of ROMand 32 Kbytes of RAMto a full 64 Kbytes of RAM. Thus the board can
include a ROMbootstrap program which loads an application program, and then
switches to 64 Kbytes of RAM for maximum buffer space. The two serial
channel scan 0perate independently of one another in asy nc hron ou s,
byte-synchronous (IBM BiSync), or bit-synChronous (SDLC/HDLC) mode, and
each channel can encode and decode NRZ, NRZI, FMO, or FlVIl data.
Chapter 1 describes how to install the BIART board in an S-100 bus system.
Chapter topics include cables, switch settings, and connector pin assignments.
Chapter 2 presents BIART programming information. This chapter assumes the
reader is familiar with programming in general, and with Z80 Assembly Language
in particular (see Reference 1). Most of the information in this chapter relates
to several BIART registers through which the Z80B processor manages all board
functions. Several of these registers are mapped to access internal Z-SCC
registers; detailed programming information for this device is contained in
Reference 2 below.
Positive logic is assumed throughout the manual. That is, logic 0 is associated
with a more negative voltage (near 0 VOC), and logic 1 with a more positive
voltage (near +4 VOC). Reset means logic 0, and set means logic 1, as these
terms apply to bit states. The *notation appearing after a signal name means
that the signal is active in the logic 0 state (e.g., signal RESET* is active when
at logic 0 and inactive when at logic 1).
Reference 1
Reference 2
Zilog, Inc., Z80 Assembly Lan~ua~e Pro~ammin~ Manual, 1977
,Zilog, Inc., Z8030/Z8530 Seria I C&mmunication G.ontroller
Technical Manual, April 1982
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