ARM ETB11 Manual del producto

ARM DDI 0275D

ETB11™

Revision: r0p1

Technical Reference Manual

ETB11

Technical Reference Manual

Release Information

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Product Status

The information in this document is final, that is for a developed product.

Web Address

http://www.arm.com

Change history

Date Issue Change

December 2002 A First release

February 2003 B ETB revision has changed to r0p1

May 2003 C Description of ETMv1/ETMv2 supported removed.

August 2003 D Preface and Index updated and corrected, Resets correctly described 2.10.2,

and 3.2.5 RAM Data Register corrected.

Contents

ETB11 Technical Reference Manual

Preface

About this document ...................................................................................... x

Feedback ..................................................................................................... xiv

Chapter 1 Introduction

1.1 About the Embedded Trace Buffer ............................................................. 1-2

1.2 ETM versions and variants .......................................................................... 1-5

1.3 Silicon revision ............................................................................................ 1-6

Chapter 2 Functional Description

2.1 Functional information ................................................................................. 2-2

2.2 Operation .................................................................................................... 2-4

2.3 Control logic ................................................................................................ 2-6

2.4 Data Formatter ............................................................................................ 2-8

2.5 Trigger delay counter .................................................................................. 2-9

2.6 Address generation ................................................................................... 2-10

2.7 BIST interface ........................................................................................... 2-11

2.8 TAP controller ........................................................................................... 2-12

2.9 Trace RAM interface ................................................................................. 2-15

2.10 Clocks, and resets .................................................................................... 2-17

2.11 AHB transfers ............................................................................................ 2-19

Contents

Chapter 3 Programmer’s Model

3.1 About the programmer’s model .................................................................. 3-2

3.2 Register descriptions .................................................................................. 3-4

3.3 Software access to the ETB11 using the AHB interface .......................... 3-11

Chapter 4 Timing Requirements

4.1 AHB interface ............................................................................................. 4-2

4.2 CLK domain ................................................................................................ 4-4

4.3 IEEE1149.1 interface .................................................................................. 4-6

Appendix A Signal Descriptions

A.1 Signal properties and requirements ............................................................ A-2

A.2 Signal descriptions ..................................................................................... A-3

Appendix B Integrating the ETB11

B.1 ASIC connections ...................................................................................... B-2

B.2 Connecting to ETM11RV ............................................................................ B-3

B.3 Connecting the ETB11 in a 64-bit AHB system .......................................... B-4

Glossary

List of Tables

ETB11 Technical Reference Manual

Change history .............................................................................................................. ii

Table 1-1 ETM major architecture versions .............................................................................. 1-5

Table 2-1 Supported public instructions .................................................................................. 2-13

Table 2-2 Trace RAM interface signals ................................................................................... 2-15

Table 3-1 Register map ............................................................................................................. 3-2

Table 3-2 Identification register description ............................................................................... 3-4

Table 3-3 RAM Depth Register bit allocations .......................................................................... 3-5

Table 3-4 RAM Width Register bit allocations ........................................................................... 3-5

Table 3-5 Status Register bit allocations ................................................................................... 3-6

Table 3-6 RAM Data Register bit allocations ............................................................................ 3-7

Table 3-7 RAM Read Pointer Register bit allocations ............................................................... 3-7

Table 3-8 RAM Write Pointer Register bit allocations ............................................................... 3-8

Table 3-9 Trigger Counter Register bit allocations .................................................................... 3-9

Table 3-10 Control Register bit allocations ............................................................................... 3-10

Table 3-11 Registers that require software access ................................................................... 3-11

Table 4-1 AHB interface timing requirements ........................................................................... 4-2

Table 4-2 CLK domain timing requirements .............................................................................. 4-4

Table 4-3 IEEE1149.1 interface timing requirements ................................................................ 4-6

Table A-1 Signal descriptions .................................................................................................... A-3

Table B-1 ETB11 connection guide ........................................................................................... B-2

Table B-2 ETB11 to generic trace port interface connections ................................................... B-3

List of Tables

List of Figures

ETB11 Technical Reference Manual

Key to timing diagram conventions ............................................................................. xii

Figure 1-1 System-on-Chip debug implementation .................................................................... 1-2

Figure 2-1 ETB11 module block diagram ................................................................................... 2-3

Figure 2-2 Trace capture operation ............................................................................................ 2-6

Figure 2-3 Trace read operation ................................................................................................. 2-7

Figure 2-4 BIST interface block diagram .................................................................................. 2-11

Figure 2-5 Read access from Trace RAM timing diagram ........................................................ 2-16

Figure 2-6 Write access to Trace RAM timing diagram ............................................................ 2-16

Figure 2-7 Example synchronizer ............................................................................................. 2-17

Figure 2-8 Synchronization logic between HCLK and CLK domains ....................................... 2-20

Figure 2-9 Software read cycle with asynchronous CLK and HCLK ........................................ 2-21

Figure 2-10 Software read cycle with synchronous CLK and HCLK .......................................... 2-22

Figure 2-11 Software write cycle with asynchronous CLK and HCLK ........................................ 2-24

Figure 2-12 Software write cycle with synchronous CLK and HCLK .......................................... 2-25

Figure 4-1 AHB interface signals ................................................................................................ 4-2

Figure 4-2 CLK domain signals .................................................................................................. 4-4

Figure 4-3 IEEE1149.1 interface signals .................................................................................... 4-6

List of Figures

Preface

This preface introduces the ARM11 Embedded Trace Buffer (ETB11™) Techn ical

Reference Manual. It contains the following sections:

•About this document on page x

•Feedback on page xiv.

Preface

About this document

This document is the technical reference manual for the ARM11 Embedded Trace Buffer

(ETB11) r0p1.

Product revision status

The rnpnidentifier indicates the revision status of the product described in this manual,

where:

rnIdentifies the major revision of the product.

pnIdentifies the minor revision or modification status of the product.

Intended audience

This document has been written for experienced hardware and software engineers who

want to design or obtain trace information from chips that use ARM cores with the ETM

facility.

Using this manual

This document is organized into the following chapters:

Chapter 1 Introduction

Read this chapter for an overview of the ETB11.

Chapter 2 Functional Description

Read this chapter for a description of the major functional blocks,

configurability, read and write timing information, clocks, and resets.

Chapter 3 Programmer’s Model

Read this chapter for a description of the registers and programming

information.

Chapter 4 Timing Requirements

Read this chapter for a description of the ETB11 AC timing

requirements.

Appendix A Signal Descriptions

This appendix lists the ETB11 signals.

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