Analog Devices UG-200 Manual de usuario

Evaluation Board User Guide

UG-200

One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com

Evaluating the AD9467 16-Bit, 200 MSPS/250 MSPS ADC

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.Rev. 0 | Page 1 of 28

FEATURES

Full featured evaluation board for the AD9467

SPI and alternate clock options

Internal and external reference options

VisualAnalog and SPI Controller software interfaces

EQUIPMENT NEEDED

Analog signal source and antialiasing filter

2 switching power supplies (6.0 V, 2.5 A) CUI EPS060250UH-

PHP-SZ, included

PC running Windows® 98 (2nd ed.), Windows 2000,

Windows ME, or Windows XP

USB 2.0 port, recommended (USB 1.1 compatible)

AD9467 evaluation board

HSC-ADC-EVALCZ FPGA-based data capture kit

DOCUMENTS NEEDED

AD9467 data sheet

HSC-ADC-EVALCZ data sheet, High Speed Converter

Evaluation Platform (FPGA-based data capture kit)

AN-905 Application Note, VisualAnalog Converter Evaluation

Tool Version 1.0 User Manual

AN-878 Application Note, High Speed ADC SPI Control Software

AN-877 Application Note, Interface to High Speed ADCs via SPI

SOFTWARE NEEDED

VisualAnalog

SPI Controller

GENERAL DESCRIPTION

This document describes the evaluation board for the AD9467,

which provides all of the support circuitry required to operate the

AD9467 in its various configurations. The application software

used to interface with the device is also described.

The AD9467 data sheet, available at www.analog.com, which

provides additional information, should be consulted when using

the evaluation board. All documents and software tools are

available at http://www.analog.com/fifo. For any questions,

send an email to highspeed.con[email protected].

TYPICAL MEASUREMENT SETUP

09436-001

Figure 1. AD9467-250EBZ Evaluation Board and HSC-ADC-EVALCZ Data Capture Board

UG-200 Evaluation Board User Guide

Rev. 0 | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Equipment Needed........................................................................... 1

Documents Needed.......................................................................... 1

Software Needed............................................................................... 1

General Description ......................................................................... 1

Typical Measurement Setup ............................................................ 1

Revision History ............................................................................... 2

Evaluation Board Hardware ............................................................ 3

Power Supplies .............................................................................. 3

Input Signals...................................................................................3

Output Signals ...............................................................................3

Default Operation and Jumper Selection Settings....................5

Evaluation Board Software Quick Start Procedures.....................6

Configuring the Board .................................................................6

Using the Software for Testing.....................................................6

Evaluation Board Schematics and Artwork................................ 10

Ordering Information.................................................................... 25

Bill of Materials........................................................................... 25

REVISION HISTORY

10/10—Revision 0: Initial Version

Evaluation Board User Guide UG-200

Rev. 0 | Page 3 of 28

EVALUATION BOARD HARDWARE

The AD9467 evaluation board provides all of the support

circuitry required to operate the AD9467 in its various modes

and configurations. Figure 2 shows the typical bench charac-

terization setup used to evaluate the performance of the AD9467.

It is critical that the signal sources used for the analog input and

clock have very low phase noise (<1 ps rms jitter) to realize the

optimum performance of the signal chain. Proper filtering of

the analog input signal to remove harmonics and lower the

integrated or broadband noise at the input is necessary to

achieve the specified noise performance (see the AD9467

data sheet).

See the Evaluation Board Software Quick Start Procedures

section to get started and Figure 17 to Figure 31 for the

complete schematics and layout diagrams that demonstrate

the routing and grounding techniques that should be applied

at the system level.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching

power supply that provides a 6 V, 2.5 A maximum output. Connect

the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz

to 63 Hz. The other end is a 2.1 mm inner diameter jack that

connects to the PCB at P700. Once on the PC board, the 6 V

supply is fused and conditioned before connecting to low dropout

linear regulators that supply the proper bias to each of the various

sections on the board.

When operating the evaluation board in a nondefault condition,

E704, E705, E706, E707 can be removed to disconnect the

switching power supply. This enables the user to bias each section

of the board individually. Use P700 and P701 to connect a different

supply for each section. At least one 1.8 V supply is needed with

a 1 A current capability for 1.8 V AVDD1 and 1.8 V DRVDD;

however, it is recommended that separate supplies be used for

both analog and digital domains. An additional supply is also

required to supply 3.3 V to the DUT, 3.3 V AVDD2. This should

also have a 1 A current capability. To operate the evaluation board

using the SPI and alternate clock and amplifier options, a separate

3.3 V analog supply is needed in addition to the other supplies.

The 3.3 V supply, or 3.3 V 3P3V_AVDD, should have a 1 A

current capability.

INPUT SIGNALS

When connecting the ADC clock and analog source, use clean

signal generators with low phase noise, such as Rohde & Schwarz

SMA or HP8644B signal generators or the equivalent. Use a 1 m

shielded, RG-58, 50 Ω coaxial cable for making connections to

the evaluation board. Enter the desired frequency and amplitude

(refer to the specifications in the AD9467 data sheet).

If a different or external ADC clock source is desired, follow the

instructions in the Clock Circuitry section or use the on-board

crystal oscillator, Y200. Typically, most Analog Devices, Inc.,

evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave

input for the clock. When connecting the analog input source,

it is recommended to use a multipole, narrow-band band-pass

filter with 50 Ω terminations. Analog Devices uses TTE and

K&L Microwave, Inc., band-pass filters. The filter should be

connected directly to the evaluation board.

OUTPUT SIGNALS

The default setup uses the FIFO5 high speed, dual-channel

FIFO data capture board (HSC-ADC-EVALCZ). For more

information on this board and its optional settings, visit

http://www.analog.com/fifo.

UG-200 Evaluation Board User Guide

Rev. 0 | Page 4 of 28

09436-002

SIGNAL

SYNTHESIZER

CLOCK

INPUT

WALL OUTLET

100V TO 240V AC

47Hz TO 63Hz SWITCHING

POWER

SUPPLY

SWITCHING

POWER

SUPPLY

RUNNING ADC

ANALYZER

OR VisualAnalog

USER SOFTWARE

ANALOG INPUT

SIGNAL

SYNTHESIZER

Figure 2. Evaluation Board Connection

Evaluation Board User Guide UG-200

Rev. 0 | Page 5 of 28

DEFAULT OPERATION AND

JUMPER SELECTION SETTINGS

This section explains the default and optional settings or modes

allowed on the evaluation board for the AD9467.

Power Circuitry

Connect the switching power supply that is supplied in the

evaluation kit between a rated 100 V ac to 240 V ac wall outlet

at 47 Hz to 63 Hz and P700.

Analog Input Front-End Circuit

The evaluation board is set up for single-ended analog input

connection with an optimum 50 Ω impedance match of

350 MHz of bandwidth. For a different bandwidth response,

the input network needs to be changed or modified.

XVREF

XVREF is set to 1.25 V. This causes the ADC to operate with

the default internal reference in the 2.5 V p-p full-scale range.

A separate external reference option using the ADR130 is also

included on the evaluation board. Populate R400 with a 0 Ω

resistor. Note that ADC full-scale ranges from 2.0 V p-p to

2.5 V p-p are supported by the AD9467.

Clock Circuitry

The default clock input circuitry is derived from a simple

transformer-coupled circuit using a high bandwidth 1:1

impedance ratio transformer (T201) that adds a very low amount

of jitter to the clock path. The clock input is 50 Ω terminated

and ac-coupled to handle single-ended sine wave types of inputs.

The transformer converts the single-ended input to a differential

signal that is clipped before entering the ADC clock inputs.

The evaluation board can be set up to be clocked from the

crystal oscillator, Y200. This oscillator is a low phase noise

oscillator from Vectron (VCC6-QCD-250M000). If this clock

source is desired, install C205 and C206 and remove C202. Jumper

P200 is used to disable the oscillator from running.

A differential LVPECL or LVDS clock driver can also be used to

clock the ADC input using the AD9517 (U300). Populate C304,

C305, C306, and C307 with 0.1 µF capacitors for one drive option

or the other and remove C209 and C210 to disconnect the default

clock path inputs. The AD9517 has many SPI-selectable options

that are set to a default mode of operation. Consult the AD9517

data sheet for more information about these and other options.

Dx+, Dx−

If an alternative data capture method to the setup shown in

Figure 2 is used, optional receiver terminations, R500 to R509, can

be installed next to the high speed backplane connector, P502.

UG-200 Evaluation Board User Guide

Rev. 0 | Page 6 of 28

EVALUATION BOARD SOFTWARE QUICK START PROCEDURES

This section provides quick start procedures for using the AD9467,

either on the evaluation board or at the system level design.

Both the default and optional settings are described.

CONFIGURING THE BOARD

Before using the software for testing, configure the evaluation

board as follows:

1. Connect the evaluation board and the HSC-ADC-E VA LC Z

as shown in Figure 1 and Figure 2.

2. Connect one 6 V, 2.5 A switching power supply (such as

the CUI, Inc., EPS060250UH-PHP-SZ included) to the

evaluation board.

3. Connect one 6 V, 2.5 A switching power supply (such as

the CUI EPS060250UH-PHP-SZ included) to the HSC-

ADC-EVALCZ board.

4. Connect the USB cable to J6 on the HSC-ADC-EVALCZ

board to the PC.

5. On the evaluation board, place jumpers on all four pin

pairs of P600 to connect the SPI bus.

6. On the evaluation board, ensure that P200 is jumpered to

the off setting to use the on-board 250 MHz Vectron VC C 6

oscillator.

7. On the evaluation board, use a clean signal generator with

low phase noise to provide an input signal to the desired

channel. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable

to connect the signal generator. For best results, use a

narrow-band band-pass filter with 50 Ω terminations

and an appropriate center frequency. (Analog Devices

uses TTE, Allen Avionics, and K&L band-pass filters.)

USING THE SOFTWARE FOR TESTING

Setting Up the ADC Data Capture

After configuring the evaluation board, set up the ADC data

capture block using the following steps:

1. Open VisualAnalog® on a PC. AD9467 should be listed in

the status bar of the New Canvas window. Select the

template that corresponds to the type of testing to be

performed (see Figure 3).

09436-003

Figure 3. VisualAnalog, New Canvas Dialog Box

2. After the template is selected, a message box opens, asking

if the default configuration can be used to program the

FPGA (see Figure 4). Click Ye s , and the window closes.

If a different program is desired, follow Step 3.

09436-004

Figure 4. VisualAnalog, New Canvas Message Box

3. To view different channels or change features to settings

other than the default settings, click the Expand Display

button located on the top right corner of the VisualAnalog

window, as shown in Figure 5 and Figure 6.

This process is described in the AN-905 Application Note,

VisualAnalog Converter Evaluation Tool Version 1.0 User

Manual. Once you are finished, click the Collapse Display

button.

09436-005

EXPAND DISPLAY BUTTON

Figure 5. VisualAnalog Window Toolbar, Expand Display Button

Evaluation Board User Guide UG-200

Rev. 0 | Page 7 of 28

09436-006

COLLAPSE DISPLAY BUTTON

Figure 6. VisualAnalog, Main Window Expanded Display

4. Program the FPGA of the HSC-ADC-EVALCZ board to a

setting other than the default setting as described in Step 3.

Then expand the VisualAnalog display and click the Settings

button in the ADC Data Capture block (see Figure 6). The

ADC Data Capture Settings box opens (see Figure 7).

09436-007

Figure 7. ADC Data Capture Settings, Capture Board Tab

5. Select the Capture Board tab and browse to the appropriate

programming file. Next, click Program; the DONE LED, D6,

in the HSC-ADC-EVALCZ board should then turn on.

6. Exit the ADC Data Capture Settings box by clicking OK.

Setting Up the SPI Controller

After the ADC data capture board setup has been completed,

set up the SPI Controller:

1. Open the SPI Controller software by going to the Start

menu or double-clicking the SPI Controller software

desktop icon. If prompted for a configuration file, select

the appropriate one. If not, check the title bar at the top of

the SPI Controller window to determine which configura-

tion is loaded. If necessary, choose Cfg Open from the File

menu and select the appropriate configuration. Note that

the CHIP ID(1) field should be filled to indicate whether

the correct SPI Controller configuration file is loaded (see

Figure 8).

09436-008

Figure 8. SPI Controller, CHIP ID(1) Box

2. Click the New DUT button in the SPI Controller (see

Figure 9).

09436-009

NEW DUT BUTTON

Figure 9. SPI Controller, New DUT Button

3. Click the Run button in the VisualAnalog toolbar (see

Figure 10).

09436-010

RUN BUTTON

Figure 10. VisualAnalog Window Toolbar, Run Button

UG-200 Evaluation Board User Guide

Rev. 0 | Page 8 of 28

Applying Input Signal and Optimizing SFDR

Apply the input signal as follows:

1. Apply the input signal so that the fundamental is at the

desired level (examine the Fund Power reading in the left

panel of the VisualAnalog FFT window). See Figure 11

and Figure 12.

09436-011

Figure 11. VisualAnalog, FFT Graph, No Signal or Very Low Signal Applied

09436-012

Figure 12. VisualAnalog, FFT Graph, Full-Scale Signal Applied

09436-013

Figure 13. Typical FFT, AD9467 (No Buffer Current Optimization)

2. To optimize SFDR performance, use Register 36 and

ADCBase 0 tab of the SPI Controller, find the BUFFER(36)/

BUFFER(107) box. Use the drop-down list box to select

the best current, if necessary. See the AD9467 data sheet, the

AN-878 Application Note, and the AN-877 Application

Note for reference.

09436-014

Figure 14. SPI Controller, BUFFER(36)/BUFFER(107)

Evaluation Board User Guide UG-200

Rev. 0 | Page 9 of 28

09436-015

Figure 15. SPI Controller, SPI Controller, BUFFER(36)/BUFFER(107) Drop-

Down Setting

09436-016

Figure 16. Typical FFT, AD9467 (With Buffer Current Optimized)

UG-200 Evaluation Board User Guide

Rev. 0 | Page 10 of 28

EVALUATION BOARD SCHEMATICS AND ARTWORK

09436-017

ANALOGINPUTCIRCUITRY

L OR R

AMP

L OR R

AIN

ENABLE

OFF

AIN

DNI

B0310E5050A00

DNI

SMA-J-P-X-ST-EM1

MABA-007159-000000

DNI

R132

R131

R134

R133

R130

R103

L105

T104

R129

954

T105

R128

R127

R125

R126

4 3

T103

J102

R124

R123

R100

R101

R104

R108

R107

R110

R109

L100

R118

R117

C120C119

L103

L104L101

L102R106

R105

C116

C115

R122

R116

R102

R115

C101

C100

C105

C106

P100

R114

R113

C113

R121

C114

C111

PAD

U100

543

J101

543

J100

C110

C107

C109

C108

C104

C103

C102

N P

C112

711C811C

R120

R119

R112R111

T101

4 3

T102

T100

ADL5562_PRELIM

DNI

0.1UF

DNI

0.1UF

DNI

0.1UF

DNI

0.1UF

DNI

0.1UF

TBD0201

DNI

TBD0201

DNI

TBD0201

DNI

120NH

10NH

ADT1-1WT+

MABA-007159-000000

DNI

DNIDNI

AMPOUT-

AMPOUT+

DNI

AMPOUT+

AMPOUT-

DNI

SMA-J-P-X-ST-EM1

DNI

AVDD_3P3V

10UF

DNI

1.00K

DNI

15NH

DNI

36NH

FP93FP001

DNI

AVDD_3P3V

DNI

5.6

36NH15NH

INDIND

5.6

DNI

1.00K

DNI

ADT1-1WT+

DNI

MABA-007159-000000

AIN+

AIN-

TBD0201

SEC

PRI

AGND

SECPRI

AGND

GND

BAL_PORT2

BAL_PORT1DIFF_IN

UNBAL

AGND

SECPRI

AGND

PADGND

ENBL

VON

VOP

VCOM

VCC

VIN2

VIN1

VIP1

VIP2

AGND

Figure 17. DUT Analog Input Circuits

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