Analog Devices ADRF6650-EVALZ Manual de usuario

ADRF6650-EVALZ User Guide

UG-1026

One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com

Evaluating the

ADRF6650

450 MHz to 2700 MHz Dual Downconverter with

DVGA and PLL/VCO

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.Rev. A | Page 1 of 17

FEATURES

Full featured evaluation board for the ADRF6650

Single supply: 5.6 V (1 A capability required)

ACEsoftware for control

EVALUATION KIT CONTENTS

ADRF6650-EVALZ evaluation board

EQUIPMENT NEEDED

SDP-S controller board

Analog signal sources

Power supply of 5.6 V (1 A capability required)

PC running Windows® XP or Windows 7

USB 2.0 port recommended

SOFTWARE NEEDED

Analysis | Control | Evaluation (ACE)

DOCUMENTS NEEDED

ADRF6650 data sheet

GENERAL DESCRIPTION

The ADRF6650-EVA LZ is a 4-layer Rogers printed circuit

board (PCB) and evaluates the performance of the ADRF6650.

A photograph of the evaluation board is shown in Figure 1. The

evaluation board contains the ADRF6650, a connector suited

for a SDP-S controller board, power supply connectors, regulators,

and subminiature Version A (SMA) connectors. The evaluation

board requires an SDP-S controller board to allow software

programming of the device.

The ADRF6650 is a high performance, dual downconverter that

integrates mixers, digital switched attenuators, digital variable gain

amplifiers (DVGAs), a phase-locked loop (PLL), and a voltage

controlled oscillator (VCO). The device uses broadband, square

wave limiting, local oscillator (LO) amplifiers to achieve an RF

bandwidth of 450 MHz to 2700 MHz. Unlike conventional,

narrow-band, sine wave LO amplifier solutions, the ADRF6650

allows the application of the LO either above or below the RF

input, over a bandwidth of 450 MHz to 2900 MHz.

This user guide describes the ADRF6650-EVA L Z evaluation board

and software. For full details, see the ADRF6650 data sheet, which

must be consulted in conjunction with this user guide when using

the evaluation board.

UG-1026 ADRF6650-EVALZ User Guide

Rev. A | Page 2 of 17

TABLE OF CONTENTS

Features .............................................................................................. 1

Evaluation Kit Contents................................................................... 1

Equipment Needed........................................................................... 1

Software Needed............................................................................... 1

Documents Needed.......................................................................... 1

General Description......................................................................... 1

Table of Contents.............................................................................. 2

Revision History ............................................................................... 2

ADRF6650 Evaluation Board Photograph.................................... 3

Evaluation Board Hardware............................................................ 4

Power Supply................................................................................. 4

RF Inputs ....................................................................................... 4

LO Generation and External LO Input ......................................5

IF Outputs ......................................................................................5

Serial Port Interface (SPI) ............................................................5

Evaluation Board Software and Quick Start Procedures .............6

Software Requirements and Installation ....................................6

ADRF6650 Graphical User Interface (GUI) Quick Start.........6

ADRF6650 GUI Components .....................................................7

Checking the USB Connectivity .................................................8

Updates to the ACE Software Plug-Ins ......................................8

Evaluation Board Schematics and Artwork...................................9

Ordering Information.................................................................... 15

Bill of Materials........................................................................... 15

REVISION HISTORY

11/2019—Revision A

ADRF6650-EVALZ User Guide UG-1026

Rev. A | Page 3 of 17

EVALUATION BOARD PHOTOGRAPH

14814-101

Figure 1. ADRF6650-EVALZ Evaluation Board

UG-1026 ADRF6650-EVALZ User Guide

Rev. A | Page 4 of 17

EVALUATION BOARD HARDWARE

RF INPUT A

RF INPUT B

REFERENCE

INPUT

CHANNELA

SINGLE-ENDED

IF OUTPUT

CHANNELB

SINGLE-ENDED

IF OUTPUT

SINGLE SUPPLY

+5.6V

SDP-S CONTROLLER

BOARD

*THE DEFAULT CONFIGURATION IS SINGLE-ENDED

OUTPUT THROUGH THE 1:1 BALUN AND OUTPUT

MATCHING NETWORK. THE OUTPUT IS ROUTED

TO IF_I_OUT_POS.

EXTERNAL LO INPUT

LO OUTPUT

USB CONNECTION

TO COMPUTER

*THE DEFAULT CONFIGURATION IS SINGLE-ENDED

OUTPUT THROUGH THE 1:1 BALUN AND OUTPUT

MATCHING NETWORK. THE OUTPUT IS ROUTED

TO IFOUT_A_POS.

GROUND

14814-002

Figure 2. ADRF6650-EVALZ Typical Measurement Setup

The ADRF6650-EVA LZ provides the support circuitry required

to operate the ADRF6650 in various modes and configurations.

Figure 2 shows the typical measurement setup that evaluates the

performance of the ADRF6650.

POWER SUPPLY

The ADRF6650-EVA L Z evaluation board requires a single, 5.6 V

power source. The power supply design on the ADRF6650-

EVA L Z evaluation board consists of low dropout dc regulators

that regulate the 5.6 V source to 3.3 V power rails for the main IC.

RF INPUTS

The ADRF6650 supports two single-ended 50 Ω terminated RF

inputs. The operational frequency range of the RF inputs is from

450 MHz to 2700 MHz and the inputs must be ac-coupled.

ADRF6650-EVALZ User Guide UG-1026

Rev. A | Page 5 of 17

LO GENERATION AND EXTERNAL LO INPUT

The ADRF6650 offers two alternatives to generating the differential

LO input signal: externally via a high frequency, low phase noise

LO signal or internally via the on-chip, fractional-N synthesizer

and on-chip, voltage controlled oscillators (VCOs). In either

case, the differential LO signal can be routed off-chip through

the balun to the subminiature A (SMA) connector, LO_OUT.

For an internal LO configuration using the on-chip, fractional-

N synthesizer, apply a low phase noise reference signal to the

reference input, shown in Figure 2. The phase-locked loop

(PLL) reference input can support a wide frequency range,

because the dividing blocks or multiply blocks can increase or

decrease the reference frequency to the desired phase frequency

detector (PFD) frequency value. The integrated synthesizer

enables continuous LO coverage from 450 MHz to 2900 MHz.

The PLL filter components populated on the evaluation board

are for a 20 kHz bandwidth (see Figure 23).

For optimum performance using an external LO source, drive

the LO inputs using the EX_LO_NEG and EX_LO_POS

connectors on the evaluation board. The wide input range of

the external LO input spans from 450 MHz to 2900 MHz. Unless

an ac-coupled balun generates the differential LO, the inputs

must be ac-coupled. The input impedance of the differential LO

signals is 100 Ω and must be taken into account when driving

differentially. For the default configuration of the LO inputs on

the ADRF6650-EVA L Z , apply a single-ended LO input to the

SMA labeled EX_LO_NEG, the on-board balun converts the

signal to differential.

IF OUTPUTS

The ADRF6650 intermediate frequency (IF) outputs have a

differential impedance of 10 Ω as looking into the IF output

pins. External series 25 Ω resistors on each differential line

optimizes the performance of the ADRF6650. The output

impedance with the 25 Ω series resistors displays as 60 Ω

differential for both IF outputs. The 60 Ω differential output

impedance terminates with 100 Ω differential for optimal

performance, providing a good output impedance match and

linearity performance.

For measurement purposes with instruments that have 50 Ω

input impedance, the evaluation board employs a 1:1 transformer

(TC1-1-13MX+) and a resistive matching network, shown in

Figure 20. The TC1-1-13MX+ is a wide bandwidth (4.5 MHz to

3000 MHz) 1:1 transformer with a flat passband response and

converts single-ended 50 Ω resistance to 50 Ω differential

resistance. A resistive matching network converts the 50 Ω

differential impedance to 100 Ω differential. The circuit topology

allows the 60 Ω IF output impedance to terminate with 100 Ω

impedance in a 50 Ω measurement environment. The resistive

matching network introduces a loss around 7.5 dB and the user

must account for the associated loss in measurements.

The ADRF6650-EVA L Z evaluation board is configured for

single-ended outputs in default mode. For a single-ended

output, use the IFOUT_A_POS connector with the on-board

balun. For a single-ended output, use the IFOUT_B connector

with the on-board balun.

SERIAL PORT INTERFACE (SPI)

The SPI of the ADRF6650 consisting of the SCLK, SDIO, SDO,

and CS pins, is controlled via an external SDP-S controller board

and the ACE software.

UG-1026 ADRF6650-EVALZ User Guide

Rev. A | Page 6 of 17

EVALUATION BOARD SOFTWARE AND QUICK START PROCEDURES

The ADRF6650-EVALZ with the SDP-S controller board is

configured with a USB friendly interface to allow programmability

of the ADRF6650 registers. The Analog Devices, Inc., ACE soft-

ware provides a user friendly experience for complete control of

the evaluation board and features.

SOFTWARE REQUIREMENTS AND INSTALLATION

Installing the ACE Software Suite

Download the ACE installation executable ACEInstall_

Versi on .exe from the Analog Devices website.

Run ACEInstall_Version.exe to begin the installation process.

The default path where the ACE software is installed on the PC

is C:\Program Files (x86)\Analog Devices\ACE.

For convenience, create a desktop icon for the ACE software.

Find ACE.exe under the default path and double-click to run

the ACE software. Alternatively, the ACE software can run from

the Start menu by navigating to the Analog Devices folder, and

run the ACE software under the ACE folder.

ADRF6650 GRAPHICAL USER INTERFACE (GUI)

QUICK START

Connect the SDP-S controller board with the USB cable

connected to the computer and power up the ADRF6650-

EVALZ. Initially, the 5.6 V power supply draws about 210 mA.

When the evaluation board is fully configured, the power supply

draws about 700 mA. The following steps outline how to begin

using the ACE software:

1. Double-click the ACE shortcut (see Figure 3) available

under the C:\Program Files (x86)\Analog Devices\ACE

directory.

14814-003

Figure 3. ACE.exe Shortcut Icon

2. When the software main window opens, it automatically

detects the ADRF6650-EVALZ. Double-click the

ADRF6650 Board icon shown in Figure 4. This brings the

user to ADRF6650 Board tab (see Figure 5).

14814-004

Figure 4. ACE Software Start Page when the ADRF6650-EVALZ Connects

14814-005

Figure 5. ADRF6650 Board Tab View

3. From the ADRF6650 Board tab, double-click the ADRF6650

icon to open the ADRF6650 Board tab (see Figure 7). The

ADRF6650 Board tab allows the user to configure the

ADRF6650 in any desired configuration.

4. Set the LO Freq field to the desired LO frequency.

5. Adjust the channel spacing for PLL/VCO steps by using the

Ch Spacing field.

6. Enter the reference frequency and the R divider value into

the fields placed under the REF In field in the GUI. Ensure

the PFD frequency stays within the data sheet limits.

7. Click PLL Set button to lock the PLL and VCO. Check the

on-board LED (DS1) or the LOCK_DETECT register on

the ADRF6650 to ensure the PLL/VCO is locked.

8. Turn on the LO buffer to quadrature divider by clicking on

the triangle buffer icon beneath the LO Out Level spin box.

9. Connect an RF input source from a signal generator to

SMAs labeled as either RF_INP_A or RF_INP_B, for

Channel A and Channel B, respectively.

10. Check the IF output of the corresponding channel on the

evaluation board. The resistive matching network at the IF

outputs schematic introduces a 7.5 dB loss.

ADRF6650-EVALZ User Guide UG-1026

Rev. A | Page 7 of 17

14814-206

Figure 6. ADRF6650 GUI Interface

ADRF6650 GUI COMPONENTS

This section describes the components within the ACE software

GUI, which enables thorough control of all the elements of the

ADRF6650.

ADRF6650 Board Tab

The ADRF6650 Board tab includes the Reset Board button,

the Poll Device button, and the Auto Apply button (see Figure 7).

14814-007

Figure 7. ADRF6650 Board Tab

The Reset Board button applies a soft reset to the device. The

Auto Apply button applies the changes made to the GUI without

the need to click Apply Changes after every change. The Poll

Device button is not employed within the ADRF6650 GUI.

ADRF6650 Tab

Figure 6 shows the ADRF6650 Board tab, which displays the

main controls required to configure the device.

There are four user-controllable elements within the GUI. The

following list describes the four elements:

•Click PLL Set (see Figure 8) to activate a series of predefined

PLL/VCO.

14814-008

Figure 8. PLL Set Button

•The entry fields within the GUI enable manual entry of a

desired value (for example, see Figure 9). Input values are

written and entered by pressing Enter. The changes made

for the PLL/VCO related controls and fields are applied

with the PLL Set button to initiate the locking process. For

controls other than the PLL/VCO, click the Apply

Changes button.

14814-009

Figure 9. LO Freq Field

•Spin boxes, check boxes, and dropdown menus allow users

to select predefined values. These elements do not start a

button to produce the PLL/VCO related register writes and

Apply Changes button all other controls. Figure 10 shows an

example of a spin box. Figure 11 shows a dropdown menu

item to select between the internal VCO and external LO

configurations.

14814-010

Figure 10. Gain Mode Dropdown Menu and FA StepSpin Box

14814-011

Figure 11. Configuration Dropdown Menu

UG-1026 ADRF6650-EVALZ User Guide

Rev. A | Page 8 of 17

14814-212

Figure 12. ADRF6650 Memory Map Tab

•The user can enable or disable some of the components by

clicking associated controllable graphics. Controllable

graphics do not automatically start a register write operation

and the user must click the Apply Changes button or the

PLL Set button to produce the related register writes.

When a controllable graphic displays as gray (see Figure 13),

the component is disabled. When a controllable graphic

displays as blue (see Figure 14), the component is enabled.

14814-013

Figure 13. Disabled Component

14814-014

Figure 14. Enabled Component

Some of the components have a pale blue color

(see Figure 15), indicating the graphical object is not

controllable by clicking on it.

14814-015

Figure 15. Noncontrollable

ADRF6650 Memory Map Tab

The Proceed to Memory Map button (see Figure 16) in the

ADRF6650 tab directs the user to the ADRF6650 memory map

for bit control of the register map (see Figure 12).

14814-016

Figure 16. Proceed to Memory Map Button

The register write and reads are performed with the +and −

buttons of the ADRF6650 Memory Map tab (see Figure 12). All

changes made in the GUI simultaneously apply to the ADRF6650

Memory Map tab and changes made in the ADRF6650 Memory

Map tab simultaneously apply to the GUI.

CHECKING THE USB CONNECTIVITY

If the user encounters an error while configuring the device,

check the USB connectivity of the evaluation board under the

System tab (see Figure 7). Figure 17 shows the Subsystem_1

window where the user can observe the connectivity of the

SDP-S board and the ADRF6650-E VA LZ .

14814-017

Figure 17. ADRF6650 ACE GUI System Tab

In the SDP-S Controller pane, there is a USB button. When the

button is green, the USB is connected. Clicking the USB button

reveals the connection options menu between the SDP-S

controller board and the evaluation board. Ensure the

ADRF6650 Board option in the System tab is selected. The

ADRF6650 Board (Local Only) option does not provide

connectivity.

Users can also check USB connectivity in the status bar of the ACE

software, located in the bottom left of the GUI. State, which

indicates the USB connectivity, must show Good at all times.

UPDATES TO THE ACE SOFTWARE PLUG-INS

Analog Devices periodically updates the ACE software and the

device plug-ins to ensure the best possible user experience.

Update the ACE software if there is indication of a new version

when running the ACE software.

ADRF6650-EVALZ User Guide UG-1026

Rev. A | Page 9 of 17

EVALUATION BOARD SCHEMATICS AND ARTWORK

50 OHMS COPLANAR TRACE

0.1uF

100PF

0.1uF

100PF

ADRF6650

100PF

0.1uF

DNI

VCC_PLL_DIG

VCC_B_CM

VCC_IF_AMP_B

VCC_VCO

VCC_LO

VCC_CP

VCC_DVGA_A

VCC_A_CM

VCC_MIXER_LOB

VCC_DIV

VCC_DVGA_B

VCC_MIXER_B

VCC_DIV

VCC_PFD

VCC_PLL_REF

VCC_MIXER_A

VCC_IF_AMP_A

VCC_MIXER_LOA

0.1uF

120OHM

5.1K

0.1uF

100PF

270nH

DNI

100PF

DNI

100PF

0.1uF

100PF

DNI

100PF DNI

10uF

100PF

DNI

100PF

DNI

100PF

150NH

100PF

5.1K

100PF

270nH

0.1uF

270nH

10uF

10uF 100PF

10uF

DNI

10uF

150NH

100PF

0.1uF

100PF

5.1K

0.1uF

1/16W

0.1uF

1nH

C4C47

C84

C38

C94

C93

C90

C35

C26

C32

C51

C80

C72

C66

R38

R69

R99

C42

C29

C40

C70

C59

C71

C87

C98C89

C83

C67

C15

C16

C41

C34

C36

C39

C14C23

C24

C27C22

C52

C28

C31

C12

C49

C37

C30

R135

L23

C69 U1

C48

C11 C9

C45

C33

C103

L24

C18

C85

C99

C95

C21

C50C44

C13

CHA_DATA

CHA_CLK

RF_INP_B

CSB

SDO

CHB_DATA

CHB_CLK

RSTB

SDIO

SCLK

LCKDT

TDD_CH_B

EX_LO_IN–

EX_LO_IN-

EX_LO_IN+

VTUNE

CP_OUT

TDD_CH_A

REFERENCE

RF_INP_A

EX_LO_IN+

PAD

142

5417

SPI

PFD

GND

IFOUT_A-

IFOUT_A+

VCC_DVGA_A

RXA_ATT_DATA

RXA_ATT_CLK

VCPL_A

MIX_PU_A-

MIX_PU_A+

RXB_ATT_DATA

RXB_ATT_CLK

VCC_DVGA_B

IFOUT_B+

IFOUT_B-

VCPL_B

MIX_PU_B-

MIX_PU_B+

LO_OUT-

LO_OUT+

EXT_LO_IN-

EXT_LO_IN+

CSB

SDO

SDIO

SCLK

TDD_B

RFIN_B

RFBT_B

RFBT_A

RFIN_A

TDD_A

VCC_MIX_B

VCC_LOA_S1

VCC_LOA_S2

VCC_LOB_S2

VCCLO_AUX_3V3

VCCFBDIV_3V3

VTUNE

VCCLO_MIX_3V3

VCCVCO_3V3

VCCDIV_3V3

DCL_BIAS

VCCCP_3V3

CPOUT

VCC_MIX_A

PAD

RSTB

LO_LCKDT

REF_IN

VBAT_DIG_3V3

SDMLDO_OUT_1V8

SPILDO_OUT_1V8

VCCPFD_3V3

VCCREF_3V3

VCC_LOB_S1

OUT

14814-018

Figure 18. ADRF6650-EVALZ Schematic

UG-1026 ADRF6650-EVALZ User Guide

Rev. A | Page 10 of 17

DNI 4300PF

4300PF

0.12uF

220

220 0

R28 R26

C81

C82 C63

R27 C75

R23 VTUNE

CP_OUT

14814-019

Figure 19. PLL Filter

0.1uF

0.1uF DNI

DNI

DNI00

0DNI

DNI

035.7

DNI DNI DNI

35.7

TC1-1-13MX+

DNI

R13

R14 R42

R29

R30

R33

R39

R34R21 R159

R22 R133

R131

R24

C112

R18

C60 T1

C58

L28

C107L26 L26

R10

R17R160

IFOUT_B_POS

IFOUT_B

3 4

2NC

SEC PRI

OUT

14814-020

Figure 20. IF Output Schematic

DNI

0TCM1-83X+

DNI DNI

R44 R145

R45

C86

C88

R115

R48

R46

R47

R43

R148

R144

R100R101

LO_OUT

LO_OUT_POS

OUT

14814-021

Figure 21. LO Output Schematic

OUT

0.1uF

DNIDNI

DNI

TC1-1-13MX+

DNI DNI

35.7

DNI

35.7

R15

R16

R25

R40R35

R41

R31

R32

R36

R163

R164

R161

R162

R134

R132

C54

C62

R12

R11

R20

C64

R19

C55 L31

L29

IFOUT_A_POS

IFOUT_A

3 4

SEC PRI

14813-022

Figure 22. External LO Input Schematic

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