Analog Devices EVAL-ADG5209FEBZ Manual de usuario

EVAL-ADG5209FEBZ User Guide

UG-875

One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com

Evaluating the ADG5209F, Overvoltage Protected Dual 4:1 Multiplexer

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.Rev. 0 | Page 1 of 12

FEATURES

Supply voltages

Dual supply: ±5 V to ±22 V

Single supply: 8 V to 44 V

Protected against overvoltage on source pins

Signal voltages up to −55 V and +55 V

Parallel interface compatible with 3 V logic

On-board low dropout (LDO) regulator for digital supply and

control, if required

EVALUATION KIT CONTENTS

EVAL-ADG5209FEBZ evaluation board

ONLINE RESOURCES

Documents Needed

ADG5209F data sheet

EVAL-ADG5209FEBZ user guide

EQUIPMENT NEEDED

DC voltage source

±22 V for dual supply

44 V for single supply

Optional digital logic supply: 3 V to 5 V

Analog signal source

Method to measure voltage, such as a digital multimeter (DMM)

GENERAL DESCRIPTION

The E VA L -ADG5209FEBZ is the evaluation board for the

ADG5209F and features an overvoltage protected dual 4:1

multiplexer. The ADG5209F has overvoltage detection and

protection circuitry on the source pins and is protected against

signals up to −55 V and +55 V in both the powered and

unpowered states.

Figure 1 shows the E VA L -ADG5209FEBZ in a typical evaluation

setup. The ADG5209F is soldered to the center of the evaluation

board, and wire screw terminals are provided to connect to each

of the source and drain pins. Three screw terminals are used to

power the device, with a fourth terminal used to provide a user

defined digital logic supply voltage, if required. Alternatively, a

low dropout (LDO) regulator is provided for 5 V digital logic

supply.

Full specifications on the ADG5209F are available in the

ADG5209F data sheet, which should be consulted in

conjunction with this user guide when using the evaluation

board.

TYPICAL EVALUATION SETUP

13457-001

Figure 1. EVAL-ADG5209FEBZ (on Right), Power Supply, and Signal Generator

UG-875 EVAL-ADG5209FEBZ User Guide

Rev. 0 | Page 2 of 12

TABLE OF CONTENTS

Features .............................................................................................. 1

Evaluation Kit Contents................................................................... 1

Online Resources.............................................................................. 1

Equipment Needed........................................................................... 1

General Description ......................................................................... 1

Typical Evaluation Setup ................................................................. 1

Revision History ............................................................................... 2

Getting Started .................................................................................. 3

Evaluation Board Setup Procedure ............................................ 3

Evaluation Board Hardware.............................................................4

Power Supply..................................................................................4

Input Signals...................................................................................4

Jumper Settings..................................................................................5

Switches and 0 Ω Resistors...........................................................5

SMB Connectors............................................................................5

Evaluation Board Schematics and Artwork...................................6

Ordering Information.................................................................... 11

Bill of Materials........................................................................... 11

REVISION HISTORY

8/15—Revision 0: Initial Version

EVAL-ADG5209FEBZ User Guide UG-875

Rev. 0 | Page 3 of 12

GETTING STARTED

EVALUATION BOARD SETUP PROCEDURE

The EVAL-ADG5209FEBZ evaluation board is designed to

operate independently and does not require any additional

evaluation boards or software to operate. An on-board LDO

regulator is provided as the digital power supply to manually

control the ADG5209F.

Supply the evaluation board with a dual power source of up to

±22 V or a single supply of up to 44 V by connecting VSS and

GND together.

A functionality test can be set up as follows:

1. Connect a power supply to J5. Connect VSS and GND

together if a single supply is required.

2. Ensure a 0 Ω resistor is inserted in R15 to use the on-board

LDO regulator, and that a 0 Ω resistor is inserted in R14.

3. SW1 through SW3 control the digital signals for the

ADG5209F.

S1A

ADG5209F

ADP7142

(LDO) S4A

J1:S1A

J3:DA

J1:S4A

VDD

EXT_VL

VSS

GND

FAULT DETECTION

AND

SWITCH DRIVER

R13=EXT_VL

R14=LDO

SW1

SW2

SW3

J2:S1B

J2:S4B

S1B

S4B

J4:DB

13457-002

Figure 2. EVAL-ADG5209FEBZ Block Diagram

UG-875 EVAL-ADG5209FEBZ User Guide

Rev. 0 | Page 4 of 12

EVALUATION BOARD HARDWARE

The operation of the ADG5209F is evaluated using the E VA L -

ADG5209FEBZ. Figure 1 shows a typical evaluation setup

where only a power supply and signal generator are required.

Figure 2 shows the block diagram of the main components of

the evaluation board.

Using this evaluation board, the ADG5209F passes signals from

either the source or drain connectors. The source pins have fault

detection circuitry that react to an overvoltage event. During an

overvoltage event, the channel on which the fault occurs is

turned off. See the ADG5209F data sheet for more details.

POWER SUPPLY

Connector J5 provides access to the supply pins of the

ADG5209F. VDD, GND, and VSS on J5 link to the appropriate

pins on the ADG5209F. For dual supply voltages, the evaluation

board can be powered from ±5 V to ±22 V. For single supply

voltages, the GND and VSS terminals must be connected together,

and power the evaluation board with 8 V to 44 V. Additionally,

an on-board LDO regulator is provided for a digital control

voltage. If necessary, a secondary voltage source can be

connected to EXT_VL and used to control the digital voltages.

To use EXT_VL, move the 0 Ω resistor from R14 to R13. Do not

expose the on-board LDO regulator to voltages greater than

28 V; remove R15 and supply an alternative digital voltage via

EXT_VL, if required.

INPUT SIGNALS

Four screw connectors are provided to connect to both

the source and drain pins of the ADG5209F. Additional

subminiature Version B (SMB) connector pads are available if

extra connections are required. The ADG5209F is overvoltage

protected on the source side, and each source terminal (S1A to S4A

and S1B to S4B) can be presented with a voltage of up to +55 V or

−55 V. See the ADG5209F data sheet for more details.

Each trace on the source and drain side includes two sets of

0603 pads, which can be used to place a load on the signal path

to ground. A 0 Ω resistor is placed in the signal path and can be

replaced with a user defined value. Use the resistor combined

with the 0603 pads to create a simple resistor-capacitor (RC)

filter.

The ADG5209F uses a parallel interface to control the operation of

the switches. The switch operation can be manually controlled

using the SW1 to SW3 switches, or an external controller can be

interfaced directly to the control pins by using the SMB connectors

(EN, A0, and A2) and removing the 0 Ω R31, R33, and R35

resistors.

EVAL-ADG5209FEBZ User Guide UG-875

Rev. 0 | Page 5 of 12

JUMPER SETTINGS

SWITCHES AND 0 Ω RESISTORS

Switches are used to control the ADG5209F manually and

0 Ω resistors are used to configure the digital control voltage.

Table 2 shows a summary of the switches and 0 Ω resistors and

how they are used on the evaluation board.

Use SW2 and SW3 to control the switches of the ADG5209F.

Position L is tied to GND and sets the logic low, and Position H

is tied to VL and sets the logic high.

Use SW1 to enable or disable the device. Position DIS is tied to

GND and disables the device, and Position EN is tied to VL and

enables the device.

Table 1. ADG5209F Truth Table

SW1 (EN) SW2 (A0) SW3 (A1) Connected Sx

DIS X1X

1All switches off

EN L L S1A/S1B

EN L H S2A/S2B

EN H L S3A/S3B

EN H H S4A/S4B

1X means don’t care.

R15 connects the on-board LDO regulator to the VDD supply.

Remove this resistor to protect the LDO regulator from voltages

higher than 28 V. Change the 0 Ω resistor to Position R13 to use

an alternative digital voltage connected to DC_V1.

SMB CONNECTORS

The parallel interface of the ADG5209F is controlled manually

using the link headers of SW1 to SW4, or it can be accessed using

the SMB connectors, EN, A0, A1, and A2. To use the SMB

connectors, remove the 0 Ω R31, R33, and R35 resistors.

Table 2. Switch and 0 Ω Resistor Descriptions

Label Position Description

SW1 EN Logic 0 on the EN pin

DIS Logic 1 on the EN pin

SW2 L Logic 0 on the A0 pin

H Logic 1 on the A0 pin

SW3 L Logic 0 on the A1 pin

H Logic 1 on the A1 pin

R13/R14 R14 On-board LDO regulator digital voltage

R13 EXT_VL digital voltage

R15 Inserted LDO regulator powered up

Removed LDO regulator unpowered

R31, R33, R35 Inserted SW1 to SW3 are used to control digital logic

Removed SMB connectors are used to control digital logic

UG-875 EVAL-ADG5209FEBZ User Guide

Rev. 0 | Page 6 of 12

EVALUATION BOARD SCHEMATICS AND ARTWORK

13457-008

Figure 3. ADG5209F Evaluation Board Schematic (Part 1)

EVAL-ADG5209FEBZ User Guide UG-875

Rev. 0 | Page 7 of 12

13457-008

Figure 4. ADG5209F Evaluation Board Schematic (Part 2)

13457-010

Figure 5. ADG5209F Evaluation Board Schematic (Part 3)

UG-875 EVAL-ADG5209FEBZ User Guide

Rev. 0 | Page 8 of 12

13457-007

Figure 6. EVAL-ADG5209FEBZ Silkscreen

13457-003

Figure 7. EVAL-ADG5209FEBZ Top Layer

EVAL-ADG5209FEBZ User Guide UG-875

Rev. 0 | Page 9 of 12

13457-004

Figure 8. EVAL-ADG5209FEBZ Layer 2

13457-005

Figure 9. EVAL-ADG5209FEBZ Layer 3

UG-875 EVAL-ADG5209FEBZ User Guide

Rev. 0 | Page 10 of 12

13457-006

Figure 10. EVAL-ADG5209FEBZ Bottom Layer

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