Analog Devices EVAL-ADGS1612SDZ Manual de usuario

EVAL-ADGS1612SDZ User Guide

UG-1199

One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com

Evaluation Board for the ADGS1612 SPI Interface, 1 Ω RON, ±5 V, 12 V, 5 V, 3.3 V,

Mux Configurable, Quad SPST Switch

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 11

FEATURES

SPI interface with error detection

Includes CRC, invalid read/write address, and SCLK count

error detection

Analog supply voltages

Dual-supply: ±3.3 V to ±8 V

Single-supply: 3.3 V to 16 V

PC control in conjunction with the evaluation software

EVAL-SDP-CB1Z SDP

PACKAGE CONTENTS

EVAL-ADGS1612SDZ

DOCUMENTS NEEDED

ADGS1612 data sheet

EQUIPMENT NEEDED

EVAL-SDP-CB1Z controller board

ACE software with EVAL-ADGS1612SDZ plug-in

DC voltage source

±5.5 V for dual-supply

12 V, 5V, 3.3V for single-supply

Optional digital logic supply: 3.3 V

Analog signal source

Method to measure voltage, such as a digital multimeter (DMM)

GENERAL DESCRIPTION

The EVAL-ADGS1612SDZ is the evaluation board for the

ADGS1612. The ADGS1612 is an iCMOS, quad single-pole,

single-throw (SPST) switch controlled by a serial peripheral

interface (SPI). The SPI has robust error detection features. These

are cyclic redundancy check (CRC) error detection, invalid read/

write address detection, and serial clock (SCLK) count error

detection. It is possible to daisy-chain multiple ADGS1612 devices

together. This enables the configuration of multiple devices with a

minimal amount of digital lines. The ADGS1612 also supports

burst mode that decreases the time between SPI commands.

Figure 1 shows the EVAL-ADGS1612SDZ in a typical evaluation

setup. The EVAL-ADGS1612SDZ is controlled by the system

demonstration platform (SDP) which connects to a PC via a USB

port. The ADGS1612 is on the center of the evaluation board and

wire screw terminals are provided to connect to each of the

source and drain pins. Three screw terminals power the device

and a fourth terminal provides users with a defined digital logic

supply voltage, if required. Alternatively, the digital logic supply

voltage can be supplied from the SDP.

Full specifications on the ADGS1612 are available in the

ADGS1612 data sheet available from Analog Devices, Inc., and

should be consulted in conjunction with this user guide when

using the evaluation board.

The evaluation board interfaces to the USB port of a PC via the

SDP board. The EVAL-SDP-CB1Z board (SDP-B controller

board) is available to order on the Analog Devices website at

www.analog.com.

UG-1199 EVAL-ADGS1612SDZ User Guide

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TABLE OF CONTENTS

Features .............................................................................................. 1

Package Contents.............................................................................. 1

Documents Needed.......................................................................... 1

Equipment Needed........................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

ADGS1612 Evaluation Board Layout ............................................ 3

Evaluation Board Hardware ............................................................ 4

Power Supplies .............................................................................. 4

Input Signals.................................................................................. 4

Link Options ..................................................................................4

Evaluation Board Software...............................................................5

Installing the Software ..................................................................5

Initial Set Up ..................................................................................5

Block Diagram And Description.....................................................5

Memory Map .................................................................................6

Evaluation Board Schematics and Artwork...................................7

Ordering Information.................................................................... 11

Bill of Materials........................................................................... 11

REVISION HISTORY

1/2018—Revision 0: Initial Version

EVAL-ADGS1612SDZ User Guide UG-1199

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ADGS1612 EVALUATION BOARD LAYOUT

Figure 1.

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EVALUATION BOARD HARDWARE

POWER SUPPLIES

Connector J1 provides access to the supply pins of the ADGS1612.

VDD, GND, and VSS on J1 link to the corresponding pins on

the ADGS1612. For dual-supply voltages, the evaluation board

can be powered from ±3.3 V to ±8 V. For single-supply voltages,

the GND and VSS terminals must connect together and power the

evaluation board with 3.3 V to 16 V. Additionally, 3.3 V is supplied

to the VLpin of the ADGS1612 by the SDP when Link LK1 is in

Position B. When controlling the ADGS1612 by another method

other than the SDP, supply between 2.7 V and 5.5 V to the VLpin of

the ADGS1612 via the EXT_VL screw terminal input on J1.

LK1 must be in Position A.

INPUT SIGNALS

Two screw connectors, J2 and J3, are provided to connect to

both the source and drain pins of the ADGS1612. Additional

subminiature Version B (SMB) connector pads are available if

extra connections are required.

Each trace on the source and drain side includes two sets of

0603 pads, which can place a load on the signal path to ground.

A 0 Ω resistor is placed in the signal path and can be replaced

with a user defined value. The resistor, combined with the 0603

pads, can create a simple resistor-capacitor (RC) filter.

LINK OPTIONS

A number of link options are provided on the E VA L -

ADGS1612SDZ board that must be set for the required operating

conditions before using. Table 1 describes the positions of the

links to control the evaluation board via the SDP board using a

PC and external power supplies. The functions of these link

options are described in detail in Table 2.

When using the SDP in conjunction with the E VA L -

ADGS1612SDZ, LK1 must be in Position B to avoid damage to

the SDP.

Table 1. Link Options for SDP Control (Default)

Link Number Option

LK1

LK2 B

Table 2. Link Functions

Link Number Function

LK1 This link selects the source of the VLvoltage supplied to the ADGS1612.

Position A selects EXT_VL from J1.

Position B selects 3.3 V from the SDP.

LK2 This link selects the source of the digital input of the ADG819 which is used to perform a hardware reset of the ADGS1612.

Position A indicates the SW1 push button performs a hardware reset.

Position B indicates the SDP can perform a hardware reset.

EVAL-ADGS1612SDZ User Guide UG-1199

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EVALUATION BOARD SOFTWARE

INSTALLING THE SOFTWARE

The EVAL-ADGS1612SDZ evaluation board uses the Analog

Devices Analysis Control Evaluation (ACE) software. ACE is a

desktop software application that allows the evaluation and

control of multiple evaluation systems.

The ACE installer installs the necessary SDP drivers and .NET

Framework 4 by default. Install ACE before connecting the SDP.

The ACE software and access to full instructions on how to

install and use ACE can be found on the Analog Devices

website.

After the installation is finished, the EVAL-ADGS1612SDZ

evaluation board plug-ins appear when opening ACE.

INITIAL SET UP

To set up the evaluation board, complete the following steps:

1. Connect the evaluation board to the SDP board and

connect the SDP board to the computer via a USB cable.

2. Power the evaluation board as described in the Power

Supplies section.

3. Run the ACE application. The EVAL-ADGS1612SDZ

board plug-ins appear in the attached hardware section of

the Start tab.

4. Double-click on the evaluation board plug-in to open the

evaluation board view seen in Figure 2.

5. The chip block diagram can be accessed by double-clicking

on the ADGS1612 chip (see Figure 2). This view provides a

basic representation of functionality of the evaluation board.

The main functions are labeled in Figure 3.

Figure 2. Evaluation Board View of the EVAL-ADGS1612SDZ

Figure 3. Chip Block Diagram View for the ADGS1612

BLOCK DIAGRAM AND DESCRIPTION

The EVAL-ADGS1612SDZ software is organized so that it

appears similar to the functional block diagram shown in the

data sheet. In this way, it is easy to correlate the functions on the

EVAL-ADGS1612SDZ board with the full description of each

block, register, and settings is given in the ADGS1612 data sheet.

Some of the blocks and their functions are described here as they

pertain to the evaluation board. The full screen block diagram,

shown in Figure 4, describes the functionality of each block.

Figure 4. EVAL-ADGS1612SDZ Block Diagram with Labels

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Table 3. Block Diagram Functions

Label Function

A The drop-down menus configure SW1 to SW4 as

open or closed.

B The INVALID RW ENABLE, SCLK COUNT ENABLE,

and CRC ENABLE checkboxes enable or disable the

error detection features on the SPI interface.

C The BURST MODE ENABLE checkbox enables or

disables burst mode.

The

RW ERROR FLAG

SCLK ERROR

, and

CRC

ERROR FLAG indicators illuminate red if flags assert

in the error flags register.

E The Clear Flags button clears the error flags register.

F Apply Changes button applies all modified values

to the devices.

Memory Map

All registers are fully accessible from the memory map tab; this

allows registers to be edited at a bit level (see Figure 5 and Figure 6).

The bits shaded in dark gray are read only bits and cannot be

accessed from ACE; all other bits are toggled. The Apply Changes

button transfers data to the device.

All changes here correspond to the block diagram; for example,

if the internal register bit is enabled, it displays as enabled on

the block diagram. Any bits or registers that are bold are

modified values that have not been transferred to the evaluation

board. After clicking Apply Changes, the data is transferred to

the evaluation board.

Figure 5. ADGS1612 Memory Map

Figure 6. ADGS1612 Memory Map with Unapplied Changes in the SW_DATA Register

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EVAL-ADGS1612SDZ User Guide UG-1199

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EVALUATION BOARD SCHEMATICS AND ARTWORK

Figure 7. EVAL-ADGS1612SDZ Schematic 1

Figure 8. EVAL-ADGS1612SDZ Schematic 2

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Figure 9. EVAL-ADGS1612SDZ Schematic 3

Figure 10. EVAL-ADGS1612SDZ Silk Screen

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Figure 11. EVAL-ADGS1612SDZ Top Layer

Figure 12. EVAL-ADGS1612SDZ Layer 2

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UG-1199 EVAL-ADGS1612SDZ User Guide

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Figure 13. EVAL-ADGS1612SDZ Layer 3

Figure 14. EVAL-ADGS1612SDZ Bottom Layer

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