Analog Devices ADP1974-EVALZ Manual de usuario

ADP1974-EVALZ User Guide

UG-883

One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com

Evaluating the ADP1974 Bidirectional Synchronous PWM Controller

for Battery Test and Formation

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.Rev. 0 | Page 1 of 12

FEATURES

Evaluation board for testing the features of the ADP1974

Standalone open-loop capability

FAULT and COMP inputs compatible with the AD8450-EVALZ

Compatible for testing with full external customer solutions

Input voltage range: 6 V to 60 V

On-board 5 V low dropout (LDO) regulator

Selective buck or boost mode

Adjustable frequency from 50 kHz to 300 kHz

Programmable dead time control

Synchronization output or input with adjustable phase shift

Programmable maximum duty cycle

Maximum internal duty cycle: 97%

Programmable soft start

Peak hiccup current limit protection

Input voltage undervoltage lockout (UVLO) protection

Jumper for enable/shutdown control

EVALUATION KIT CONTENTS

ADP1974-EVALZ evaluation board

ADDITIONAL EQUIPMENT NEEDED

Power supplies

Digital multimeters

Oscilloscope

Signal generator

ONLINE RESOURCES

Documents

ADP1974 data sheet

ADP1974-EVALZ user guide

AD8450 data sheet

EngineerZone

Frequently asked questions (FAQs) and troubleshooting

GENERAL DESCRIPTION

The ADP1974-EVA L Z is an open-loop evaluation board that

can be used to test the features of the ADP1974. The ADP1974

is a constant frequency, voltage mode, bidirectional synchro-

nous pulse-width modulation (PWM) controller for buck or

boost, dc-to-dc, battery charge and discharge applications.

When connected to external, high voltage field effect transistors

(FET); a half bridge driver; and an external control device, such as

the AD8450-E VA L Z , the ADP1974-EVA L Z can be used to

evaluate the ADP1974 in a complete closed-loop application.

This user guide includes input/output descriptions, setup

instructions, the schematic, and the printed circuit board (PCB)

layout drawings for the ADP1974-E VA L Z evaluation board.

The ADP1974-EVA L Z can be used to test internal features such

as precision enable, pin selective battery charge or recycle mode

operation, internal and external frequency synchronization

control with programmable phase shift, PWM duty cycle control,

programmable maximum duty cycle, programmable dead time,

and programmable peak hiccup current limit. Additional

protection features that can be evaluated include soft start,

input voltage undervoltage lockout (UVLO), fault signaling,

and thermal shutdown (TSD).

Complete specifications for the ADP1974 are available in the

ADP1974 data sheet, which should be consulted in conjunction

with this user guide when using the evaluation board.

UG-883 ADP1974-EVALZ User Guide

Rev. 0 | Page 2 of 12

TABLE OF CONTENTS

Features .............................................................................................. 1

Evaluation Kit Contents................................................................... 1

Additional Equipment Needed....................................................... 1

Online Resources.............................................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Typical Setup for Open-Loop Evaluation...................................... 3

Evaluation Board Setup Procedures............................................... 4

Quick Start Steps .......................................................................... 4

Adjusting the ADP1974-EVALZ Components for a Specific

Application .................................................................................... 5

Application Specific ADP1974 Control .....................................7

Evaluation Board Hardware.............................................................8

Typical Application Circuit..........................................................8

Evaluation Board Schematic and Layout........................................9

Schematic........................................................................................9

PCB Layout ................................................................................. 10

Ordering Information.................................................................... 11

Bill of Materials........................................................................... 11

Related Links................................................................................... 11

REVISION HISTORY

10/15—Revision 0: Initial Version

ADP1974-EVALZ User Guide UG-883

Rev. 0 | Page 3 of 12

TYPICAL SETUP FOR OPEN-LOOP EVALUATION

OSCILLOSCOPE

MULTIMETER

USE JUMPERS TO CONFIGURE

EN AND MODE OR

CONNECT EXTERNALPOWER

SUPPLIES TO CENTER PINS

GROUND CONNECTION FOR

EXTERNAL EQUIPMENT

AND SYSTEM GROUND

POWER SUPPLY

= 6V TO 60V

POWER SUPPLY

FAULT

= 6V TO 60V POWER SUPPLY

COMP

= 0V TO 5V

GROUND CONNECTION

FOR EXTERNALEQUIPMENT

AND SYSTEM GROUND

13517-001

CONNECT AN OSCILLOSCOPE

IF SYNC IS CONFIGURED

AS AN OUTPUT

CONNECT TO AN EXTERNAL

CLOCK SIGNALFOR SYNCHRONIZATION

IF SYNC IS CONFIGUREDAS AN OUTPUT

SELECT R

FOR A DESIRED CURRENT LIMIT

OR CONNECT CL TO GND FOR EVALUATION

Figure 1.

UG-883 ADP1974-EVALZ User Guide

Rev. 0 | Page 4 of 12

EVALUATION BOARD SETUP PROCEDURES

The ADP1974-EVA L Z has many features that are customizable

via the resistors and capacitors on the evaluation board. Other

features are observable by adjusting the voltages applied to several

of the pins. Most features can be initially observed without making

any physical changes to the board, with the exception of RS. If

no RSis added, CL must be shorted to GND for most tests. If

testing the current-limit functionality, RSmust be mounted to

the evaluation board. The steps in the following sections describe

how to use the ADP1974-E VA L Z evaluation board.

QUICK START STEPS

To begin using the evaluation board, connect the external

equipment as described in the following sections.

GNDx Test Loop

The GND1 and GND2 test loops are the power ground

connection for the device via the GND pin and the external

bypass capacitors. Connect the ground connections from the

external equipment to this bus.

VIN Test Loop

Connect an external power supply from to VIN to GND1 or

GND2. The VIN test loop connects the positive input supply

voltage to the VIN pin. Connect the power supply to this bus

and keep the wires as short as possible to minimize the EMI

transmission.

EN Test Bus

The EN test bus is used to enable/disable the ADP1974 via

the EN pin. Use one of the following methods to control the

ADP1974. Do not leave the EN pin floating.

•Use a jumper to connect the top two pins of the EN test

bus. This jumper connects EN to VIN and enables the

ADP1974 (see Figure 2).

PLACE

JUMPER

HERE

13517-002

Figure 2. Enabled Jumper Position

•Use a jumper to connect the bottom two pins of the EN test

bus. This jumper connects EN to GND and disables the

ADP1974 (see Figure 3).

PLACE

JUMPER

HERE

13517-003

Figure 3. Disabled Jumper Position

•Alternatively, connect a voltage between 0 V and 60 V to

the center pin of the EN test bus for independent control of

the EN pin voltage (see Figure 4). The ADP1974 is enabled

when VEN ≥ 1.25 V (typical).

CONNECT

EXTERNAL

SIGNAL

HERE

13517-004

Figure 4. EN Pin Direct Connection

VREG Test Point

Connect a multimeter from VREG to GNDx. When VEN ≥

1.25 V (typical), VREG rises to 5 V (typical).

MODE Test Bus

The MODE test bus is used to set the ADP1974 in buck or

boost mode. Do not leave the MODE pin floating.

The state of the MODE pin can only be changed when the

ADP1974 is disabled via the EN pin or disabled due to a fault

condition.

•Use a jumper to connect the top two pins of the MODE

bus. This jumper connects MODE to VREG and places

the ADP1974 in buck/charge mode (see Figure 5).

PLACE

JUMPER

HERE

13517-005

Figure 5. Enabled Jumper Position

•Use a jumper to connect the bottom two pins of the MODE

test bus. This jumper connects MODE to GND and places

the ADP1974 in boost/recycle mode (see Figure 6).

PLACE

JUMPER

HERE

13517-006

Figure 6. Disabled Jumper Position

•Alternatively, connect a voltage between 0 V and 5.5 V

to the center pin of the MODE test bus for independent

control of the MODE pin voltage (see Figure 7). The

MODE pin is logic high when VMODE ≥ 1.20 V (typical).

CONNECT

EXTERNAL

SIGNAL

HERE

13517-007

Figure 7. MODE Pin Direct Connection

ADP1974-EVALZ User Guide UG-883

Rev. 0 | Page 5 of 12

FAULT Test Point

Connect FAULT to VIN or apply an external voltage between 0 V

and 60 V. If SYNC is configured as an output, when VFAULT ≥ 1.2 V

(typical), a square wave is visible on the SYNC pin operating at

the frequency set by RFREQ.

SYNC Test Point

If SYNC is configured as an output, connect an oscilloscope to

SYNC. The SYNC signal is visible when VEN ≥ 1.25 V (typical)

and VFAULT ≥ 1.2 V (typical).

If SYNC is configured as an input, connect a signal with fSW

between 50 kHz and 300 kHz, with VSYNC(HIGH) ≥ 1.2 V (typical)

and VSYNC(LOW) ≤ 1.05 V (typical).

COMP Test Point

Connect an external power supply to COMP. See Figure 8 for

the relationship between VCOMP and the switching duty cycle of

DH and DL.

100

00.5 5.0

4.54.03.53.02.52.01.51.0

DUTY CYCLE (%)

VCOMP (V)

13517-008

TA= 25°C

Figure 8. Duty Cycle vs. VCOMP, RFREQ = 100 kΩ, No Load on DL, DH, or DMAX

DL and DH Test Point

Connect the DH and DL pins to an oscilloscope. To observe a

signal on DH or DL, enable the ADP1974 via the EN pin by

setting VEN ≥ 1.25 V (typical), VFAULT ≥ 1.2 V (typical), and

VCOMP ≥ 0.5 V (typical).

If VMODE ≤ 1.05 V (typical), the ADP1974 is in boost/recycle

mode, and a square wave is visible on the DL pin. A

complementary square wave is visible on the DH pin.

0.5V

4.5V

2.5V

BOOST MODE CONFIGURATION

MODE ≤ 1.05V (TYPICAL)

SCFG

≥ 4.53V (TYPICAL)

COMP

INTERNAL RAMP

(4V p-p)

VREG (5V TYPICAL)

13517-009

Figure 9. Signal Diagram for Boost Configuration

If VMODE ≥ 1.20 V (typical), the ADP1974 is in buck/charge

mode, and a square wave is visible on the DH pin. A

complementary square wave is visible on the DL pin.

BUCK MODE CONFIGURATION

MODE ≥ 1.20V (TYPICAL)

SCFG

≥ 4.53V (TYPICAL)

13517-010

0.5V

4.5V

COMP

INTERNAL RAMP

(4V p-p)

VREG (5V TYPICAL)

2.5V

Figure 10. Signal Diagram for Buck Configuration

CL Test Point

Unless testing the current limit, connect CL to GND1 or GND2.

If testing the current, see the ADP1974 data sheet for more infor-

mation about current limits and selecting RSto set the current limit.

ADJUSTING THE ADP1974-EVALZ COMPONENTS

FOR A SPECIFIC APPLICATION

For more detailed guidance in selecting the components to

customize the features of the ADP1974, consult the ADP1974

data sheet.

Selecting RFREQ for a Master Device

When VSCFG is ≥ 4.53 V, the ADP1974 operates as a master device.

When functioning as a master device, the ADP1974 operates at

the frequency set by the external RFREQ resistor connected

between FREQ and ground, and the ADP1974 outputs a clock

at the programmed frequency on the SYNC pin.

UG-883 ADP1974-EVALZ User Guide

Rev. 0 | Page 6 of 12

Figure 11 shows the relationship between the RFREQ (MASTER) value

and the programmed switching frequency.

210

110

130

150

170

190

50 100 150 200 250 300

RFREQ (MASTER) (kΩ)

SET (kHz)

13517-011

Figure 11. RFREQ (MASTER) vs. Switching Frequency (fSET)

To calculate the RFREQ (MASTER) value for a desired master clock

synchronization frequency, use the following equation:

( )

(kHz)

kΩ

)(

SET

MASTERFREQ f

(1)

where:

RFREQ (MASTER)is the resistor in kΩ to set the frequency for master

devices.

fSET is the switching frequency in kHz.

Selecting RFREQ for a Slave Device

To configure the ADP1974 as a slave device, drive VSCFG < 4.53 V.

When functioning as a slave device, the ADP1974 operates at

the frequency of the external clock applied to the SYNC pin. To

ensure proper synchronization, select RFREQ to set the frequency

to a value slightly slower than that of the master clock by using

the following equation:

RFREQ (SLAVE) = 1.11 × RFREQ (MASTER) (2)

where:

RFREQ (SLAVE) is the resistor value that appropriately scales the

frequency for the slave device, and 1.11 is the RFREQ slave to

master ratio for synchronization.

RFREQ (MASTER) is the resistor value that corresponds to the

frequency of the master clock applied to the SYNC pin.

The frequency of the slave device is set to a frequency slightly

lower than that of the master device to allow the digital

synchronization loop of the ADP1974 to synchronize to the

master clock period. The slave device can synchronize to a

master clock frequency running between 2% to 20% higher

than the slave clock frequency. Setting RFRE Q ( S LAVE) to 1.11× larger

than RFREQ (MASTER) runs the synchronization loop in approximately

the center of the adjustment range.

Phase Shift Resistor (RSCFG)

If a phase shift from SYNC to DH and DL is desired, select RSCFG

for the desired time delay using Figure 12 as reference.

450

400

350

300

250

200

150

100

007.54.5 6.03.01.5

RSCFG (kΩ)

DELAY (µs)

13514-012

Figure 12. RSCFG vs. Phase Delay, RFREQ = 100 kΩ

Programming the Dead Time (RDT)

To adjust the dead time on the synchronous DH and DL

outputs, connect a resistor (RDT) from DT to GND and bypass

with a 47 pF capacitor. Select RDT for a given dead time using

Figure 13 or calculate RDT using the following equations. To

reach a single equation for RDT, combine the equations for VDT

and RDT.

( )

3.76

28.51ns

V−×

=DEAD

(3)

(4)

where:

VDT is the DT pin programming voltage.

IDT is 20 µA, typical internal current source.

tDEAD is the desired dead time in ns.

RDT is the resistor value in kΩ for the desired dead time.

To calculate RDT for a given tDEAD, the resulting equation used is

( )

3.76

28.51ns

kΩ −

=DEAD

(5)

13517-013

RDT (kΩ)

DEAD (ns)

100

125

150

175

0100 200 300 400 500 600 700

Figure 13. DT Pin Resistance (RDT) vs. Dead Time (tDEAD)

ADP1974-EVALZ User Guide UG-883

Rev. 0 | Page 7 of 12

Maximum Duty Cycle Resistor (RDMAX)

To customize the maximum duty cycle of the DH and DL pins

for the ADP1974, use Figure 14 to select RDMAX.

450

100

150

200

250

300

400

350

020 40 60 80 100

DMAX

(kΩ)

DUTY CYCLE (%)

= +25°C

13517-014

Figure 14. RDMAX vs. Duty Cycle, RFREQ = 100 kΩ, VCOMP = 5 V

Current-Limit Set Resistor (RS)

If testing the current limit in an application, use the following

equation to set the current limit:

( )

PK R

ImV100

mA =

(6)

where:

IPK is the desired peak current limit in mA.

RSis the sense resistor used to set the peak current limit in Ω.

When the ADP1974 is configured to operate in buck (charge)

mode, the internal current-limit threshold is set to 300 mV

(typical) and the negative valley current-limit threshold is set to

450 mV (typical). When the ADP1974 is configured to operate

in boost (recycle) mode, the internal current-limit threshold is

set to 500 mV (typical). The external resistor (RCL) is needed to

offset the current properly to detect the peak in both buck and

boost operation. Set the RCL value to 20 kΩ. In operation, the

equations for setting the peak currents follow.

For buck/charge mode, the equations are

VCL (BUCK) = (ICL) × (RCL) − (IPK) × (RS) (7)

VNC (BUCK) = (ICL) × (RCL) + (IVL(NEG)) × (RS) (8)

For boost/recycle mode, the equation is

VCL (BOOST) = (ICL) × (RCL) + (IPK) × (RS) (9)

where:

VCL (BUCK) = 300 mV typical.

VNC (BUCK) = 450 mV typical.

VCL (BOOST) = 500 mV typical.

IPK = peak inductor current.

IVL(NEG) = valley inductor current.

ICL = 20 µA, typical.

RCL = 20 kΩ.

The ADP1974 is designed so that the peak current limit is the same

in both the buck mode and boost mode of operation. A tolerance

of 1% or better for the RCL and RSresistors is recommended.

Soft Start Capacitor (CSS)

The ADP1974-EVA L Z comes with a 1 nF capacitor on the

evaluation board.

A CSS capacitor is not required for the ADP1974. When the CSS

capacitor is not used, the internal 5 µA (typical) current source

pulls the SS pin voltage to VREG, and there is no soft start control.

Use the following equation to calculate the delay time before

switching is enabled (tREG):

REG

t×= 0.52

(10)

where:

ISS = 5 µA, typical.

CSS = soft start capacitor value.

During soft start, the ADP1974 operates in asynchronous

mode, and the synchronous FET is not driven. After the soft

start period is completed (SS > 4.5 V), the ADP1974 switches to

full synchronous mode.

VREG

4.5V

VOUT

0.52V

ENABLE

ADP1974 BEGIN

REGULATION

SYNCHRONOUS

OPERATION

REG

13517-015

Figure 15. Soft Start Diagram

APPLICATION SPECIFIC ADP1974 CONTROL

When integrated in a battery test solution, the ADP1974 can be

controlled with external control signals from other devices in the

application. The FAULT pin allows an external device to signal

the ADP1974 when an external fault occurs. The COMP pin

allows an external device to control the PWM output signals on

the DH and DL pins. The SYNC and SCFG pins can be used to

synchronize the ADP1974 to an external clock signal or to

implement the ADP1974 as a master clock. The EN and MODE

pins provide logic control to turn the ADP1974 on or off and

to transition the system between boost/recycle mode and

buck/charge mode.

UG-883 ADP1974-EVALZ User Guide

Rev. 0 | Page 8 of 12

EVALUATION BOARD HARDWARE

TYPICAL APPLICATION CIRCUIT

GND

24V RECYLCING

DC BUS

VIN

24V

COMP

FAULT

MODE

FROM

CENTRAL PC

FROM

ANALOG IC

ADP1974

VREG

FREQ

SYNC

DMAX

SCFG

MOSFET

DRIVER

BATTERY

13517-016

Figure 16. ADP1974 Typical Application Circuit

Table 1. Input Pins that Require External Power Supplies or External Control Signals

Power Supply Connector Voltage Range (V) Purpose

VIN1 VIN 6 to 60 Supplies power to the ADP1974 internal control circuitry.

VEN1EN 0 to 60 Supplies logic signal to enable operation of the ADP1974.

VMODE1MODE 0 to 5.5 Supplies logic signal to select boost/recycle mode or buck/charge mode.

VFAULT2FAULT 0 to 60 Supplies the signal to indicate when a fault condition has occurred in the application

external to the ADP1974.

VCOMP3COMP 0.5 to 5.0 Supplies the error signal that is compared internally to the liner ramp to produce the

PWM signal.

VSYNC SYNC 0 to 5.5 Supplies the external synchronization waveform when the ADP1974 is a slave device,

and SYNC is configured as an input.

1VIN can also be used to supply VEN and VMODE via jumper connections. Alternatively, EN and MODE can be powered with separate power supplies.

2When used with the AD8450, the FAULT signal is supplied by the FAULT pin (Pin 46) of the AD8450.

3When used with the AD8450, the COMP signal is supplied by the VCTRL pin (Pin 59), the error amplifier output of the AD8450.

Table 2. Output Pins to Observe with Ammeter or Oscilloscope

Output

Signal Connector Signal

Recommended

Equipment Expected Measurement

VVREG1 VREG 5 V dc Ammeter or oscilloscope When VIN > 6 V, VVREG rises to 5 V.

VDL DL 0 V to VREG square wave Oscilloscope When MODE is logic low, a square wave is visible on DH.

When MODE is logic high, DL is complementary to DH.

VDH DH 0 V to VREG square wave Oscilloscope When MODE is logic high, a square wave is visible on DL.

When MODE is logic low, DH is complementary to DL.

VSYNC SYNC 0 V to VREG square wave Oscilloscope When SYNC is configured as an output, the SYNC pin outputs a

clock signal programmed by RFREQ.

ICL CL Magnitude dependent

on RStriangle wave

Oscilloscope The current rises and falls with the duty cycle of DH and DL.

1VVREG provides the logic high signal for the MODE pin when a jumper is placed on the top two pins of the MODE test bus.

ADP1974-EVALZ User Guide UG-883

Rev. 0 | Page 9 of 12

EVALUATION BOARD SCHEMATIC AND LAYOUT

SCHEMATIC

VREG

SYNC

VREG

VIN

MODE

SYNC

FAULT

SCFG

FREQ

DMAX

COMP

GND

DLR

DHR

VIN

MODE

ADP1974

SYNC

FAULT COMP

VIN1

DMAX

FREQ

SCFG

VIN2

13517-017

Figure 17. ADP1974 Evaluation Board Schematic

UG-883 ADP1974-EVALZ User Guide

Rev. 0 | Page 10 of 12

PCB LAYOUT

13514-016

13517-018

Figure 18. ADP1974 Evaluation Board PCB Top Layer

13517-019

Figure 19. ADP1974 Evaluation Board PCB Inner Layer 2

13517-020

Figure 20. ADP1974 Evaluation Board PCB Inner Layer 1

13517-021

Figure 21. ADP1974 Evaluation Board PCB Bottom Layer

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