Analog Devices EVAL-SSM3525Z Manual de usuario

EVAL-SSM3525Z User Guide

UG-1183

One Technology Way •P. O . Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com

Evaluating the SSM3525 30 W,Filterless,Class-D,Output Sensing Audio Amplifier

Rev. 0 | Page 1 of 16

FEATURES

15.3 W into 4 Ω at 12 V with a 1% THD + N

EVALUATION KIT CONTENTS

USBi USB interface board

USB cable

EVAL-SSM3525Z evaluation board

DOCUMENTS NEEDED

SSM3525 data sheet

EVAL-SSM3525Z user guide

DLL for SigmaStudio

GENERAL DESCRIPTION

The E VA L -SSM3525Z is an evaluation board for the SSM3525,

which is an integrated mono 30 W, high efficiency, stereo Class-D

audio amplifier with digital input. The application circuit requires a

few external components and can operate from a single 4.5 V to

17 V supply. It is capable of delivering 15.3 W of continuous output

power into a 4 Ω load from a 12 V power supply, with <1% total

harmonic distortion plus noise (THD + N).

The SSM3525 features a high efficiency, low noise modulation

scheme that requires no external inductor/capacitor (LC) output

filters. This scheme continues to provide high efficiency even at

low output power.

The SSM3525 operates with 92.1% efficiency at 9 W into an 8 Ω

load, and it has a typical output noise voltage of 37.5 µV rms,

A weighted.

This user guide describes how to configure and use the E VA L -

SSM3525Z evaluation board. Read this user guide in conjunction

with the SSM3525 data sheet, which provides specifications,

internal block diagrams, register map, and application guidance

for the amplifier IC.

Figure 1 shows the top view of the evaluation board, and Figure 2

shows the bottom view of the evaluation board.

EVALUATION BOARD PHOTOGRAPHS

16199-001

Figure 1. SSM3525 Evaluation Board Top View

16199-002

Figure 2. SSM3525 Evaluation Board Bottom View

UG-1183 EVAL-SSM3525Z User Guide

Rev. 0 | Page 2 of 16

TABLE OF CONTENTS

Features .............................................................................................. 1

Evaluation Kit Contents................................................................... 1

Documents Needed.......................................................................... 1

General Description ......................................................................... 1

Evaluation Board Photographs ....................................................... 1

Revision History ............................................................................... 2

Setting Up the Hardware ................................................................. 3

Input Configuration ..................................................................... 3

Control Port .................................................................................. 3

Output Configuration.................................................................. 3

Power Supply Configuration........................................................4

Edge Mode......................................................................................4

Component Selection ...................................................................4

Getting Started...................................................................................5

Suggested System Level and Audio Tests ...................................5

Evaluation Board Schematics and Artwork...................................6

Ordering Information.................................................................... 14

Bill of Materials........................................................................... 14

REVISION HISTORY

1/2018—Revision 0: Initial Version

EVAL-SSM3525Z User Guide UG-1183

Rev. 0 | Page 3 of 16

SETTING UP THE HARDWARE

INPUT CONFIGURATION

There are several ways to source audio to the SSM3525 on the

E VA L-SSM3525Z evaluation board. The evaluation board can

accept direct inter-IC sound/time division multiplexed (I2S/TDM)

data or it can convert from Sony/Philips Digital Interface (S/PDIF)/

optical digital audio data to I2S using an on-board digital audio

receiver, U6. The E VA L-SSM3525Z can also accept a SoundWire®

interface.

Use the 3 × 3 way header (J10) to make a connection from either

the on-board S/PDIF audio receiver circuitry or the external digital

audio signals to the SSM3525 device pins. The EVA L -SSM3525Z

comes set with three jumpers set for receiving the S/PDIF audio

data. The logic level for the inputs at J10 is 3.3 V.

To use the external I2S/TDM data, the three jumpers must be

removed, and the signal source (FSYNC, BCLK, and SDATA) must

be connected to the J10 center pins.

If the user does not have a direct I2S or TDM source, the on-board

digital audio receiver can accept S/PDIF data from a digital audio

source, such as the digital audio output of a CD player. In this case,

select either optical or coaxial using the S2 switch to properly

connect the desired input to the digital audio receiver.

The voltage/current sense, analog-to-digital converter (ADC)

output data is available at the J15 jumper at the IOVDD logic

level or at the J22 jumper at the 3.3 V logic level. Refer to the

SSM3525 data sheet for more information on placement options.

CONTROL PORT

The SSM3525 supports I2C control for setting the internal registers.

The J16 10-way header is used for connecting the external I2C

master for controlling the E VA L -SSM3525Z. The evaluation board

can be set for the desired I2C address by using two headers (JP9

and J25). The JP9 is used for setting the pull-up or pull-down to

the IOVDD and GND voltages on the printed circuit board (PCB),

whereas J25 can be used for bypassing the 47 kΩ resistor. Refer to

the SSM3525 data sheet for address selection options. Remove the

jumper across J25 to insert the 47 kΩ resistor in the signal path

for pull-up or pull-down operation. To properly float the

ADDR pin to a no connect state, do not insert jumpers on JP9

or J25. By default, the J25 is inserted, and JP9 is set so that the

ADDR pin is pulled to ground. Setting the ADDR pin to ground

sets the 7-bit device address to 0x24.

OUTPUT CONFIGURATION

The binding post output terminals (OUT+ and OUT−) provide

an option to connect the speaker with standard banana connectors.

In addition, 2-pin, 0.100-inch headers (J6 and J9) are provided

as alternate option.

To reduce the system radiated emission, especially if the speaker

cable length exceeds 20 cm, it may be necessary to include an

output filter. The recommended filter uses two ferrite beads (L2

and L3) and two capacitors (C1 and C2). See Figure 10 for more

details.

Note the addition of the ferrite beads other than the one used

on the evaluation board may affect the total harmonic distortion

(THD) and signal-to-noise ratio (SNR) performance as specified

in the SSM3525 data sheet. For best performance, the Murata

output ferrite beads in Table 1 are recommended.

Table 1. Recommended Output Ferrite Beads

Part No. Manufacturer1

Impedance (Z)

(Ω at 100 MHz)

Maximum

Current (IMAX) (mA)

Direct Conversion

Receiver (DCR) (Ω) Size (mm)

NFZ2MSM101SN10 Murata Manufacturing Co. 100 4000 0.014 2.0 ×

1.6 × 0.9

NFZ2MSM181SN10

Murata Manufacturing Co.

180

3400

0.020

2.0 ×

1.6 × 0.9

NFZ2MSM301SN10 Murata Manufacturing Co. 300 3100 0.024 2.0 ×

1.6 × 0.9

1Contact Murata Manufacturing Co. for further options.

UG-1183 EVAL-SSM3525Z User Guide

Rev. 0 | Page 4 of 16

POWER SUPPLY CONFIGURATION

The binding posts, J5 (PVDD) and J4 (GND), provide the power

supply to the evaluation board. Care must be taken to connect

the dc power with the correct polarity and voltage. Reverse polarity

or overvoltage can damage the E VA L -SSM3525Z permanently.

Permissible supply voltages range from 4.5 V to 17 V; higher

voltages may damage the amplifier. In addition, use an appropriate

current rated power supply to the evaluation board. Typically, a

5 A rating supply is recommended if using 4 Ω speakers and 12 V.

The E VA L-SSM3525Z has an option to generate the 5 V (AVDD),

3.3 V, 1.8 V, and 1.2 V from the PVDD supply. These voltages

are generated using the linear regulators on the evaluation

board: U3 for 5 V, U2 for 3.3 V, U4 for 1.8 V, and U5 for 1.2 V.

The 5 V and 3.3 V regulators can be turned off using Jumper

JP11 for 5 V and Jumper JP10 for 3.3 V. T h e 3 . 3 V regulator is used

for the on-board S/PDIF digital audio receiver and I2C pull-up.

The 1.8 V/1.2 V must be provided as IOVDD to the SSM3525.

The 5 V (AVDD) can be provided externally or generated

internally by the SSM3525. By default, the evaluation board is set

up for generating the 5 V, 3.3 V, 1.8 V, and 1.2 V using on-board

regulators; however, only PVDD and IOVDD (1.8 V) are

supplied to the SSM3525, and 5 V (AVDD) is generated from

on-chip LDO. After power-up, the SSM3525 generates the

AVDD (5 V) from the on-chip regulator. The on-chip regulator

for AVDD can be enabled in Register 0x04 via I2C. By default,

the on-chip regulator is disabled. Jumper J23 is open, and

Jumper J17 must be fitted.

The J17 and J23 jumpers are provided to measure the IOVDD

and AVDD currents. If using the on-board regulators as a source

for the AVDD and IOVDD, Jumper J17 and Jumper J23 must be

fitted, and the on-chip AVDD regulator must be disabled in

EDGE MODE

To reduce the radiated emissions from the SSM3525 amplifier, an

edge rate control mode is available. Register 0x05, Bit2(EDGE)

controls the edge rate of the switching. To enable lowelectro-

magnetic interference (EMI) mode,set Bit 2 of Register 0x05 to 1.

To return to normal operation, set Bit 2 of Register 0x05 to 0.

COMPONENT SELECTION

Selecting the proper components is the key to achieving the

performance required at the cost budgeted.

Output Decoupling Capacitors

There are two output filter capacitors (C1 and C2) that work

with the L2 and L3 ferrite beads. Use small size (0603 or 0402),

multilayer ceramic capacitors of dielectric type X7R or COG

(NPO) materials. The recommended value is 220 pF.

Output Ferrites

If ferrite beads are preferred for EMI filtering at the output nodes,

Table 1 shows the recommended output ferrite beads to use to

avoid excessive noise induced by the nonlinear behavior of the

ferrite beads.

I2C CONECTOR FOR USBi

PVDDGND

RESET

SOUNDWIRE INTERFACE

5V REG ENABLE/DISABLE

3.3V REG ENABLE

OUTPUT

OPTICAL COAXIAL SELECTI2C SELECT

I2C PULL-UP SELECT

IOVDD SELECT

I2C DEVICE

ADDRESS SETTING

I2S SOUNDWIRE SELECT

SPDIF EXT I2S SELECT

16199-003

Figure 3. Board Settings for I2C to I2S Mode

EVAL-SSM3525Z User Guide UG-1183

Rev. 0 | Page 5 of 16

GETTING STARTED

To set up the amplifier to work in a simple single-supply

configuration for quick evaluation, follow these steps:

1. Download the SigmaStudio® software to the PC, and follow

the installation steps provided suitable for the PC.

2. Connect the USBi to the USB port on the PC and ensure

that the USB driver for the USBi board is installed.

3. Copy the provided SSM3525 DLL file to the C:\Program

files\Analog Devices folder on your PC.

4. After installing the SigmaStudio software, the SigmaStudio

icon appears on the desktop. Double click on the icon to

open the SigmaStudio project screen.

5. Start a new project by pulling the USBi and SSM3525 to

the Hardware Configuration tab.

6. Connect the USBi to the SSM3525 block on the Hardware

Configuration schematic. See Figure 4.

16199-005

Figure 4. Hardware Configuration Tab

7. Connect the 12 V power supply source to the E VA L -

SSM3525Z.

8. Connect the USBi to J16 on the evaluation board.

9. Select the digital audio source for the SDATAI, FSYNC,

and BCLK pins of the SSM3525. By default, the evaluation

board is set for the S/PDIF source. Connect the optical or

coaxial cable to the appropriate connector on the

evaluation board.

10. Ensure that the jumpers are inserted across all three rows

of JP10 to establish direct connection of the digital audio

signal lines to the inputs of the SSM3525. See Figure 3 for

setting the jumpers and switches.

11. Connect the speakers across OUT+ (J2) and OUT− (J3)

binding posts.

12. If using the on-board S/PDIF to I2S circuitry, press the S4

button to synchronize the audio signals, which resets the

digital audio receiver.

13. Click the IC-1SSM3525 tab. If you click the Read Info

button, the 35 appears in the Device ID 1 field, 25 appears

in the Device ID 2 field, and the die revision number

appears in the Revision field. See Figure 5.

14. Go to the Chip & DAC CTRL tab.

16199-006

Figure 5. Chip & DAC CTRL Tab

15. Click Wr i te A l l button.

16. Under Master Software Powerdown, select Normal

Operation. The SSM3525 then powers up with audio on

the output.

SUGGESTED SYSTEM LEVEL AND AUDIO TESTS

It is recommended that users test the following:

•SNR

•Output noise, ensuring that an A-weighted filter is used to

filter the output before reading the measurement meter

•Maximum output power

•Distortion

•Efficiency

UG-1183 EVAL-SSM3525Z User Guide

Rev. 0 | Page 6 of 16

EVALUATION BOARD SCHEMATICS AND ARTWORK

EXT SUPPLY

4.5V TO 17V PVDD INPUT

SPDIF_OUT

SPDIF_IN

USBi/ AARDVARK

SW-LNK

PSIA SCL_3525

SDA_3525

FSYNC_3525

SDATAI_3525

BCLK_3525

OUT–

OUT+

SDATAO_3525

SSM3525

SHEET-2

SDATAI_3525

FSYNC_3525

BCLK_3525

SDATAO_3525

SHEET-3

PVDD

+3V3

+5V

+5V_EXT

+3V3_EXT

IOVDD_EXT

IOVDD

POWER_SUPPLY

SHEET-4

OUT+

OUT–

OUTPUTS

SHEET-5

SDA_3525

SCL_3525

SHEET-6

16199-007

Figure 6. Schematic of the EVAL-SSM3525Z Evaluation Board Block Diagram

EVAL-SSM3525Z User Guide UG-1183

Rev. 0 | Page 7 of 16

C26

0.10µF

J17

TP28

TP27

TP24

TP5 TP4

C13

10µF

C31

0.22µF

C33

0.22µF

C15

0.10µF

C43

10pF C44

10pF C45

10pF

BST–

OUT–

PVDD

OUT+

BST+

B1 PGND

OUT–

PVDD

OUT+

B5 PGND

C1 PGND C3

PVDD

C5 PGND

VREG/AVDD

D2 AGND

D3 ADDR

IOVDD

D5 FSYNC

E1 SCL

E2 SDA

E3 SDATAI

E4 SDATAO

E5 BCLK

SSM3525

R31

49.9Ω

C46

10pF

2J23

2-Jumper

TP14

TP18

R44

47kΩ

J25

A B

JP9

C39

10nF C40

10nF

C29

10µF

C17

10µF

C19

0.10µF

TP3

TP9

IOVDD

AVDD_3525

PVDD

SCL_3525

SDA_3525

FSYNC_3525

SDATAI_3525

BCLK_3525

OUT–

OUT+

ADDR

SDATAO_3525

BCLK_3525

FSYNC_3525

SDATAI_3525

IOVDD_3525

+5V

ADDR

SCL_3525

SDA_3525

IOVDD

16199-008

Figure 7. Schematic of the EVAL-SSM3525Z Evaluation Board SSM3525 Section

UG-1183 EVAL-SSM3525Z User Guide

Rev. 0 | Page 8 of 16

HIGH

NORM

OFF

RERR

NVERR

ERRORSEMPH

PH DET RATE

MASTER

SLAVE

SERIAL PORT CONTROL

128xFs

256xFs

RMCK Freq

SERIAL PORT FORMAT

SFSEL [1:0]

00 = LJ 24BIT

01 = I2S 24BIT

10 = RJ 24BIT

11 = DIRECT AES

SFSEL1 SFSEL0

RESET SPDIF

COAX IN

PSIA IN

ADD SPDIFTX TO SEND THE IV DATA

SOUNDWIRE INTERFACE

PDM LR SEL

0.10µF

TP41

GND

DVDD

OUT

TORX147L(FT)

C23

10nF

C25

10nF

C27

0.10µF

C28

0.10µF

600Ω

AT 100 MHz

600Ω

AT 100 MHz

600Ω AT 100 MHz

C18

0.10µF

4RXP0

5RXN

8FILT

6VA 23

SDOUT 28

OLRCK 27

OSCLK 24

RMCK

10 RXSEL1

11 RXSEL0

12 TXSEL1

13 TXSEL0

C18

U17

RCBL 14

NV/RERR 15

AUDIO

3RXP1

2RXP2

1RXP3

96KHZ

9RST

OMCK

AGND 22

DGND

CS8416_SPDIF_RX

C35

22nF

C36

1.0nF

R14

3kΩ1

C30

0.10µF

R12

47kΩ

R15

49.9Ω

R13 49.9Ω

R16 49.9Ω

R11 49.9Ω

C34

47µF

J13

75Ω

R18

10kΩ

JP6

C38

0.10µF

3S2

SPDT_SLIDE_EG1218

DEFAULT R25 DEFAULT R21 DEFAULT

R22

DEFAULT R20

DEFAULT

R24

DEFAULT R23

DEFAULT R19

J19 1

2GND

OUTPUT

4VDD

JP7

R26

47kΩ

MTH1

MTH2

MTH3

MTH4

J10

HEADER_3X3_9WAY_UNSHROUD

C41

0.10µF

VCC

3MR

GND

2RESET

ADM811TARTZ

100kΩ

1 2

3 4

5 6

7 8

910

11 12

13 14

15 16

J11

HEADER_16WAY_POL

J15

VCCA

VCCB

3A4

2GND

5DIR

U10

74AVC1T45

C14

0.10µF C16

0.10µF

R17

47kΩ

R32

DO NOT FIT

VCCA

VCCB

3A4

2GND

5DIR

U9A

74AVC1T45

C32

0.10µF

C37

0.10µF

R33

47kΩ

R34

DO NOT FIT

VCCA

VCCB

3A4

2GND

5DIR

U11

74AVC1T45

C47

0.10µF C48

0.10µF

R35

47kΩ

R36

DO NOT FIT

VCCA

VCCB

3A4

2GND

5DIR

U12

74AVC1T45

C49

0.10µF

C50

0.10µF

R37

DO NOT FIT

R38

47kΩ

1 2

3 4

5 6

7 8

910

11 12

13 14

15 16

HEADER_16WAY_UNSHROUD

2 3

SPST_HALF-PITCH_2SEC_SMD

R1 47kΩ

R2 47kΩ

C54

0.10µF

47kΩ

J18

J21

J22

TP8 TP7 TP6

TP11

J28

J29

J30

+3.3V

SDATAI_3.3V

FSYNC_3.3V

BCLK_3.3V

8416_MCLK

+3.3V +3.3V

+3.3V

8416_FYNC

8416_RMCK

SPDIF_COAX

SPDIF_OPT

+3.3V

OMCK_IN

8416_FYNC

8416_SDATA

8416_BCLK

RESET_SPDIF

MASTER_RESET

+3.3V

SDATAO_3525

+3.3V

SDATAI_3.3V SDATAI_IOVDD

+3.3V IOVDD

+3.3V

FSYNC_3.3V FSYNC_IOVDD

+3.3V IOVDD

+3.3V

BCLK_3.3V BCLK_IOVDD

+3.3V IOVDD

+3.3V

SDATAO_IOVDD

+3.3V IOVDD

BCLK_3525

FSYNC_3525

SDATAI_3525

SDATAO_3525

SDATAO_IOVDD

SDATAI_IOVDD

FSYNC_IOVDD

BCLK_IOVDD

IOVDD

SDATAO_3.3V

SW_CLK

SW_DATA

SDATAI_SW

SW_DATA

SW_CLK

FSYNC_SW

BCLK_HDR

FSYNC_HDR

SDATAI_HDR

16199-009

Figure 8. Schematic of the EVAL-SSM3525Z Evaluation Board I2C Digital Input Section

EVAL-SSM3525Z User Guide UG-1183

Rev. 0 | Page 9 of 16

TO SSM3525 AVDD

TO CS8416

TO SSM3525/LEVEL TRANSLATORS

C22

10µF

C21

1.0µF C9

1.0µF

OUT

7IN

8IN

4GND

6SD

ADP3335ARMZ-3.3-RL-LFCSP C11

1.0nF

C10

1.0µF C20

1.0µF

OUT

7IN

8IN

4GND

6SD

ADP3335ARMZ-1.8-RL-LFCSP C24

1.0nF

475Ω

A B

JP1

J14

J24

A B

JP2

J12

VOUT

SENSE

3GND

5EN/UVLO

6GND

8VIN

9EP

ADP7102-5.0V_LFCSP8

0.10µF

C12

1.0µF

100kΩ

TP13

TP15

TP16

TP17

TP19

TP33

TP35

TP36

+C6

+C5

470µF

A B

JP10

A B

JP11

3EN

GND

1IN 5

OUT

BYP

ADP1713AUJZ-1.2-R7

1.0µF C42

1.0µF

C53

10nF

1 2

3 4

5 6

J26

HEADER_6WAY_UNSHROUD

J27

3.3V_REG

+1.8V

PVDD

+3.3V

+5V

+5V_EXT

+3.3V_EXT

+5V_REG

IOVDD_EXT

PVDD_IN

IOVDD

+1.8V

+1.2V

IOVDD_EXT

16199-010

Figure 9. Schematic of the EVAL-SSM3525Z Evaluation Board Power Supply Section

UG-1183 EVAL-SSM3525Z User Guide

Rev. 0 | Page 10 of 16

OUTPUT

OUT–

OUT+

OUT–

OUT+

16199-011

Figure 10. Schematic of the EVAL-SSM3525Z Evaluation Board Output Section

USBi OR AARDVARK I

C INTERFACE

C/SA MODE SELECT

DOUBLE PULL, DOUBLE THROW SLIDE

J16

R39R40

2.43kΩ2.43kΩ

J20

C51

0.10µF

SPST_HALF-PITCH_2SEC_SMD

R41

47kΩ

R42

TP1

TP2

C52

0.10µF

SCL_3525

+3.3V

SDA_3525

USB_IO

IOVDD

SA_SDA

USB_SDA

SA_SCL

USB_SCL

16199-012

Figure 11. Schematic of the EVAL-SSM3525Z Evaluation Board I2C Section

16199-013

Figure 12. EVAL-SSM3525Z Evaluation Board Top Layer Copper

Tabla de contenidos

Otros manuales de Placa madre de Analog Devices

Analog Devices

Analog Devices SigmaDSP EVAL-AD1940MINIB Manual de instrucciones

Analog Devices

Analog Devices ADuCM350 Manual de usuario

Analog Devices

Analog Devices UG-396 Manual de usuario

Analog Devices

Analog Devices EVAL-ADPD188BIZ-SK Manual de usuario

Analog Devices

Analog Devices EZ-KIT Lite ADSP-BF533 Manual de usuario

Analog Devices

Analog Devices EVAL-AD7656-1SDZ Manual de usuario

Analog Devices

Analog Devices EVAL-ADM3051EBZ Manual de usuario

Analog Devices

Analog Devices EVAL-FLTR-DF-1RZ Instrucciones de instalación y funcionamiento

Analog Devices

Analog Devices DC2958A Guía de configuración rápida

Analog Devices

Analog Devices EVAL-AD4111SDZ Manual de usuario

Analog Devices

Analog Devices EVAL-AD7386FMCZ Manual de usuario

Analog Devices

Analog Devices EV-ADUCRF101 Manual de usuario

Analog Devices

Analog Devices EVAL-ADAQ4001FMCZ Manual de usuario

Analog Devices

Analog Devices Linear ADI Power DC3054A-C Guía de configuración rápida

Analog Devices

Analog Devices ADuC7024 Manual de usuario

Analog Devices

Analog Devices EVAL-AD5423SDZ Manual de usuario

Analog Devices

Analog Devices EVAL-SSM3515Z Manual de usuario

Analog Devices

Analog Devices EVAL-ADIN1100EBZ Manual de usuario

Analog Devices

Analog Devices EVAL-ADM1075MEBZ Manual de usuario

Analog Devices

Analog Devices ADGM1004EBZ Manual de usuario

Analog Devices

Analog Devices AD5162 Manual de usuario

Analog Devices

Analog Devices EVAL-AD5165DBZ Manual de usuario

Analog Devices

Analog Devices UG-059 Manual de usuario

Analog Devices

Analog Devices UG-189 Manual de usuario

Manuales populares de Placa madre de otras marcas

DFI

DFI SD170 Manual de usuario

ASROCK

ASROCK ROMED8-2T Manual de usuario

Asus

Asus P2L97A Manual de usuario

Winmate

Winmate IC70 Manual de usuario

Asus

Asus MES-B Manual de usuario

Grantech

Grantech SYS8F377VGGA-3OMN Manual de usuario

Telit Wireless Solutions

Telit Wireless Solutions SL869-3DR Manual de usuario

Gigabyte

Gigabyte GA-9IVDT Manual de usuario

Texas Instruments

Texas Instruments ADS8372EVM Manual de usuario

Commell

Commell MS-C73 Manual de usuario

IBT Technologies

IBT Technologies MB860 Manual de usuario

Nvidia

Nvidia TEGRA DG-04927-001_V01 Manual de usuario

Biostar

Biostar M7VIT Bravo Instrucciones de funcionamiento e instalación

Intel

Intel D33217CK Manual de usuario

Asus

Asus F1A55-M LX PLUS R2.0 Manual de usuario

EPC

EPC EPC9147C Manual de usuario

Asus

Asus EX-B760M-V5 D4 Manual de usuario

EPOX

EPOX MU-8KHA0010 Manual de usuario