Acromag APZU AcroPack Series Manual de usuario

Series APZU AcroPack

Zynq Ultrascale+ Based Module

USER’S MANUAL

ACROMAG INCORPORATED

30765 South Wixom Road

Wixom, MI 48393-2417 U.S.A.

Tel: (248) 295-0310

Fax: (248) 624-9234

Data and specifications are subject to change without notice.

8501150A

SERIES APZU+ ACROPACK USER’S MANUAL

Acromag, Inc. Tel: 248-295-0310 - 1 - www.acromag.com

Table of Contents

1.0 GENERAL INFORMATION..........................................................................................4

1.1 Intended Audience .........................................................................................................4

1.2 Preface...........................................................................................................................4

1.2.1 Trademark, Trade Name and Copyright Information .................................................................4

1.2.2 Class A Product Warning...........................................................................................................4

1.2.3 Environmental Protection Statement........................................................................................4

1.3 AcroPack Information – All Models ................................................................................5

1.3.1 Ordering Information ...............................................................................................................5

1.3.2 Key Features.............................................................................................................................5

1.3.3 Key Features PCIe Interface ......................................................................................................6

Figure 1 Block Diagram Model APZU-303...........................................................................................7

Figure 2 Block Diagram Model APZU-301/304....................................................................................8

1.4 Signal Interface Products................................................................................................8

1.5 Software Support ...........................................................................................................8

Windows.........................................................................................................................................9

VxWorks..........................................................................................................................................9

Linux...............................................................................................................................................9

1.6 References .....................................................................................................................9

2.0 PREPARATION FOR USE........................................................................................... 10

2.1 Unpacking and Inspecting ............................................................................................10

2.2 Installation Considerations...........................................................................................11

2.3 Board Configuration .....................................................................................................11

Table 2.1 Boot Mode Switch Settings ................................................................................................11

2.4 Field I/O Connector ......................................................................................................12

Table 2.2 Field I/O Connector Pin Assignments.................................................................................. 12

2.5 Logic Interface Connector.............................................................................................14

Table 2.3 Logic Interface Connections.............................................................................................. 14

3.0 PROGRAMMING INFORMATION........................................................................... 16

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Inc. Tel: 248-295-0310 - 2 - www.acroma

.com

CONFIGURATION REGISTERS ...............................................................................................16

Table 3.1 Configuration Registers...................................................................................................... 17

Table 3.2: BAR1 Memory Map .......................................................................................................... 18

Table 3.3: BAR1 M01_AXI Memory Map............................................................................................ 18

Global Interrupt Register (Read/Write) - (BAR1 + 0x0000 0000) ..........................................19

Table 3.4 Interrupt Register.............................................................................................................19

Module Location In System Register (Read Only) - (BAR1 + 0x0000 0004)............................19

Table 3.5 Location Register ............................................................................................................. 19

Digital Input/Output Registers (Read/Write) - (BAR1 + 0x0000 0008) ..................................20

Digital Direction Control Register (Read/Write) - (BAR1 + 0x0000 000C)..............................20

Interrupt Enable Register (Read/Write) - (BAR1 + 0x0000 0010) ........................................................21

Interrupt Type (COS or H/L) Configuration Register (Read/Write) - (BAR1 + 0x0000 0014) ..21

Interrupt Polarity Registers (Read/Write) - (BAR1 + 0x0000 0018) .......................................22

Interrupt Status Register (Read/Write) - (BAR1 + 0x0000 001C)...........................................22

RS485 Data Registers (Read/Write) - (BAR1 + 0x0000 002C) ................................................22

RS485 Direction Control Register (Read/Write) - (BAR1 + 0x0000 0030) ..............................23

Firmware Revision Register (Read Only) - (BAR1 + 0x0000 0200) .........................................23

System Monitor (SYSMONE 4) ............................................................................................. 23

Table 3.6: SYSMONE4 (System Monitor) (Read Only) - Memory Map.................................................24

Table 3.7: FPGA Voltage and Temperature Range..............................................................................24

Block RAM ...........................................................................................................................24

The Effect of Reset............................................................................................................................ 24

Quad-SPI Flash.................................................................................................................................. 25

MAC Address EEPROM...................................................................................................................... 25

4.0 THEORY OF OPERATION.......................................................................................... 26

4.1 AcroPack Operation .....................................................................................................26

4.2 Digital Interface Logic................................................................................................... 26

5.0 OVERVIEW OF XILINX VIVADO AND VITIS TOOLS .......................................... 31

5.0.1 APZU Testing Hardware Requirements ................................................................................... 31

5.0.2 Vitis Integrated Design Environment and Vivado Design Suite................................................. 31

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5.1 Vivado and the Programmable Logic ............................................................................32

5.1.1 APZU Programmable Logic Block Diagram Overview ...............................................................32

5.1.2 APZU Programmable Logic Block Design Constraints ...............................................................45

5.1.3 APZU Programmable Logic Block FPGA Configuration.............................................................. 45

5.2 Vitis Integrated Design Environment (IDE)....................................................................46

5.2.1 Creating a Hardware Platform using Vitis IDE.......................................................................... 47

6.0 APZU PROCESSING SYSTEM BARE METAL SOFTWARE ................................. 58

6.1 PCIe Software...............................................................................................................58

6.2 Ethernet Bare Metal Software......................................................................................61

6.3 IIC Bare Metal Software ...............................................................................................62

6.4 USB Bare Metal Software .............................................................................................63

6.5 LED Bare Metal Software..............................................................................................67

7.0 SERVICE AND REPAIR ............................................................................................... 68

7.1 Service and Repair Assistance ......................................................................................68

7.2 Preliminary Service Procedure......................................................................................68

7.3 Where to Get Help ....................................................................................................... 68

8.0 SPECIFICATIONS......................................................................................................... 69

8.1 Physical ........................................................................................................................69

8.2 Power Requirements....................................................................................................69

8.3 Environmental Considerations .....................................................................................69

8.3.1 Operating Temperature ..........................................................................................................69

8.3.2. Relative Humidity.................................................................................................................. 70

8.3.3 Isolation .................................................................................................................................70

8.3.4 Vibration and Shock Standards ...............................................................................................70

8.3.5 EMC Directives .......................................................................................................................70

8.4 Reliability Prediction......................................................................................................70

Table 8.4.1 MTBF of APZU-303..........................................................................................................70

8.5 Field I/O .......................................................................................................................71

SERIES APZU+ ACROPACK USER’S MANUAL

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Inc. Tel: 248-295-0310 - 4 - www.acroma

.com

8.6 PCIe Bus Specifications................................................................................................. 71

Table 8.6 PCIe Bus Data Rates ...........................................................................................................71

CERTIFICATE OF VOLATILITY ........................................................................................ 73

REVISION HISTORY ............................................................................................................ 74

1.0 GENERAL INFORMATION

1.1 Intended Audience

This users’ manual was written for technically qualified personnel who will

be working with I/O devices using the AcroPack module. It is not intended

for a general, non-technical audience that is unfamiliar with I/O devices and

their application.

1.2 Preface

The information contained in this manual is subject to change without

notice, and Acromag, Inc. (Acromag) does not guarantee its accuracy.

Acromag makes no warranty of any kind with regard to this material,

including, but not limited to, the implied warranties of merchantability and

fitness for a particular purpose. Further, Acromag assumes no responsibility

for any errors that may appear in this manual and makes no commitment to

update, or keep current, the information contained in this manual. No part

of this manual may be copied or reproduced in any form, without the prior

written consent of Acromag.

1.2.1 Trademark, Trade Name and Copyright Information

Incorporated. All other trademarks, registered trademarks, trade names,

and service marks are the property of their respective owners.

1.2.2 Class A Product Warning

This is a Class A product. In a domestic environment this product may cause

radio interference, in which case the user may find it necessary to take

adequate corrective measures.

1.2.3 Environmental Protection Statement

This product has been manufactured to satisfy environmental protection

requirements where possible. Many components used (structural parts,

circuit boards, connectors, etc.) are capable of being recycled. Final

SERIES APZU+ ACROPACK USER’S MANUAL

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disposition of this product after its service life must be conducted in

accordance with applicable country, state, or local laws or regulations.

1.3 AcroPack Information – All Models

The AcroPack IO module are based on the PCI Express Mini Card

Electromechanical specification and are 70mm in length with an added 100

pin field I/O connector.

The AcroPack is 19.05mm longer than the full length mini PCIe card at

50.95mm. It has the same mPCIe board width of 30mm and uses the same

mPCIe standard board hold down standoff and screw keep out areas.

The APZU+ module is a Xilinx Zynq base module the has FPGA fabric

available for parallel computing applications. The key information resulting

from the parallel processing can then be passed to the ARM processing

system for further manipulation and processing.

The APZU+ utilizes state of the art Surface-Mounted Technology (SMT) to

achieve its wide functionality and is an ideal choice for a wide range of

industrial I/O applications that require a high-density, highly reliable, high-

performance interface at a low cost.

1.3.1 Ordering Information

The AcroPack ordering options are given in the following table.

Model Number Description Zynq I/O Bank

APZU-3011 28 TTL I/O 1.8 volt HP Bank 65

APZU-3031 20 TTL & 3 RS485/422 3.3 volt HD Bank 26

APZU-3041 14 LVDS I/O 1.8 volt HP Bank 65

Note 1: Operating temperature range for models:-40oCto 75oC.

1.3.2 Key Features

Zynq UltraScale Plus device XCZU3CG

oDual-core ARM Cortex-A53 Processing Unit

1.5GHz CPU

Single/double precision Floating Point Unit

oDual-core ARM Cortex-R5 Real-Time processor system

SERIES APZU+ ACROPACK USER’S MANUAL

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Inc. Tel: 248-295-0310 - 6 - www.acroma

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600MHz CPU

Single/double precision Floating Point Unit

oProgrammable Logic resources

154,350 logic cells

70,560 LUTs

360 DSP slices

Board support package and FPGA Design Kit for Xilinx Vivado

oIP Block design

Block RAM

System Monitor

AXI interface to Digital I/O

Ethernet Gigabit Ethernet over copper wire 1000BASE-T

LPDDR4 Storage Memory Provides 2 Giga Byte (512Mbit x 32) of LPDDR4 Memory.

USB Peripheral Port USB 2.0 Transceiver

USB-UART provides a Zynq debug terminal port

Provides MicroSD socket as primary boot device.

512 Mega bit Nor Flash (alternative boot)

1.3.3 Key Features PCIe Interface

PCIe Bus – The AP module includes a PCI Express Generation 1

interface operating at a bus speed of 2.5 Gbps with one lane in each

direction.

Compatibility – PCI Express Base Specification v2.1 compliant PCI

Express Endpoint.

SERIES APZU+ ACROPACK USER’S MANUAL

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Figure 1 Block Diagram Model APZU-303

Quad-SPI Flash

64MB/512Mb

LPDDR4

2 GByte

(512 x 32)

Ethernet MAC

Power Chip

MPSoC

XCZU3CG

Programmable Logic (PL)

PCIe

X1 lane

Ethernet

10/100/1000

USB 2.0

USB-UART

Boot Mode

SW2

AcroPack

I/O

50 Pin

MicroSD

(primary boot) Processing System (PS)

Bank 26

Bank 65

3 RS485 Ports

3.3V TTL Digital

I2C

SERIES APZU+ ACROPACK USER’S MANUAL

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Inc. Tel: 248-295-0310 - 8 - www.acroma

.com

Figure 2 Block Diagram Model APZU-301/304

1.4 Signal Interface Products

Breakout Panel

5028-626

This AcroPack Module will mate directly to all Acromag AP carriers. Once

connected, the module is accessed via a 68 pin front panel connector.

The cables and termination panels are also available. The APZU Cable

Breakout panel (Model number 5028-626) will mate directly to all 68-pin

AcroPack Carriers. The breakout panel and short 68-pin male to male 1 foot

cable will bring an ethernet port, USB 2.0 port, UART to USB port, digital I/O

at jumper blocks, and power and reset buttons out to the field.

1.5 Software Support

The AcroPack series products require support drivers specific to your

operating system. Supported operating systems include: Linux, Windows,

and VxWorks

Quad SPI Flash

64MB/512Mb

LPDDR4

2 GByte

(512 x 32)

Ethernet MAC

Power Chip

MPSoC

XCZU3CG

Programmable Logic (PL)

PCIe

X1 lane

Ethernet

10/100/1000

USB 2.0

USB-UART

Boot Mode

SW2

AcroPack

I/O

50 Pin

MicroSD

(primary boot) Processing System (PS)

(APZU-304)

14 LVDS I/O

I2C

Bank 65

(APZU-301)

28 TTL I/O (1.8V)

SERIES APZU+ ACROPACK USER’S MANUAL

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Windows

Acromag provides software products (sold separately) to facilitate the

development of Windowsapplications interfacing with AcroPack modules,

VPX I/O board products, and PCIe I/O Cards. This software (model APSW-

API-WIN) consists of low-level drivers and Dynamic Link Libraries (DLLs) that

are compatible with a number of programming environments. The DLL

functions provide a high-level interface to boards eliminating the need to

perform low-level reads/writes of registers, and the writing of interrupt

handlers.

VxWorks

Acromag provides a software product (sold separately) consisting of

VxWorkssoftware. This software (Model APSW-API-VXW) is composed of

VxWorks(real time operating system) libraries for all AcroPack modules,

VPX I/O board products, and PCIe I/O Cards. The software is implemented

as a library of “C” functions which link with existing user code to make

possible simple control of all Acromag AcroPack modules.

Linux

Acromag provides a software product consisting of Linuxsoftware. This

software (Model APSW-API-LNX) is composed of Linuxlibraries for all

AcroPack modules, VPX I/O board products, and PCIe I/O Cards. The

software is implemented as a library of “C” functions which link with existing

user code to make possible simple control of all Acromag AcroPack modules.

1.6 References

The following resources regarding AcroPack modules are available for

download on Acromag’s website or by contacting your sales representative.

PCI Express MINI Card Electromechanical Specification, REV 1.2

http://www.pcisig.com

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