2.10 IP Logic Interface Connectors (IP modules A through D) ............................................16
Table 2.2 Standard IP Logic Interface Connections (P11-P14) ..............................................16
2.11 VMEbus Connections ................................................................................................17
Table 2.3 VMEbus P1 CONNECTIONS ..................................................................................17
TABLE 2.4: VME64x bus P2 CONNECTIONS.........................................................................19
2.12 POWER UP TIMING AND LOADING............................................................................21
2.13 DATA TRANSFER TIMING ..........................................................................................21
2.14 FIELD GROUNDING CONSIDERATIONS.......................................................................22
3.0 PROGRAMMING INFORMATION........................................................................... 23
Table 3.1 AVME9675A Carrier Board Short I/O Memory Map .............................................23
Table 3.2 AVME9675A Carrier Board Registers ...................................................................25
3.1 Identification ROM (Read Only, 32 Odd Byte Addresses) .............................................27
Table 3.3 Generic IP Module ID Space Identification (ID) ROM............................................28
3.2 Carrier Board Status Register (Read/Write, Base + C1H) ..............................................28
3.3 Interrupt Level Register (Read/Write, Base + C3H) ......................................................30
3.4 IP Error Register (Read, Base + C5H)............................................................................31
3.5 IP Memory Enable Register (Read/Write, Base + C7H) .................................................31
3.6 IP Memory Base Address & Size Register (Read/Write) ...............................................32
IP_A (Base + D1H), IP_B (Base + D3H), IP_C (Base + D5H), IP_D (Base + D7H),......................32
3.7 IP Interrupt Enable Register (Read, Base + E1H) ..........................................................33
3.8 IP Interrupt Pending Register (Read, Base + E3H) ........................................................33
3.9 IP Interrupt Clear Register (Write, Base + E5H) ............................................................34
Firmware Revision Register (Read Only) - (BAR0 + 0x0000 0200) , Base + F1H .....................................34
XADC Status/Control Register (Read/Write) - Base + F9H ....................................................................35
XADC Address Register (Read/Write) - Base + FBH...............................................................................35
System Monitor Register Map..................................................................................................... 35
