Virtex-6 FPGA CLB User Guide www.xilinx.com UG364 (v1.2) February 3, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
06/24/09 1.0 Initial Xilinx release.
09/16/09 1.1 Add Virtex-6 HXT devices to Table 2. Updated discussions at Look-Up Table (LUT),
page 11, and Static Read Operation, page 29. CLB labeling change in figures throughout
document (Figure 6 through Figure 13, Figure 15, Figure 17, Figure 27 through
Figure 29), including clarifying the TDS/TDH functions, descriptions, and notes in
Table 7, page 39 and Table 8, page 42.
02/03/12 1.2 In Enable – WE/WED, updated second sentence to say that an inactive write enable
prevents writing to memory cells. In Inverting Clock Pins, updated second sentence to
“positive edge of the clock.”
