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GENERAL INFORMATION
1.1 SCOPE OF MANUAL
This manual contains the information necessary to operate and maintain the TrueTime
VME Timing Cards. Multiple configurations are described. This VME product line
consists of the VME Timing board which by itself is referred to as the VME-SG. When a
GPS Engine is added to the basic VME Timing board assembly the product becomes
known as the GPS-VME. All functions described in this manual are available in the
GPS-VME version. The VME-SG does not provide GPS related functions. Both the
GPS-VME and the VME-SG may be configured with the optional alphanumeric display
front panel assembly. In this manual these two board configurations are referred to as
the Model VME-SG-GPS.
1.2 PURPOSE OF EQUIPMENT
The VME-SG-GPS is a precision time source that conforms with the IEEE 1014.C-1
VMEbus Specification. The VME-SG-GPS operates in one of the following three
modes: Generator, GPS Synchronized Generator (GPS-VME only) or Code
Synchronized Generator. In all modes the VME-SG-GPS is designed to supply precise
time to a VME based computer. The time consists of microseconds through thousands
of years. In the Generator mode the time can be started, stopped and preset via the
VME bus. The Generator counters can also be started using an external reference 1
PPS pulse. In the GPS Synchronized Generator mode the card operates with the GPS
Engine. Time and position are derived from the NAVSTAR Global Positioning System
(GPS). In the Code Synchronized Generator mode the generator will phase lock to an
external IRIG B time code. The code format can be either amplitude modulated or DC
shift at RS-422 logic levels. In all synchronized modes the internal oscillator is
disciplined to remove any frequency offset with respect to the external reference. This
is necessary to maintain precise phase lock and to minimize drift error if the input
reference is lost.
Time information and status are available to the VME computer bus in five, 16 bit words.
Each word contains up to 4 packed BCD time values. Since no time ready flags must
be set before time information can be read, the data is immediately available (zero
latency). On board DIP switches select the memory address space where the VME-SG
board resides.
Two independent time capture register sets are provided. Time is latched or "frozen" in
one set of registers by a user read operation via the VME bus. This will provide time on
request. The second set of capture registers has the time latched into it when an
External Event pulse occurs. This allows time tagging of an External Event. An event
normally is programmed to generate an interrupt to flag its occurance.
A Rate Generator is provided that is configured by the user to output one of 5 different
pulse rates to the P2 connector. The Rate Pulse can also be configured to produce an
interrupt to the VME processor.
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