Transcend TS128GSSD18M-M Manual

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

Description

DescriptionDescription

Description

Transcend’s 1.8" Solid State Drive (SSD) advanced,

eSATA / USB 2.0 external storage device is the

perfect way to add an extra hard drive to your

computer for downloading, backing up, and

transporting and your data. With both eSATA and

USB 2.0 connection options, the SSD18M gives you

the ultimate in flexibility. The USB interface provides

maximum compatibility with all types of notebooks

and PCs, while the new high-speed eSATA interface

gives you the maximum performance possible from

your SSD with transfer speeds up to 90MB/s.

Combining portability, reliability, and elegant exterior,

the SSD18M is the perfect choice for downloading,

backing up, and transporting all your data.

Placement

PlacementPlacement

Placement

Features

Features Features

Features

•Build-in 1.8” high-speed solid state drive

•Slim, lightweight, pocket-friendly size

•Faster and more durable than 1.8”/2.5” hard drives

•Two connection options: eSATA or USB2.0

•Shock and vibration resistance

•LED indicator light

Dimensions

DimensionsDimensions

Dimensions

Side Millimeters Inches

A 80.00 ±1.00 3.150 ±0.040

B 50.00 ±1.00 1.969 ±0.040

C 12.50 ±1.00 0.492 ±0.040

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

Specifications

SpecificationsSpecifications

Specifications

Physical Specification

Form Factor 1.8 inch solid state drive

Storage Capacities 32 GB to 128 GB

Length 80.00 ±1.00

Width 50.00 ±1.00

Dimensions (mm)

Height 12.50 ±1.00

Input Voltage DC 5V (from USB port)

Weight 50g (Max)

Connector eSATA 7 pins

USB 4 pins

Environmental Specifications

Operating Temperature 0

℃

(32

℉

) to 70

℃

(158

℉

)

Storage Temperature -30

℃

(-22

℉

) to 70

℃

(158

℉

)

Reliability

Data Reliability Supports BCH ECC 8 bits in 512 bytes

Data Retention 10 years

MTBF 1,500,000 hours

Regulations

Compliance CE, FCC and BSMI

Performance

Model P/N Interface Max. Read

(MB/s)

Max. Write

(MB/s)

USB 35 25

TS32/64/128GSSD18M-M eSATA 90 50

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

Package Dimensions

Package DimensionsPackage Dimensions

Package Dimensions

Below figure illustrates the Transcend 1.8 inch Portable Solid State Drive. All dimensions are in mm.

M-

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

Pin Assignments

Pin AssignmentsPin Assignments

Pin Assignments

Pinouts (USB)

Pin No. Pin Name

01 VCC

02 USB-

03 USB+

04 VSS

Pinouts (eSATA)

Pin No. Pin Name

01 VSS

02 TX+

03 TX-

04 VSS

05 RX-

06 RX+

07 VSS

Pin Identification (USB)

Symbol Function

USB-

USB+

USB differential signal

The pair are used to transmit

Data/Address/Command

VCC USB Cable Power Detector

VSS Ground

Pin Identification (eSATA)

Symbol Function

TX+/TX-

RX+/RX-

eSATA differential signal

The two pairs are used to transmit

Data/Address/Command

VSS Ground

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

Block Diagram

Block DiagramBlock Diagram

Block Diagram

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

Reliability

Reliability Reliability

Reliability

Wear-Leveling algorithm

The controller supports static/dynamic wear leveling. When the host writes data, the controller will find and use the block

with the lowest erase count among the free blocks. This is known as dynamic wear leveling. When the free blocks' erase

count is higher than the data blocks', it will activate the static wear leveling, replacing the not so frequently used user

blocks with the high erase count free blocks.

ECC algorithm

The controller use BCH8 ECC algorithm per 512 bytes. BCH8 can correct up to 8 random error bits within 512 data bytes.

Bad-block management

When the flash encounters ECC failed, program fail or erase fail, the controller will mark the block as bad block to prevent

the used of this block and caused data lost later on.

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

SATA Interface

ATA InterfaceATA Interface

ATA Interface

Out of bank signaling

There shall be three Out Of Band (OOB) signals used/detected by the Phy: COMRESET, COMINIT, and COMWAKE.

COMINIT, COMRESET and COMWAKE OOB signaling shall be achieved by transmission of either a burst of four Gen1

ALIGN

primitives or a burst composed of four Gen1 Dwords with each Dword composed of four D24.3 characters, each

burst having a duration of 160 UI

OOB

. Each burst is followed by idle periods (at common-mode levels), having durations as

depicted in Figure 4 and Table 2.

Figure 4 : OOB signals

Table 2 : OOB signal times

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

COMRESET

COMRESET always originates from the host controller, and forces a hardware reset in the device. It is indicated by

transmitting bursts of data separated by an idle bus condition. The OOB COMRESET signal shall consist of no less than six

data bursts, including inter-burst temporal spacing. The COMRESET signal shall be:

1) Sustained/continued uninterrupted as long as the system hard reset is asserted, or

2) Started during the system hardware reset and ended some time after the negation of system hardware reset, or

3) Transmitted immediately following the negation of the system hardware reset signal.

The host controller shall ignore any signal received from the device from the assertion of the hardware reset signal until the

COMRESET signal is transmitted. Each burst shall be 160 Gen1 UI’s long (106.7 ns) and each inter-burst idle state shall be

480 Gen1 UI’s long (320 ns). A COMRESET detector looksfor four consecutive bursts with 320 ns spacing (nominal). Any

spacing less than 175 ns or greater than 525 ns shall invalidate the COMRESET detector output. The COMRESET

interface signal to the Phy layer shall initiate the Reset sequence shown in Figure 5 below. The interface shall be held

inactive for at least 525 ns after the last burst to ensure far-end detector detects the negation properly.

Figure 5 : comreset sequence

Description:

1. Host/device are powered and operating normally with some form of active communication.

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

2. Some condition in the host causes the host to issue COMRESET

3. Host releases COMRESET. Once the condition causing the COMRESET is released, the host releases the COMRESET

signal and puts the bus in a quiescent condition.

4. Device issues COMINIT – When the device detects the release of COMRESET, it responds with a COMINIT. This is also

the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT.

5. Host calibrates and issues a COMWAKE.

6. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional).

Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN

sequence starting at the device's highest supported speed. After ALIGNP Dwords have been sent

for 54.6us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP

primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional speeds

are available the device tries the next lower supported speed by sending ALIGNP Dwords at that rate for

54.6 us (2048 nominal Gen1 Dword times.) This step is repeated for as many slower speeds as are supported. Once the

lowest speed has been reached without response from the host, the device enters an error state.

7. Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate.

Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at

the same speed as received. A host shall be designed such that it acquires lock in 54.6us (2048

nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword

times) after detecting the release of COMWAKE to receive the first ALIGNP. This ensures interoperability with

multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times)

the host restarts the power-on sequence – repeating indefinitely until told to stop by the Application layer.

8. Device locks – the device locks to the ALIGN sequence and, when ready, sends SYNCP indicating it is ready to start

normal operation.

9. Upon receipt of three back-to-back non-ALIGNP primitives, the communication link is established and normal operation

may begin.

COMINIT

COMINIT always originates from the drive and requests a communication initialization. It is electrically identical to the

COMRESET signal except that it originates from the device and is sent to the host. It is used by the device to request a

reset from the host in accordance to the sequence shown in Figure 6, below.

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1.8” Portable Solid State Drive

Transcend Information Inc.

V1.2

Figure 6 : cominit sequence

Description:

1. Host/device are powered and operating normally with some form of active communication.

2. Some condition in the device causes the device to issues a COMINIT

3. Host calibrates and issues a COMWAKE.

4. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional).

Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN

sequence starting at the device's highest supported speed. After ALIGN

Dwords have been sent for 54.6 us (2048 nominal

Gen1 Dword times) without a response from the host as determined by detection of ALIGN

primitives received from the

host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the

device tries the next lower supported speed by sending ALIGN

Dwords at that rate for 54.6 us (2048 nominal Gen1 Dword

times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached

without response from the host, the device enters an error state.

5. Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate.

Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at

the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword

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