THine THCV235 Manual de usuario

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THCV235 and THCV236

SerDes transmitter and receiver with bi-directional transceiver

General Description

The THCV235 and THCV236 are designed to

support video data transmission between the host and

display.

One high-speed lane can carry up to 32bit data and

3bits of synchronizing signals at a pixel clock

frequency from 6MHz to 160MHz by converting

RGB444 to YCbCr422.

The chipset, which has one high-speed data lane,

can transmit video data up to 1080p/60Hz.

The maximum serial data rate is 4.00Gbps/lane.

Features

Color depth selectable:24/32bit

RGB YCbCr422 color space conversion

function

Wide frequency range

AC coupling for high-speed lanes

CDR requires no external frequency reference

Wide range supply voltage from 1.7V to 3.6V

Additional spread spectrum on data stream

2-wire serial interface bridge function(400kbps)

Remote side GPIO control and monitoring

Low speed data bridge function

QFN64(9mm x 9mm) with exposed pad ground

V-by-One®HS standard version1.4 compliant

EU RoHS compliant

Block Diagram

THCV236

CDR

Controls

Formatter

YCbCr to RGB

D31-D0

HSYNC

VSYNC

CLKOUT

Settings

2-wire I/F

SDA/SCL

RXP

RXN

Deserializer

RCMP

RCMN

LVCMOS output

THCV235

LVCMOS input

PLL

Controls

Formatter

RGB to YCbCr

D31-D0

HSYNC

VSYNC

CLKIN

Settings

2-wire I/F

SDA/SCL

TXP

TXN

Serializer

OSC

TCMP

TCMN

LDO

OSC

LDO

CAPOUT

CAPINA

CAPINP

CAPOUT

CAPINA

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Contents Page

General Description .............................................................................................................................................. 1

Features.................................................................................................................................................................. 1

Block Diagram....................................................................................................................................................... 1

Pin Configuration.................................................................................................................................................. 4

Pin Description ...................................................................................................................................................... 5

Functional Overview........................................................................................................................................... 13

Functional Description........................................................................................................................................ 13

Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)............................................ 13

Power Down (PDN1, PDN0)........................................................................................................................... 13

Main-Link Mode Setting................................................................................................................................. 14

V-by-One®HS Mode (MAINMODE=0)........................................................................................................ 14

Sync Free Mode (MAINMODE=1)................................................................................................................ 14

Color Space Conversion.................................................................................................................................. 14

Pre-emphasis and Drive Select Function (THCV235 only) ......................................................................... 14

Permanent Clock Output (THCV236 only).................................................................................................. 15

Spread Spectrum Clock Generator (SSCG).................................................................................................. 15

Data Enable...................................................................................................................................................... 17

Hot-Plug Function........................................................................................................................................... 18

Lock Detect Function...................................................................................................................................... 18

Field BET Operation....................................................................................................................................... 20

Data Width and Frequency Range Select Function ..................................................................................... 22

Data Mapping.................................................................................................................................................. 24

Sub-Link Mode Setting................................................................................................................................... 26

2-wire serial I/F Mode..................................................................................................................................... 26

2-wire serial I/F Device ID setting ................................................................................................................ 26

2-wire serial I/F Clock Stretching ................................................................................................................. 27

Read/Write access to Sub-Link Master Register ........................................................................................... 28

Read/Write access to Sub-Link Slave Register ............................................................................................. 29

Read/Write access to remote side 2-wire serial slave devices connected to Sub-Link Slave Device............ 31

GPIO.............................................................................................................................................................. 35

Interruption.................................................................................................................................................... 38

Low Speed Data Bridge Mode........................................................................................................................ 39

Register Map........................................................................................................................................................ 40

Absolute Maximum Ratings............................................................................................................................... 50

Recommended Operating Conditions................................................................................................................ 50

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Electrical Specification........................................................................................................................................ 50

AC Timing Diagrams and Test Circuits ............................................................................................................ 56

PCB Layout Guideline regarding VDD and AVDD for THCV236 ................................................................. 66

Package................................................................................................................................................................. 67

Notices and Requests........................................................................................................................................... 68

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Pin Configuration

THCV236 (QFN 64pin)

PDN0

D27

PDN1

LFSEL

TEST1

TEST2

RF/BETOUT

COL0/INT/GPIO2

COL1/SD0

OUTSEL/SD1

TTLDRV/SD2/AIN0/GPIO1

LATEN/SD3/AIN1/GPIO0

D31

D30

D29

D28

VDD

18 D26

D25/GPIO4

20 D24/GPIO3

D23

22 D22

D21

24 D20

VDD

26 CLKOUT

D19

28 D18

D17

30 D16

D15

32 VDD

33 D14

D11

D12

D10

VDD

VSYNC

HSYNC

VDD

CAPOUT

LOCKN/MSSEL

HTPDN/SUBMODE

MAINMODE/RCMN

CAPIN

RXP

RXN

BET

HFSEL/RCMP

(TOP VIEW)

65 EXPGND

D13

RXDEFSEL

THCV235 (QFN 64pin)

PDN0

PDN1

LFSEL

TEST1

TEST2

RF/BETOUT

COL0/INT/GPIO2

COL1/SD0

PRE/SD1

CMLDRV/SD2/AIN0/GPIO3

LATEN/SD3/AIN1/GPIO4

VDD

18 D5

20 D7

22 D9

D10

24 D11

VDD

26 CLKIN

D12

28 D13

D14

30 D15

D16

32 VDD

33 D17

D20

D19

D22

D21

VDD

D23

D24

VDD

D26

D25

D28

D27

VSYNC

D29

D30

HSYNC

VDD

CAPOUT

BET/GPIO1

SSEN/GPIO0

D31

TXN

TXP

HFSEL/TCMN

MAINMODE/TCMP

HTPDN/SUBMODE

LOCKN/MSSEL

CAPINP

CAPIN

(TOP VIEW)

65 EXPGND

D18

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Pin Description

Pin Description for THCV235

Pin Name Pin No. Type Description

TXP 59 CO High-Speed CML Signal Output(Main-Link)

TXN 60 CO High-Speed CML Signal Output(Main-Link)

MAINMODE/

TCMP

57 I/CB MAINMODE : Setting V-by-One

HS Mode or Sync Free

Mode when PDN1=0. See page12.

0 : V-by-One®HS Mode

1 : Sync Free Mode

TCMP : CML Signal Bi-directional Input/Output(Sub-Link)

when PDN1=1.

HFSEL/TCMN 58 I/CB HFSEL : High Frequency mode select when PDN1=0.

0 : High Frequency mode Disable

1 : High Frequency mode Enable

TCMN : CML Signal Bi-directional Input/Output(Sub-Link)

when PDN1=1.

HTPDN/

SUBMODE 64 IL HTPDN : Hot Plug Detect Input when PDN1=0.

SUBMODE : Sub-Link Mode Select when PDN1=1.

0: 2-wire serial interface(I/F) Mode(default No Clock

Stretching mode)

1: Low Speed Data Bridge Mode

Forbid the different setting between THCV235 and THCV236.

LOCKN/MSSEL 63 IL LOCKN : Lock Detect Input when PDN1=0.

MSSEL : Sub-Link Master/Slave Select when PDN1=1.

0 : Sub-Link Master side(inside 2-wire serial I/F is slave)

1 : Sub-Link Slave side(inside 2-wire serial I/F is master)

Sub-Link Master is connected to HOST MPU.

Forbid the same setting between THCV235 and THCV236.

LATEN/SD3/AIN1/

GPIO4

11 B LATEN : Latch select input under Field BET(Main-Link or

Sub-Link).

0 : NOT Latched result

1 : Latched result

SD3 : Sub-Link Data Input/Output when PDN1=1 and

SUBMODE=1.

When Sub-Link is Master (MSSEL=0), SD3 is output.

When Sub-Link is Slave (MSSEL=1), SD3 is input.

AIN1 : Device ID setting for 2-wire serial I/F when

SUBMODE=0 and MSSEL=0. See Table 26.

GPIO4 : General Purpose Input/Output when SUBMODE=0

and MSSEL=1.

When GPIO4 is used as Open-Drain Output, it must be

connected with a pull-up resistor to VDD.

When GPIO4 is used as push pull output or input, no external

component is required.

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CMLDRV/SD2/

AIN0/GPIO3

10 B CMLDRV : High-Speed CML Output Drive Strength Select

when PDN1=0.

0 : Weak Drive Strength (600mV diff p-p)

1 : Normal Drive Strength (800mV diff p-p)

SD2 : Sub-Link Data Input/Output when PDN1=1 and

SUBMODE=1.

When Sub-Link is Master (MSSEL=0), SD2 is input.

When Sub-Link is Slave (MSSEL=1), SD2 is output.

AIN0 : Device ID setting for 2-wire serial I/F when

SUBMODE=0 and MSSEL=0. See Table 26.

GPIO3 : General Purpose Input/Output when SUBMODE=0

and MSSEL=1.

When GPIO3 is used as Open-Drain Output, it must be

connected with a pull-up resistor to VDD.

When GPIO3 is used as push pull output or input, no external

component is required.

PRE/SD1 9 B PRE : Pre-Emphasis Level Select Input when PDN1=0.

0 : Pre-Emphasis Disable

1 : Pre-Emphasis Enable (when CMLDRV=1. See Table 4)

SD1 : Sub-Link Data Input/Output when PDN1=1.

When SUBMODE=0, SD1 is used as SCL input/output for

2-wire serial I/F, requires pull-up resistor to VDD.

When SUBMODE=1 and MSSEL=0, SD1 is input.

When SUBMODE=1 and MSSEL=1, SD1 is output.

COL1/SD0 8 B COL1 : Color Space Converter Enable when PDN1=0 and

MAINMODE=0.

0 : Color Space Converter Disable

1 : Color Space Converter Enable

Data Width Setting when PDN1=0 and MAINMODE=1.

See Table 20.

SD0 : Sub-Link Data Input/Output when PDN1=1.

When SUBMODE=0, SD0 is used as SDA input/output for

2-wire serial I/F, requires pull-up resistor to VDD.

When SUBMODE=1 and MSSEL=0, SD0 is input.

When SUBMODE=1 and MSSEL=1, SD0 is output.

COL0/INT/GPIO2 7 B COL0 : Data Width Setting when PDN1=0. See Table 20.

INT : Interrupt signal output for Sub-Link when

SUBMODE=0 and MSSEL=0. It must be connected with a

pull-up resistor to VDD.

L : Interrupt occurred

H : Steady state

GPIO2 : General Purpose Input/Output when SUBMODE=0

and MSSEL=1.

When GPIO2 is used as Open-Drain Output, it must be

connected with a pull-up resistor to VDD.

When GPIO2 is used as push pull output or input, no external

component is required.

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BET/GPIO1 55 BO BET : Field BET entry when PDN1=0 or Sub-Link is active

and Low Speed Data Bridge Mode(PDN1=1, SUBMODE=1).

0 : Normal Operation

1 : Field BET Operation

GPIO1 : General Purpose Input/Output when SUBMODE=0.

GPIO1 has Open-Drain Output buffer, it must be connected

with a pull-up resistor to VDD.

SSEN/GPIO0 54 BO SSEN : Spread Spectrum Clock Generator(SSCG) Enable

when PDN1=0 or Sub-Link is active and Low Speed Data

Bridge Mode(PDN1=1, SUBMODE=1).

0 : SSCG Disable

1 : SSCG Enable

GPIO0 : General Purpose Input/Output when SUBMODE=0.

GPIO0 has Open-Drain Output buffer, it must be connected

with a pull-up resistor to VDD.

CLKIN 26 I Clock Input

D31-D0 53,52,47-42,

39-33,31-27,

24-17,15-12

I Pixel Data Input

DE 51 I DE Input

HSYNC 50 I HSYNC Input

VSYNC 48 I VSYNC Input

RF/BETOUT 6 B RF : Input Clock Triggering edge select. See Figure 19.

0 : Falling Edge

1 : Rising Edge

BETOUT : Field BET Result Output when Field BET mode

LFSEL 3 I Low Frequency mode select

0 : Low Frequency mode Disable

1 : Low Frequency mode Enable

PDN1 2 IL Sub-Link Power Down

0 : Power Down. Main-Link setting by external pin

1 : Normal Operation. Main-Link Setting by 2-wire serial I/F

PDN0 1 IL Main-Link Power Down

0 : Power Down

1 : Normal Operation

TEST2 5 I Test pin. Must be tied to Ground for normal operation.

TEST1 4 IL Test pin. Must be tied to Ground for normal operation.

CAPOUT 56 PWR Decoupling Capacitor Pin, 1.2V output.

CAPINA 61 PWR Reference Input for Analog Circuit. Must be tied to CAPOUT.

CAPINP 62 PWR Reference Input for Analog Circuit. Must be tied to CAPOUT.

VDD 49,41,32,25,16 PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O

AVDD 40 PWR 1.7-3.6V Analog Power Supply Pin for LDO

EXPGND 65 GND Exposed Pad Ground. Must be tied to the PCB ground plane

through an array of vias.

CO : CML Output buffer , CB : CML Bi-directional buffer

I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer

B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer

PWR : Power supply , GND : Ground

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Table 1. Pin Sharing Description (THCV235)

Sub-Link State →Sub-Link

Power Down

Low Speed Data

Bridge Mode

2-wire serial

I/F Mode

Sub-Link

Master/Slave →- Master Slave Master Slave

PDN1 0 1 1 1 1

HTPDN/SUBMODE * 1 1 0 0

LOCKN/MSSEL * 0 1 0 1

BET/GPIO1 0 0 0 * *

RF/BETOUT RF

BETOUT(*2)

COL0/INT/GPIO2 COL0 COL0 COL0 INT GPIO2(*4)

COL1/SD0 COL1 SD0(input) SD0(output)(*6) SD0(SDA) SD0(SDA)

PRE/SD1 PRE SD1(input) SD1(output)(*6) SD1(SCL) SD1(SCL)

CMLDRV/SD2/AIN0/GPIO3 CMLDRV SD2(input) SD2(output)(*6) AIN0 GPIO3(*5)

LATEN/SD3/AIN1/GPIO4 -(*1) SD3(output)(*6) SD3(input) AIN1 GPIO4(*5)

LATEN(*3)

SSEN/GPIO0 SSEN SSEN SSEN GPIO0(*4) GPIO0(*4)

BET/GPIO1 BET BET BET GPIO1(*4) GPIO1(*4)

MAINMODE/TCMP MAINMODE TCMP

HFSEL/TCMN HFSEL TCMN

LOCKN/MSSEL LOCKN MSSEL

HTPDN/SUBMODE HTPDN SUBMODE

*1 There is no function. LVCMOS IO has input state. Must be fixed at 0 or 1 input.

*2 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output.

*3 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input.

*4 Programmable GPIO input is default on register setting.

*5 Through GPIO open-drain output is default on register setting.

*6 Low Speed Data Bridge Mode output is LVCMOS push pull buffer.

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Pin Description for THCV236

Pin Name Pin No. Type Description

RXP 58 CI High-Speed CML Signal Input(Main-Link)

RXN 57 CI High-Speed CML Signal Input(Main-Link)

HFSEL/RCMP 61 CB/I HFSEL : High Frequency Mode select when PDN1=0.

0 : High Frequency Mode Disable

1 : High Frequency Mode Enable

RCMP : CML Signal Bi-directional Input/Output(Sub-Link) when

PDN1=1.

MAINMODE/

RCMN

60 CB/I MAINMODE : Setting V-by-One

HS Mode or Sync Free Mode

when PDN1=0

0 : V-by-One®HS Mode

1 : Sync Free Mode

RCMN : CML Signal Bi-directional Input/Output(Sub-Link)

when PDN1=1.

HTPDN/

SUBMODE

54 BO HTPDN : Hot Plug Detect Output when PDN1=0. Must be

connected to Tx HTPDN with 10kΩpull-up resistor.

SUBMODE : Sub-Link Mode Select when PDN1=1.

0 : 2-wire serial I/F Mode (default No Clock Stretching mode)

1 : Low Speed Data Bridge Mode

Forbid the different setting between THCV235 and THCV236.

LOCKN/

MSSEL

55 BO LOCKN : Lock Detect Output when PDN1=0. Must be connected

to Tx LOCKN with 10kΩpull-up resistor.

MSSEL : Sub-Link Master/Slave Select when PDN1=1.

0 : Sub-Link Master side(inside 2-wire serial I/F is slave)

1 : Sub-Link Slave side(inside 2-wire serial I/F is master)

Sub-Link Master is connected to HOST MPU.

Forbid the same setting between THCV235 and THCV236.

LATEN/SD3/

AIN1/GPIO0

11 B LATEN : Latch select input under Field BET(Main-Link or

Sub-Link).

0 : NOT Latched result

1 : Latched result

SD3 : Sub-Link Data Input/Output when PDN1=1 and

SUBMODE=1.

When Sub-Link is Master (MSSEL=0), SD3 is output.

When Sub-Link is Slave (MSSEL=1), SD3 is input.

AIN1 : Device ID setting for 2-wire serial I/F when

SUBMODE=0 and MSSEL=0. See Table 26.

GPIO0 : General Purpose Input/Output when SUBMODE=0 and

MSSEL=1.

When GPIO0 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD.

When GPIO0 is used as push pull output or input, no external

component is required.

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TTLDRV/SD2/

AIN0/GPIO1

10 B TTLDRV : TTL Output Drive Strength Select when PDN1=0.

0 : Weak Drive Strength

1 : Normal Drive Strength

SD2 : Sub-Link Data Input/Output when PDN1=1 and

SUBMODE=1.

When Sub-Link is Master (MSSEL=0), SD2 is input.

When Sub-Link is Slave (MSSEL=1), SD2 is output.

AIN0 : Device ID setting for 2-wire serial I/F when

SUBMODE=0 and MSSEL=0. See Table 26.

GPIO1 : General Purpose Input/Output when SUBMODE=0 and

MSSEL=1.

When GPIO1 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD.

When GPIO1 is used as push pull output or input, no external

component is required.

OUTSEL/SD1 9 B OUTSEL : Permanent Clock Output Enable when PDN1=0.

0 : Permanent Clock Output Disable

1 : Permanent Clock Output Enable

SD1 : Sub-Link Data Input/Output when PDN1=1.

When SUBMODE=0, SD1 is used as SCL input/output for 2-wire

serial I/F, requires pull-up resistor to VDD.

When SUBMODE=1 and MSSEL=0, SD1 is input.

When SUBMODE=1 and MSSEL=1, SD1 is output.

COL1/SD0 8 B COL1 : Color Space Converter Enable when PDN1=0 and

MAINMODE=0.

0 : Color Space Converter Disable

1 : Color Space Converter Enable

Data Width Setting when PDN1=0 and MAINMODE=1. See

Table 20.

SD0 : Sub-Link Data Input/Output when PDN1=1.

When SUBMODE=0, SD0 is used as SDA input/output for 2-wire

serial I/F, requires pull-up resistor to VDD.

When SUBMODE=1 and MSSEL=0, SD0 is input.

When SUBMODE=1 and MSSEL=1, SD0 is output.

COL0/INT/

GPIO2

7 B COL0 : Data Width Setting when PDN1=0. See Table 20.

INT : Interrupt signal output for Sub-Link when SUBMODE=0

and Sub-Link Master. It must be connected with a pull-up resistor

to VDD.

L : Interrupt occurred

H : Steady state

GPIO2 : General Purpose Input/Output when SUBMODE=0 and

MSSEL=1.

When GPIO2 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD.

When GPIO2 is used as push pull output or input, no external

component is required.

CLKOUT 26 O Clock Output

D31-D26 12-15,17,18 O Pixel Data Output

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