Texas Instruments TPS65120EVM-076 Manual de usuario

TPS65120EVMĆ076/

TPS65124EVMĆ076

August 2004 PMP Portable Power

User’s Guide

SLVU112

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EVM IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:

This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION

PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided

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compatibility and therefore may not meet the technical requirements of the directive.

Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned

within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE

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TI assumes no liability for applications assistance, customer product design, software performance, or

infringement of patents or services described herein.

Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM

User’s Guide prior to handling the product. This notice contains important safety information about temperatures

and voltages. For further safety concerns, please contact the TI application engineer.

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Post Office Box 655303

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EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the input voltage range described in the EVM User’s

Guide.

Exceeding the specified input range may cause unexpected operation and/or irreversible

damage to the EVM. If there are questions concerning the input range, please contact a TI

field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or

possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to

connecting any load to the EVM output. If there is uncertainty as to the load specification,

please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than

60°C. The EVM is designed to operate properly with certain components above 60°C as long

as the input and output ranges are maintained. These components include but are not limited

to linear regulators, switching transistors, pass transistors, and current sense resistors. These

types of devices can be identified using the EVM schematic located in the EVM User’s Guide.

When placing measurement probes near these devices during operation, please be aware

that these devices may be very warm to the touch.

Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265

Related Documentation From Texas Instruments

Preface



About This Manual

This user’s guide describes the characteristics, operation, and use of the

TPS65120EVM−076 and TPS65124EVM−076 evaluation modules (EVM).

Included are EVM specifications, test results, schematic diagram, bill of

materials (BOM), and recommended test setup.

How to Use This Manual

This document contains the following chapters:

-Chapter 1 – Introduction

-Chapter 2 – EVM Operation

-Chapter 3 – Board Layout

-Chapter 4 – Bill of Materials and Schematic

Related Documentation From Texas Instruments

SLVS531 – TPS6512x data sheet

FCC Warning

This equipment is intended for use in a laboratory test environment only. It gen-

erates, uses, and can radiate radio frequency energy and has not been tested

for compliance with the limits of computing devices pursuant to subpart J of

part 15 of FCC rules, which are designed to provide reasonable protection

against radio frequency interference. Operation of this equipment in other en-

vironments may cause interference with radio communications, in which case

the user at his own expense will be required to take whatever measures may

be required to correct this interference.

If You Need Assistance

Contact your local TI representative.

Contents

vii



1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Background 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Performance Specification Summary 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Modifications 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 EVM Operation 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Input/Output Connections 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Test Setup 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Test Results 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Board Layout 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Board Layout 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Bill of Materials and Schematic 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Bill of Materials 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Schematic 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

viii



2−1 Main Output Efficiency vs Load Current 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Main Output Ripple Voltage 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 VGH and VGL Output Ripple 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 Top Assembly Layer 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 Top Layer Routing 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Bottom Layer Routing 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 HPA076 Schematic 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .



1−1 Typical Performance Specification Summary for VIN = 3.6 V and TA= 25°C 1-2. . . . . . . . . .

4−1 HPA076 Bill of Materials 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

Introduction



This chapter contains introductory information about the TPS65120EVM−076

and TPS65124EVM−076 evaluation modules.

Topic Page

1.1 Background 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Performance Specifiction Summary 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Modifications 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 1

Background

1-2

1.1 Background

The TPS65120EVM uses a TPS65120 single inductor, multichannel output IC

to provide the three output voltages necessary to power amorphous silicon

(a−Si) and low-temperature polysilicon (LTPS) TFT-LCD displays. The

TPS65120 has integrated power−up/down sequencing and an auxiliary linear

regulator providing an additional 3.3-V rail. The TPS65124EVM uses a

TPS65124 IC that provides the same output rails as the TPS65120EVM,

except that it has user-programmable power-up/down sequencing and

replaces the linear regulator with enable signals for VGH and VGL.

1.2 Performance Specification Summary

Table 1−1.Typical Performance Specification Summary for VIN = 3.6 V and TA= 255C

Specification

Output Voltage (V) Output Current (mA)

Specification

Min Typ Max Min Typ Max

VMAIN 4.95 5.00 5.05 25

VGH 11.64 12.00 12.36 4

VGL −12.36 −12.00 −11.64 4

LDOOUT (65120) 3.20 3.30 3.40 20

1.3 Modifications

The HPA076 PCB was designed to allow for several user−defined

modifications. In addition to being able to accommodate the other members

of the TPS6512x family, the board has unpopulated footprints of passive and

active elements which provide the following:

-VLOGIC Rail – P-channel FET Q1 (e.g., Si1031x) and supporting

passives C4, C9, C11, R11, R12, and J6 allow the input voltage to be gated

and provide a rail to power peripheral logic circuits . In addition, VLOGIC

enables VMAIN, VGH, and VGL after the RC time constant delay formed

by R11 and C9 (if R1 is removed).

-VMAIN Power−Down Sequencing – The TPS65120/1/2 actively power

down VMAIN only after FBL reaches 1.2 V typical. Using N-channel FET

Q2 (e.g., Si1032X) and supporting passives R10, R14, and R15 to alter

FBL, VMAIN’s power-down sequencing trip point can be moved. See the

TPS6521x data sheet (SLVS531) for guidance on sizing the passive

components.

-Independent VMAIN Sequencing – After RUN is pulled high, the

TPS6512x devices power up VMAIN. Using dual transistor Q3 (e.g.,

Si1016X), supporting passives JP4, R16, and R20, and removing R18, a

switch can be constructed to switch in VMAIN as the application requires.

R18 shorts out Q3.

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