Texas Instruments TPS5124EVM-001 Manual de usuario

User’s Guide

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User’s Guide

EVM IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:

This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION

PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided

may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective

considerations, including product safety measures typically found in the end product incorporating the goods.

As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic

compatibility and therefore may not meet the technical requirements of the directive.

Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned

within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE

WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,

IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY

PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user

indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products

received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction

of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic

discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE

TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not

exclusive.

TI assumes no liability for applications assistance, customer product design, software performance, or

infringement of patents or services described herein.

Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM

User’s Guide prior to handling the product. This notice contains important safety information about temperatures

and voltages. For further safety concerns, please contact the TI application engineer.

Persons handling the product must have electronics training and observe good laboratory practice standards.

No license is granted under any patent right or other intellectual property right of TI covering or relating to any

machine, process, or combination in which such TI products or services might be or are used.

Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265

DYNAMIC WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the input voltage range of 0 Vdc to100 Vdc.

Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.

If there are questions concerning the input range, please contact a TI field representative prior to connecting

the input power.

Applying loads outside of the specified output range may result in unintended operation and/or possible

permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM

output. If there is uncertainty as to the load specification, please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than 50°C. The EVM

is designed to operate properly with certain components above 50°C as long as the input and output ranges are

maintained. These components include but are not limited to linear regulators, switching transistors, pass

transistors, and current sense resistors. These types of devices can be identified using the EVM schematic

located in the EVM User’s Guide. When placing measurement probes near these devices during operation,

please be aware that these devices may be very warm to the touch.

Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265

SLUU182 − March 2004

4High-Performance Dual Synchronous Buck Conversion Using the TPS5124

High-Performance Dual Synchronous Buck Conversion

Using the TPS5124

Systems Powe

Contents

1 Introduction 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Features 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Schematic 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Component Selection 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Test Results/Performance Data 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Layout Considerations 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 PCB Layout 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 List of Materials 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Introduction

The TPS5124 is a dual independent synchronous buck controller. Both controllers internal to the

TPS5124 operate at 180°phase shift and the input ripple is partially cancelled and therefore the

required input capacitance is reduced. Other features include separate soft-start circuit and

standby control. See the TPS5124 data sheet (SLUS571) for detail.

SLUU182 − March 2004

High-Performance Dual Synchronous Buck Conversion Using the TPS5124

2 Features

This EVM is designed to operate from 12-V bus voltage. It generates two outputs, 3.3 V at 15 A

and 1.5 V at 10 A.

Table 1. TPS5124EVM−001 Performance Summary

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Input voltage range 6.5 12.0 15.0 V

Operating frequency 300 kHz

Input ripple voltage (RMS) VIN = 12 V, IOUT1 = 15 A, IOUT2 = 10 A 92 mV

Channel 1

Output current range 6.5 V ≤VIN ≤15 V 0 15 16 A

Line regulation 6.5 V ≤VIN ≤15 V IOUT = 15 A ±0.1%

Load regulation 1 A ≤IOUT ≤15 A VIN = 12 V ±0.3%

Load transient response voltage

IOUT rising from 0 A to 8.5 A −160

mVPK

Load transient response voltage

change IOUT falling from 8.5 A to 0 A 200 mVPK

Load transient response recovery

IOUT rising from 0 A to 8.5 A 80

Load transient response recovery

time IOUT falling from 8.5 A to 0 A 120 µs

Loop bandwidth IOUT = 15 A 30 kHz

Phase margin IOUT = 15 A 55 °

Output ripple voltage IOUT = 15 A 33 66 mVPP

Output rise time VIN = 12 V, VOUT = 3.3 V, IOUT = 15 A 2.85 ms

Full load efficiency VIN = 12 V, VOUT = 3.3 V, IOUT = 15 A 90.6%

Channel 2

Output current range 6.5 V ≤VIN ≤15 V 0 10 12 A

Line regulation 6.5 V ≤VIN ≤15 V ±0.1%

Load regulation 1 A ≤IOUT ≤10 A VIN = 12 V ±0.3%

Load transient response voltage

IOUT rising from 0 A to 7.5 A −120

mVPK

Load transient response voltage

change IOUT falling from 7.5 A to 0 A 220 mVPK

Load transient response recovery

IOUT rising from 0 A to 7.5 A 40

Load transient response recovery

time IOUT falling from 7.5 A to 0 A 80 µs

Loop bandwidth IOUT = 10 A 23 kHz

Phase margin IOUT = 10 A 55 °

Output ripple voltage IOUT = 10 A 15 30 mVPP

Output rise time VIN = 12 V, VOUT = 1.5 V, IOUT = 10 A 2.12 ms

Full load efficiency VIN = 12 V, VOUT = 1.53 V, IOUT = 10 A 85.5%

3 Schematic

The schematic of TPS5124EVM is shown in Figure 1.

SLUU182 − March 2004

6High-Performance Dual Synchronous Buck Conversion Using the TPS5124

+ +

Figure 1. HPA053 TPS5124 Controller Schematic

SLUU182 − March 2004

High-Performance Dual Synchronous Buck Conversion Using the TPS5124

4 Design Procedure

4.1 Frequency Setting

Many factors influence frequency selection. Higher switching frequency leads to smaller output

inductor and capacitor, reducing the size of the converter. However, higher switching frequencies

increase switching losses, and lower the converter’s efficiency. A frequency of 300 kHz is

chosen for this design for reasonable efficiency and size.

Capacitor C16, which is connected from CT (pin 5) to ground, programs the oscillator frequency.

A C16 value of 47 pF yields a switching frequency of 300 kHz at 25°C.

4.2 Inductance Value

The inductance value can be calculated using equation (1).

L+VOUT

f(min) IRIPPLE ǒ1*VOUT

VIN(max)Ǔ

where

•IRIPPLE is the ripple current flowing through the inductor

The ripple current affects the output voltage ripple and core losses. Based on 20% ripple current

and 300 kHz, the inductance value is calculated as 2.2 µH. An off-the-shelf 2.2-µH inductor from

Vishay is chosen. The part number is IHLP−5050CE−01−2R2M01. The DCR is 7 mΩand the

DCR related conduction loss is 1.6 W, which is about 3.3% of output power.

The same procedure is followed to choose the inductor for Channel 2. The same inductor is

chosen.

4.3 Output Capacitors

The required output capacitance and its ESR can be calculated using equations (2) and (3).

COUT(min) +IRIPPLE

8 f VRIPPLE

ESROUT +VRIPPLE

IRIPPLE

With 1% output voltage ripple, the required minimum output capacitance is 54 µF and its ESR

should be less than 7.7 mΩ.

From the load transient point of view, the capacitance needed for 6% overshoot can be

calculated using equation (4).

COUT +ǒIOUT(max)Ǔ2 L

ǒVOUT2Ǔ2*ǒVOUT1Ǔ2

(1)

(2)

(3)

(4)

SLUU182 − March 2004

8High-Performance Dual Synchronous Buck Conversion Using the TPS5124

where

•VOUT2 is the allowed overshoot voltage

•VOUT1 is the nominal operating voltage

For 6% overshoot, the required capacitance is about 370 µF. Four 100-µF, 6.3-V ceramic

capacitors are used. Their ESR value is 2.0 mΩeach.

4.4 Input Capacitors

Due to the out of phase operation, the input current ripple is partially cancelled. The total RMS

current in the input capacitor is calculated as follows. This assumes the total input current goes

into the input capacitor to the power ground and ignores the ripple current in the inductor.

UDG−04010

0 V

ǒIOUT1 *IAVGǓ

ǒIOUT2 *IAVGǓ

IAVG

2)D2 T

D1 T

IAVG

Figure 2. Case One (D1 < 0.5, D2 < 0.5)

UDG−04010

ǒIOUT1 *IAVGǓ

ǒIOUT1 )IOUT2 *IAVGǓ

0 T

2)D2 T

D1 T

IAVG

0 V

ǒIOUT2 *IAVGǓ

Figure 3. Case Two (D2 < 0.5 < D1 )

SLUU182 − March 2004

High-Performance Dual Synchronous Buck Conversion Using the TPS5124

4.4.1 Case One: D1, D2 < 0.5.

The ripple current through the input capacitor is shown in Figure 2 and can be calculated using

equation (6).

IincapRMS :+

T ȧ

ȲŕD1@T

0ǒIOUT1 *IAVGǓ2dt )ŕT

D1@TǒIAVGǓ2dt )ŕT

2)D2@T

ǒIOUT2 *IAVGǓ2dt )ŕT

2)D2@TǒIAVGǓ2dtȧ

IincapRMS :+D1 ǒIOUT1Ǔ2)D2 ǒIOUT2Ǔ2*ǒIAVGǓ2

where:

IAVG is the average input current.

IAVG +IOUT1 D1 )IOUT2 D2

4.4.2 Case Two: D2 < 0.5 < D1.

The ripple current through the input capacitor is shown in Figure 3 and can be calculated using

equation (8).

IincapRMS :+

T ƪŕT

0ǒIOUT1 *IAVGǓ2dt )ŕD1@T

ǒIOUT1 )IOUT2 *IAVGǓ2dt )ŕT

2)D2@T

D1@TǒIOUT2 *IAVGǓ2dt )ŕT

2)D2@TǒIAVGǓ2dtƫ

IincapRMS :+D1 ǒIOUT1Ǔ2)D2 ǒIOUT2Ǔ2)(2 D1*1) IOUT1 IOUT2 *ǒIAVGǓ2

This EVM meets “Case One” criteria. The maximum input ripple current is 6.7 A at VIN =12 V.

Two 150-µF, 20-V special polymer capacitors from Panasonic (part number is EEFWA1D151P)

are used. It can handle 3.7 A of ripple current each. The ESR value of each capacitor is 26 mΩ.

So the input ripple voltage is calculated using equation (10) and is approximately 88 mVRMS

IRIPPLE +IincapRMS ESR

(5)

(6)

(7)

(8)

(9)

(10)

SLUU182 − March 2004

10 High-Performance Dual Synchronous Buck Conversion Using the TPS5124

4.5 Compensation Design

The following compensation loop design uses Channel 1 as example, but a design for Channel 2

follows the same rules.

TPS5124 uses voltage-mode control method. A Type III compensation network, formed by R1,

R2, R4, C14, C12, and C23, is used to guarantee the stability. The L-C frequency of the power

stage is around 5.4 kHz and the ESR zero is at 790 KHz due to the low ESR of the ceramic

capacitors. An overall crossover frequency (f0db) of 30 kHz is chosen for reasonable transient

response and stability. Both zeros (fZ1 and fZ2) from the compensator are set at 2.68 kHz. The

two poles (fP1 and fP2) and are set at 150 kHz and 2 MHz. The frequency of poles and zeros are

defined by the following equations.

fZ1 +1

2p R4 C14

fZ2 +1

2p R1 C12, assuming R1 ơR2

fP1 +1

2p R4 C23

fP2 +1

2p R2 C12, assuming C14 ơC23

The transfer function for the compensator is calculated as:

A(s) +(1)s C14 R2) [1)s C12 (R1 )R2)]

s R1 C14 ƪǒ1)C23

C14Ǔ)s R4 C23ƫ (1)s R2 C12)

100

−10

−30

−20

120

180

140

160

100

100 k

1 k 10 k

GAIN AND PHASE

OSCILLATOR FREQUENCY

(CHANNEL 1)

Figure 4.

fOSC − Frequency − Hz

Phase − °

Gain − dB

Gain

Phase

VIN = 12 V

VOUT = 3.3 V

IOUT = 15 A

−10

−30

−20

120

140

160

100

180

100 100 k1 k 10 k

fOSC − Frequency − Hz

Gain − dB

GAIN AND PHASE

OSCILLATOR FREQUENCY

(CHANNEL 2)

Figure 5. Channel 2

L = 0.6 µH

Phase − °

VIN = 12 V

VOUT = 1.5 V

IOUT = 10 A

Gain

Phase

−20

(11)

(12)

(13)

(14)

(15)

Tabla de contenidos

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