Texas Instruments PCM1802EVM Manual de usuario
User’s Guide
PCM1802EVM and PCM1803AEVM Evaluation Module
ABSTRACT
This user's guide describes the function and use of the PCM1802EVM and PCM1803AEVM. This document
includes the hardware configuration instructions, a quick-start guide, jumper and connector descriptions,
schematics, and printed-circuit board (PCB) layout that demonstrate TI's recommended practices for these
devices.
Figure 1-1. PCM1802EVM and PCM1803AEVM
Table of Contents
1 Trademarks..............................................................................................................................................................................1
2 Introduction.............................................................................................................................................................................2
3 Power Supply.......................................................................................................................................................................... 2
4 Hardware Configuration.........................................................................................................................................................3
5 Interfacing With the EVM........................................................................................................................................................5
5.1 PCM1802EVM and PCM1803AEVM Inputs...................................................................................................................... 5
5.2 PCM1802EVM and PCM1803AEVM Output..................................................................................................................... 5
6 Switching Between the PCM1802EVM and PCM1803AEVM............................................................................................... 5
7 Board Layout...........................................................................................................................................................................6
8 Schematic and Bill of Materials.............................................................................................................................................7
8.1 Schematic.......................................................................................................................................................................... 8
8.2 Bill of Materials.................................................................................................................................................................10
9 Related Documentation........................................................................................................................................................14
1 Trademarks
All trademarks are the property of their respective owners.
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2 Introduction
The PCM1802EVM and PCM1803AEVM are evaluation modules (EVMs) designed to demonstrate the
performance and functionality of the PCM1802 and PCM1803A devices, respectively. Although the populated
components differ between the two device variants, the PCM1802EVM and PCM1803AEVM use the same
hardware and printed circuit board (PCB) layout. The variants are differentiated by the label at the top of
the PCB, and by the variant name, DC167-001 (PCM1802EVM) and DC167-002 (PCM1803AEVM), within the
manufacturing files.
Both the PCM1802 and PCM1803A are high-performance, low-cost, single-chip, stereo analog-to-digital
converters (ADCs) with single-ended analog voltage inputs. The devices are configured through logic-level
mode selection pins and do not require a digital interface such as I2C or SPI to configure registers. As such, no
software is necessary to interface with the EVMs. The EVMs are powered with a single 5-V supply. Access to the
converter output is provided on the audio serial interface in I2S, right-justified (RJ), and left-justified (LJ) formats.
3 Power Supply
The PCM1802EVM and PCM1803AEVM are powered with a single 5-V power supply connected to J17. An
onboard low-dropout regulator converts the 5-V supply to the 3.3-V rail used by the ADC. The analog supply,
VCC, is fixed at 5 V and the digital supply, VDD, is fixed at 3.3 V. The power status of the EVM is indicated by
LED (D1), which illuminates when power is applied to the board.
J1 (VCC, 5 V) and J2 (VDD, 3.3 V) are jumper wires that can be used to disconnect the voltage supply
pins (VCC and VDD) of the device from the supply nets (5 V and 3.3 V). This process is done by cutting or
unsoldering the wire. These disconnections can help measure the power consumption of each voltage rail using
an ammeter or digital multimeter (DMM).
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4 Hardware Configuration
The audio data format and the ADC operating mode are controlled by the MODE0, MODE1, FMT0, FMT1, OSR,
BYPAS, and PWDN pins. These signals are referenced to VDD and can be set to high (1) or low (0). If no shunt
is installed, then an internal 50-kΩ pulldown resistor sets the pin low so that the ADC remains in a defined state.
Table 4-1 shows the header numbers and their pin functions and Table 4-2, Table 4-3, Table 4-4, Table 4-5, and
Table 4-6 list the possible modes, output formats, and other functions of the device.
MODE0 and MODE1 are used to select the serial audio data communication timing and must be set prior to
power on. In controller mode, BCK and LRCK are output pins that are generated by internal divider circuitry
from the SCKI input. Thus, SCKI must be a valid multiple of the intended sample rate. The frequency of BCK is
constant at 64 BCKs per frame.
In peripheral mode, BCK and LRCK function as input pins. The device accepts either 64-BCKs per frame or
48-BCKs per frame format (only for a 384 fS system clock), but not a 32-BCK per frame format. Although BCK
and LRCK are no longer derived from SCKI in peripheral mode, a valid SCKI is still required for operation.
Table 4-1. PCM1802EVM and PCM1803AEVM Headers and Jumpers
Designator Function
J9 Audio serial interface: system clock input (SCK_IN)
J8 Audio serial interface: bit-clock input or output (BCK)
J15 Audio serial interface: latch-enable input or output (LRCLK)
J18 Audio serial interface: digital data output (DOUT)
J16 PCM1802 only: Frame synchronous clock input and output (FSYNC)
J4 System clock source select (SCKI)
J10 Format [0] select (FMT0)
J11 Format [1] select (FMT1)
J3 Mode [0] select (MODE0 and MD0)
J6 Mode [1] select (MODE1 and MD1)
J12 Oversampling ratio select (OSR)
J13 High-pass filter bypass control select (BYPAS)
J14 Power-down control (nPWDN)
J7 Analog audio input: right
J5 Analog audio input: left
J17 5-V supply input
J1 VDD, 3.3-V jumper wire
J2 VCC, 5-V jumper wire
Table 4-2. PCM1802 and PCM1803A Mode Settings
MODE1, MD1 MODE0, MD0 Interface Mode
0 0 Peripheral mode (256 fs, 384 fs, 512 fs, and 768 fs)
0 1 Controller mode (512 fs)
1 0 Controller mode (384 fs)
1 1 Controller mode (256 fs)
Table 4-3. PCM1802 and PCM1803A Format Settings
FMT1 FMT0 Format
0 0 Left-justified, 24-bit
0 1 I2S, 24-bit
1 0 Right-justified, 24-bit
1 1 Right-justified, 20-bit
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Table 4-4. PCM1802 and PCM1803A Oversampling Ratio Settings
OSR Oversampling Ratio
0 x64
1 x128 (fS < 50 kHz)
Table 4-5. PCM1802 and PCM1803A High-Pass Filter Bypass Mode Settings
BPYAS High-Pass Filter (HPF) Mode
0 Normal (no DC component on DOUT) mode
1 Bypass (DC component on DOUT) mode
Table 4-6. PCM1802 and PCM1803A Power-Down Settings
nPWDN Mode
0 Power-down mode
1 Normal operation mode
The default jumper locations place the device in peripheral mode and in the I2S, 24-bit audio format with x64
oversampling ratio, normal HPF mode, and not in power-down mode. For more information on the operating
modes and clock timing of the PCM1802 and PCM1803A device, see the PCM1802 Single-Ended Analog-Input
24-Bit, 96-kHz Stereo A/D Converter and PCM1803A Single-Ended, Analog-Input 24-Bit, 96-kHz Stereo A/D
Converter data sheets, respectively.
In addition, the SCKI signal can be sourced from an onboard oscillator or provided externally at J9. J4 selects
the SCKI clock source (SCK_OSC) or externally from J9 (SCK_IN) by changing the position of J4 as shown in
Table 4-7.
Table 4-7. PCM1802EVM and PCM1803AEVM SCK Source Select
Shunt Position SCK Source Select
Pins 1-2 SCKI sourced externally through J9 (SCK_IN)
Pins 2-3 SCKI sourced from onboard oscillator (SCK_OSC)
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5 Interfacing With the EVM
5.1 PCM1802EVM and PCM1803AEVM Inputs
The right and left audio inputs to the PCM1802EVM and PCM1803AEVM can be applied through the RCA
connectors (J7 and J5, respectively) or directly to the test points (TP4 and TP3, respectively). The single-ended
audio inputs pass through an optional antialiasing filter made by R6 and C8 for the right input and R3 and C6 for
the left input. The capacitors can be left depopulated and the resistors replaced with 0-Ω resistors if the filter is
not desired.
An input high-pass filter is created by the 4.7-µF capacitors (C5 and 79) and 20-kΩ input impedance for the
PCM1802 or 40-kΩ input impedance for the PCM1803A. This filter structure results in a high-pass filter cutoff
frequency of approximately 1.69-Hz and 0.84-Hz for the PCM1802EVM and PCM1803AEVM, respectively.
5.2 PCM1802EVM and PCM1803AEVM Output
The digital I/O of the PCM1802EVM and PCM1803AEVM are provided by J8, J9, J15, J16, and J18; the
functions are outlined in Table 4-1. The first two pins of each header are duplicated signals to allow for signal
input and monitoring. The third pin of each signal is connected to GND.
6 Switching Between the PCM1802EVM and PCM1803AEVM
As discussed previously, the populated components differ between the two variants, but the PCM1802EVM and
PCM1803AEVM use the same hardware and PCB layout. The variants are differentiated by the label at the top
of the PCB, and by the variant name, DC167-001 (PCM1802EVM) and DC167-002 (PCM1803AEVM), within the
manufacturing files. As such, a PCM1802EVM can be converted to a PCM1803AEVM and vice versa.
The difference between the two variants is located at pin 9 of U1, which can be either the PCM1802 or
PCM1803A. Specifically, all pin functions between the two devices are similar or identical, with the exception of
pin 9. Pin 9 functions as FSYNC for the PCM1802, and functions as TEST for the PCM1803A.
Although the FSYNC and TEST details can be reviewed within each device data sheet, the hardware changes
are captured in Section 8.1. Specifically, FSYNC is considered part of the audio serial interface (J16), which can
be used when R9 is populated, and TEST is a test pin that must be grounded for normal operation, which can be
done through R11.
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7 Board Layout
Figure 7-1 to Figure 7-4 illustrate the EVM board layout.
Figure 7-1. PCM1802EVM and PCM1803AEVM Top Layer
Figure 7-2. PCM1802EVM and PCM1803AEVM Power Plane 1
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Figure 7-3. PCM1802EVM and PCM1803AEVM Power Plane 2
Figure 7-4. PCM1802EVM and PCM1803AEVM Bottom Layer
8 Schematic and Bill of Materials
This section contains the EVM schematics and bill of materials.
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8.1 Schematic
Figure 8-1 and Figure 8-2 illustrate the EVM schematics for the PCM1802EVM and PCM1803AEVM, respectively.
47.0
R13
GND GND GND GND
GND
GND
GND
GND
GND
GND
10uF
16V
C16
GND GND GND GNDGND
+5V+3.3V
+3.3V+5V
+3.3V
+3.3V
LRCK
GND
GND
GND
GND
CLOCK SOURCE HEADERS
POWER
GND GND
GND
+3.3V
GND
1
2
3
J4
CONTROLLER
1 2
Y1
1
2
J7
1
2
J5
0.1uF
50V
C2
+5V
GND
SCKI
SCK_IN
SCKI
GND
GNDGND
CLOCK GENERATOR
1.0M
R8
0
R10
PCM1802EVMDC167A
Main Schematics
INTERFACE
MODE [0]
MODE [1]
INTERFACE
EXTERNAL
+5V INPUT
DOUT
BCK
0.1uF
16V
C17
1
2
J17
Green
1 2
D1
442
R1
GND
+3.3V
Power Ready
POWER LED
LRCK
BCK
DOUT
SCK_IN
0.1uF
50V
C4
0.1uF
50V
C13
SN74LVC1GX04DCKR
NC 1
GND 2
Y6
X1
3
X2
4
VCC
5
U2
47.0
R20 47.0
R14
47.0
R2
10uF
16V
C18
0.1uF
16V
C19
1
2
3
J3
1
2
3
J6
0.1uF
16V
C9
GND
GND
100
R6
100
R3
1
2
3
J9
1
2
3
J8
1
2
3
J15
1
2
3
J18
10.0k
R4
10.0k
R5
10 Fµ
16V
C1
10 Fµ
16V
C3
10 Fµ
16V
C12
PDWN
7
BCK
11
BYPAS
8
FMT0
17
FMT1
18
FSYNC
9
LRCK
10
OSR
16
SCKI
15
VCC
5
VDD
14
VINL
1
VINR
2
VREF1
3
VREF2
4
AGND 6
DGND 13
DOUT 12
MODE0 19
MODE1 20
PCM1802DBR
U1
GND GND
0.1uF
50V
C15
10 Fµ
16V
C14
FSYNC
47.0
R9
+3.3V
FORMAT [1]
SELECTION
1
2
3
J10
GND
10.0k
R15
+3.3V
1
2
3
J11
GND
10.0k
R16
+3.3V
1
2
3
J12
GND
10.0k
R17
OVERSAMPLE
SELECTION
RATIO
+3.3V
1
2
3
J13
GND
10.0k
R18
HPF BYPASS
SELECTION
CONTROL
+3.3V
1
2
3
J14
GND
10.0k
R19
POWER DOWN
CONTROL
FORMAT [0]
SELECTION
SELECTION
SELECTION
GND
FSYNC
1
2
3
J16
(SCKI SOURCE)
FORMAT
NUMBER FM T1 FMT0 FORMAT
0 0 0 Left-justified, 24-bit
1 0 1 I2S, 24-bit
2 1 0 Right-justified, 24-bit
3 1 1 Right-justified, 20-bit
VINL
VINR
VREF1
VREF2
SCKI_pin
BCK_pin
LRCK_pin
FMT0
FMT1
OSR
BYPAS
nPDWN
Pin_9
DOUT_pin
MODE0
MODE1
OSR OVERSAM PLING RATIO
0 x64
1 x128 (f < 50 kHz)
S
BPYAS HIGH-PASS FILTER (HPF) M ODE
0 Normal (no DC component on DOUT)
mode
1 Bypass (DC component on DOUT)
mode
nPWDN MODE
0 Power-down mode
1 Normal operation mode
0
R12
VCC/+5V
TP10
GNDGND
TP11
GNDGND
OSCOPE GND CLIP BAR
4.7µF
16V
C7
4.7µF
16V
C5
25V
0.01uF
C6
25V
0.01uF
C8
MODE1 MODE0 INTERFACE MODE
0 0 Peripheral Mode (256 fS, 384 fS, 512 fS, 768 fS)
0 1 Controller Mode (512 fS)
1 0 Controller Mode (384 fS)
1 1 Controller Mode (256 fS)
OR PERIPHERAL
SELECTION
TP3
INL
TP6
VREF1
TP7
VREF2
TP1
VCC/+5V
TP4
INR
TP9
GND
TP2
GND
0
R11
GND
10.0k
R7
+3.3V
TP5
Pin_9
GND
SCK_OSC
50V
33pF
C10
50V
33pF
C11
J1 J2
VDD/+3.3V
VCC/+5V
TP8
+3.3V
IN
1
GND 2
EN
3NR/FB 4
OUT 5
TPS73601DBVR
U3
52.3k
R21
30.1k
R22
Figure 8-1. PCM1802EVM (DC167-001) Main Schematic Page
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47.0
R13
GND GND GND GND
GND
GND
GND
GND
GND
GND
10uF
16V
C16
GND GND GND GNDGND
+5V+3.3V
+3.3V+5V
+3.3V
+3.3V
LRCK
GND
GND
GND
GND
CLOCK SOURCE HEADERS
POWER
GND GND
GND
+3.3V
GND
1
2
3
J4
CONTROLLER
1 2
Y1
1
2
J7
1
2
J5
0.1uF
50V
C2
+5V
GND
SCKI
SCK_IN
SCKI
GND
GNDGND
CLOCK GENERATOR
1.0M
R8
0
R10
PCM1803AEVMDC167A
Main Schematics
INTERFACE
MODE [0]
MODE [1]
INTERFACE
EXTERNAL
+5V INPUT
DOUT
BCK
0.1uF
16V
C17
1
2
J17
Green
1 2
D1
442
R1
GND
+3.3V
Power Ready
POWER LED
LRCK
BCK
DOUT
SCK_IN
0.1uF
50V
C4
0.1uF
50V
C13
SN74LVC1GX04DCKR
NC 1
GND 2
Y6
X1
3
X2
4
VCC
5
U2
47.0
R20 47.0
R14
47.0
R2
10uF
16V
C18
0.1uF
16V
C19
1
2
3
J3
1
2
3
J6
0.1uF
16V
C9
GND
GND
100
R6
100
R3
1
2
3
J9
1
2
3
J8
1
2
3
J15
1
2
3
J18
10.0k
R4
10.0k
R5
10 Fµ
16V
C1
10 Fµ
16V
C3
10 Fµ
16V
C12
VCC
5
VDD
14
VINL
1
VINR
2
VREF1
3
VREF2
4
FMT0
17
FMT1
18
MODE0 19
MODE1 20
PDWN
7
BCK
11
BYPAS
8
DOUT 12
LRCK
10
OSR
16
SCKI
15
TEST
9AGND 6
DGND 13
PCM1803ADBR
U1
GND GND
0.1uF
50V
C15
10 Fµ
16V
C14
FSYNC
47.0
R9
+3.3V
FORMAT [1]
SELECTION
1
2
3
J10
GND
10.0k
R15
+3.3V
1
2
3
J11
GND
10.0k
R16
+3.3V
1
2
3
J12
GND
10.0k
R17
OVERSAMPLE
SELECTION
RATIO
+3.3V
1
2
3
J13
GND
10.0k
R18
HPF BYPASS
SELECTION
CONTROL
+3.3V
1
2
3
J14
GND
10.0k
R19
POWER DOWN
CONTROL
FORMAT [0]
SELECTION
SELECTION
SELECTION
GND
FSYNC
1
2
3
J16
(SCKI SOURCE)
FORMAT
NUMBER FM T1 FMT0 FORMAT
0 0 0 Left-justified, 24-bit
1 0 1 I2S, 24-bit
2 1 0 Right-justified, 24-bit
3 1 1 Right-justified, 20-bit
VINL
VINR
VREF1
VREF2
SCKI_pin
BCK_pin
LRCK_pin
FMT0
FMT1
OSR
BYPAS
nPDWN
Pin_9
DOUT_pin
MODE0
MODE1
OSR OVERSAM PLING RATIO
0 x64
1 x128 (f < 50 kHz)
S
BPYAS HIGH-PASS FILTER (HPF) M ODE
0 Normal (no DC component on DOUT)
mode
1 Bypass (DC component on DOUT)
mode
nPWDN MODE
0 Power-down mode
1 Normal operation mode
0
R12
VCC/+5V
TP10
GNDGND
TP11
GNDGND
OSCOPE GND CLIP BAR
4.7µF
16V
C7
4.7µF
16V
C5
25V
0.01uF
C6
25V
0.01uF
C8
MODE1 MODE0 INTERFACE MODE
0 0 Peripheral Mode (256 fS, 384 fS, 512 fS, 768 fS)
0 1 Controller Mode (512 fS)
1 0 Controller Mode (384 fS)
1 1 Controller Mode (256 fS)
OR PERIPHERAL
SELECTION
TP3
INL
TP6
VREF1
TP7
VREF2
TP1
VCC/+5V
TP4
INR
TP9
GND
TP2
GND
0
R11
GND
10.0k
R7
+3.3V
TP5
Pin_9
GND
SCK_OSC
50V
33pF
C10
50V
33pF
C11
J1 J2
VDD/+3.3V
VCC/+5V
TP8
+3.3V
IN
1
GND 2
EN
3NR/FB 4
OUT 5
TPS73601DBVR
U3
52.3k
R21
30.1k
R22
Figure 8-2. PCM1803AEVM (DC167-002) Main Schematic Page
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8.2 Bill of Materials
Table 8-1 and Table 8-2 list the bill of materials (BOM) for the PCM1802EVM and PCM1803AEVM, respectively.
Table 8-1. PCM1802EVM (DC167-001) Bill of Materials
Designator Quantity Value Description Package Reference Part Number Manufacturer
!PCB1 1 Printed Circuit Board DC167 Any
C1, C3, C12, C14 4 10uF CAP, CERM, 10 uF, 16 V, +/- 10%, X7R, 0805 805 CL21B106KOQNNNE Samsung Electro-
Mechanics
C2, C4, C13, C15 4 0.1uF CAP, CERM, 0.1 uF, 50 V, +/- 10%, X7R, 0402 402 C1005X7R1H104K050BB TDK
C5, C7 2 4.7uF CAP, CERM, 4.7 uF, 16 V, +/- 10%, X7R, AEC-
Q200 Grade 1, 0805
805 GCM21BR71C475KA73L MuRata
C6, C8 2 0.01uF CAP, CERM, 0.01 uF, 25 V, +/- 5%, C0G/NP0,
AEC-Q200 Grade 1, 0603
603 C0603C103J3GECAUTO Kemet
C9, C17, C19 3 0.1uF CAP, CERM, 0.1 uF, 16 V, +/- 10%, X7R, 0402 402 GCM155R71C104KA55D MuRata
C10, C11 2 33pF Cap Ceramic 33pF 50V C0G ±5% SMD 0402
+125°C Paper T/R
402 CL05C330JB5NNNC Samsung
C16, C18 2 10uF CAP, CERM, 10 uF, 16 V, +/- 20%, X5R, 0603 603 GRM188R61C106MAALD MuRata
D1 1 Green LED, Green, SMD LED_0805 LTST-C170KGKT Lite-On
H1, H2, H3, H4 4 Bumpon, Hemisphere, 0.25 X 0.075, Clear 75x250 mil SJ5382 3M
J1, J2 2 Jumper Wire, 100mil spacing, pkg of 200, TH Wire Jumper 923345-01-C 3M
J3, J4, J6, J8, J9, J10,
J11, J12, J13, J14, J15,
J16, J18
13 Header, 100mil, 3x1, Gold, TH 3x1 Header TSW-103-07-G-S Samtec
J5 1 RCA Jack, 1Pos, Tin, White, R/A, TH RCA Jack, 1Pos, R/A,
TH
RCJ-013 CUI Inc.
J7 1 RCA Jack, 1Pos, Tin, Red, R/A, TH RCA Jack, 1Pos, R/A,
TH
RCJ-012 CUI Inc.
J17 1 Terminal Block, 3.5mm Pitch, 2x1, TH 7.0x8.2x6.5mm ED555/2DS On-Shore Technology
LBL1 1 Thermal Transfer Printable Labels, 0.650" W x
0.200" H - 10,000 per roll
PCB Label 0.650 x
0.200 inch
THT-14-423-10 Brady
R1 1 442 RES, 442, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 603 CRCW0603442RFKEA Vishay-Dale
R2, R9, R13, R14, R20 5 47 RES, 47.0, 1%, 0.1 W, 0603 603 RC0603FR-0747RL Yageo
R3, R6 2 100 RES, 100, 1%, 0.125 W, AEC-Q200 Grade 0,
0805
805 CRCW0805100RFKEA Vishay-Dale
R4, R5, R7, R15, R16,
R17, R18, R19
8 10.0k RES, 10.0 k, 1%, 0.1 W, AEC-Q200 Grade 0,
0603
603 CRCW060310K0FKEA Vishay-Dale
R8 1 1.0Meg RES, 1.0 M, 5%, 0.063 W, AEC-Q200 Grade 0,
0402
402 CRCW04021M00JNED Vishay-Dale
R10 1 0 RES, 0, 5%, 0.063 W, 0402 402 RC0402JR-070RL Yageo America
R12 1 0 RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0603 603 ERJ-3GEY0R00V Panasonic
Schematic and Bill of Materials www.ti.com
10 PCM1802EVM and PCM1803AEVM Evaluation Module SBAU384 – JULY 2021
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