Texas Instruments PCM4201EVM Manual de usuario

User's Guide

SBAU108A–January 2005–Revised February 2005

PCM4201EVM User's Guide

This document provides the information needed to set up and operate the

PCM4201EVM evaluation module (EVM). For a more detailed description of the

PCM4201, please refer to the product datasheet available from the Texas Instruments

web site at www.ti.com. Additional support documents are listed in the section of this

guide entitled Related Documentation from Texas Instruments and Additional

Documentation. Throughout this document, the acronym EVM and the phrase

evaluation module are synonymous with the PCM4201EVM. This user’s guide

includes setup and configuration instructions, information regarding absolute operating

conditions, an electrical schematic, PCB layout drawings, and a bill of materials (BOM)

for the EVM.

Contents

1 Introduction .......................................................................................... 2

2 Getting Started ...................................................................................... 5

3 Hardware Description and Configuration ........................................................ 6

4 Schematic, PCB Layout, and Bill of Materials................................................. 10

List of Figures

1 PCM4201 Functional Block Diagram ............................................................ 2

2 PCM4201EVM Functional Block Diagram....................................................... 3

3 Transmitter Reset Circuitry ........................................................................ 9

4 PCM4201EVM Schematic ....................................................................... 11

5 Top Side Silkscreen .............................................................................. 12

6 Bottom Side Silkscreen........................................................................... 13

7 Top Layer (Component Side).................................................................... 14

8 Ground Layer ...................................................................................... 15

9 Power Plane Layer................................................................................ 16

10 Bottom Layer (Solder Side) ...................................................................... 17

List of Tables

1 Absolute Operating Conditions ................................................................... 5

2 System Clock Source Selection .................................................................. 7

3 Sampling Mode Selection ......................................................................... 7

4 Digital High-Pass Filter Configuration ........................................................... 7

5 Slave/Master Mode Configuration ............................................................... 8

6 System Clock Rates for Master Mode Operation .............................................. 8

7 System Clock Rates for Slave Mode Operation ............................................... 8

8 Digital Interface Transmitter Configuration ..................................................... 9

9 Transmitter Master Clock Configuration ........................................................ 9

10 PCM4201EVM Bill of Materials.................................................................. 18

PCM4201EVM User's GuideSBAU108A–January 2005 –Revised February 2005 1

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1 Introduction

HPF

Delta−Sigma

Modulator Decimation

Filter

Voltage

Reference

VREF+

VREF−

VINR+

VINR−

Power

VDD

AGND

Reset

Logic Clock

Control

Audio

Serial

Port

DGND

VCC

FSYNC

BCK

DATA

S/M

RATE

SCKI

RST

HPFD

1.1 PCM4201EVM Features

Introduction

The PCM4201 is a low power, high-performance, single channel audio analog-to-digital (A/D) converterdesigned for use in battery-operated or portable professional audio applications, including digital wirelessmicrophones and digital audio recorders/processors. The PCM4201 features a 24-bit linear PCM dataoutput, with a data format compatible with digital signal processors and digital audio interface transmitters(including the DIT4096 and DIT4192 from Texas Instruments).

The PCM4201 includes three sampling modes, supporting sampling rates up to 108kHz. The NormalSpeed Low Power mode supports sampling rates up to 54kHz, and employs 64x oversampling to reduceoverall converter power. The Normal Speed High Performance mode supports sampling rates up to 54kHzwith 128x oversampling, resulting in higher dynamic range than the Low Power mode, at the expense ofincreased power dissipation. The Double Speed mode supports sampling frequencies up to 108kHz, andis provided for those cases where higher sampling rates may be required.

A digital high-pass filter is included for DC removal. Dedicated control pins are included for sampling modeselection, Slave/Master mode port operation, digital high-pass filter enable/disable, and reset/power-downfunctions.

A +5V power supply is required for the analog section of the device, while a +3.3V power supply istypically utilized for the digital circuitry. The digital supply may operate at voltages as low as +1.8V, with acorresponding 10mW to 20mW reduction in power dissipation, depending upon the sampling modeselection. Figure 1 illustrates the functional block diagram for the PCM4201.

Figure 1. PCM4201 Functional Block Diagram

The PCM4201EVM provides a convenient platform for evaluating the performance and functions of thePCM4201 device. The primary EVM features include:•Simple configuration using an onboard DIP switch•Differential voltage input supporting 3-pin XLR or balanced TRS connections•Differential input buffer and filter circuit utilizing the Texas Instruments OPA2134 dual op amp•Flexible input buffer power supply connection (dual or single supply options) and resistor/capacitorconfiguration allow for circuit experimentation and op amp substitution

PCM4201EVM User's Guide2 SBAU108A – January 2005 – Revised February 2005

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1.2 PCM4201EVM General Description and Functional Block Diagram

Analog

Input

Analog

Input Buffer

PCM4201

Switch

SW1

DIT Circuitry

and

Clock Enables

22.5792M

EXT CLOCK INPUT

System

Clock

24.576M

S/M

OPA2134

GND

+5VA+15V

−15V

GND

+15V

GND

+5VA

U10

REG1117

+3.3V

+5VD

GND

EXT VDD

VDD

JMP4

BUF

S/M

PCM Data HDR J3

Audio

Serial Port

BUF

DIT

DIT4096

AES3 Output

Introduction

•Buffered audio serial port output supports connection to external DSP hardware or audio testequipment

•An onboard Texas Instruments DIT4096 provides an AES3-encoded digital output suitable for use withaudio test systems or commercial audio equipment, supporting output sampling rates up to 108kHz•Onboard crystal oscillators, operating at 22.5792MHz and 24.576MHz, support 44.1kHz, 48kHz,88.2kHz, and 96kHz sampling rates and all three sampling modes of the PCM4201•An external clock input allows operation at alternative sampling frequencies

As shipped, the PCM4201EVM requires +15V, –15V, and +5V analog power supplies. Options areprovided to operate the analog section from a single power supply by utilizing alternative op amps for theinput buffer circuit. A +5V digital supply is required, with a +3.3V digital supply being derived onboardusing a Texas Instruments REG1117 voltage regulator IC. Connections are provided for an external digitalsupply for the PCM4201, allowing digital operation down to +1.8V.

The PCM4201EVM provides a complete platform for evaluating the performance and features of thePCM4201 single channel audio A/D converter. Figure 2 illustrates the functional block diagram for theevaluation module.

Figure 2. PCM4201EVM Functional Block Diagram

PCM4201EVM User's GuideSBAU108A – January 2005 – Revised February 2005 3

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1.3 Related Documentation from Texas Instruments

1.4 Additional Documentation

Introduction

A differential analog input is supported at connector J1. The analog input supports either a 3-pin male XLRor balanced TRS input plug. The analog input is buffered and filtered using a low noise input circuit,utilizing a Texas Instruments' OPA2134 dual audio op amp IC. The output of the buffer circuit is connectedto the differential input of the PCM4201, which is then used to convert the analog signal to a 24-bit linearPCM representation in the digital domain.

The 24-bit PCM output data is made available at header J3. The audio data can also be routed to theDIT4096 digital interface transmitter, supporting an AES3-encoded output, which is provided at BNCconnector J5. The buffered header is convenient for interfacing to external development hardware ordigital signal processors, while the AES3-encoded outputs may be connected to audio test systems orcommercial audio equipment.

Power is connected to the board at either terminal block J2 for the analog supplies, or at terminal block J6for the digital supplies.

Manual reset circuits are provided for both the PCM4201 (U1) and the DIT4096 (U7). The ADC RESETswitch (SW2) is utilized for resetting the A/D converter, while the DIT RESET switch (SW3) is utilized forresetting the AES3 transmitter.

The system or master clock for the evaluation module may be generated onboard or by an external clocksource. Oscillators X1 and X2 operate at fixed clock frequencies of 22.5792MHz and 24.576MHz,respectively. The oscillators provide low jitter clock sources for measuring the performance of thePCM4201 in Master mode operation. Alternatively, an external clock source may be connected at J4 forMaster mode operation, supporting alternative sampling rates. For Slave mode operation, the systemclock is provided from an external source through header J3. Switch SW1 provides configuration controlfor the PCM4201, the DIT4096, the onboard oscillators, and the external clock input at connector J4.

The following documents provide information regarding Texas Instruments integrated circuits used in theassembly of the PCM4201EVM. The latest revisions of these documents are available from the TI website at www.ti.com .

Data Sheet Literature NumberPCM4201 Datasheet SBAS342DIT4096 Datasheet SBOS225OPA2134 Datasheet SBOS058REG1117 Datasheet SBVS001SN74ALVC245 Datasheet SCES271SN74LVC1G04 Datasheet SCES214SN74LVC1G08 Datasheet SCES217SN74LVC1G125 Datasheet SCES223

The following documents or references provide information regarding selected non-TI components used inthe assembly of the PCM4201EVM. These documents are available from the corresponding manufacturer.

Document/Reference ManufacturerSM7745H Series CMOS Oscillators Pletronics (http://www.pletronics.com )

PCM4201EVM User's Guide4 SBAU108A – January 2005 – Revised February 2005

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2 Getting Started

2.1 Electrostatic Discharge Warning

2.2 EVM Package Contents

2.3 Absolute Operating Conditions

Getting Started

This section provides information regarding handling, package contents, and absolute operating conditionsfor the PCM4201EVM.

CAUTIONFailure to observe proper ESD handling precautions may result in damageto EVM components.

Many of the components used in the assembly of the PCM4201EVM are susceptible to damage byelectrostatic discharge (ESD). Customers are advised to observe proper ESD handling procedure whenunpacking and handling the PCM4201EVM. All handling should be performed at an approved ESDworkstation or test bench, using a grounded wrist strap. Failure to observe proper handling procedure mayresult in damage to the EVM and/or the module components.

Upon opening the PCM4201EVM package, please check to make sure that these items are included:•One PCM4201EVM evaluation module•One printed copy of the PCM4201 product datasheet•One printed copy of this PCM4201EVM User’s Guide

If any of these items are missing, please contact the TI Product Information Center in your region.

CAUTIONExceeding the absolute operating conditions may result in damage to theevaluation module and/or the equipment connected to it.

The user should be aware of the absolute operating conditions for the PCM4201EVM. Table 1summarizes the critical data points.

Table 1. Absolute Operating Conditions

Min Max Units

Power Supplies

+15V +5.0 +18.0 V-15V -5.0 -18.0 V+5VA +4.5 +5.5 V+5VD +4.5 +5.5 VEXT VDD +1.8 +3.6 V

Audio Serial Port (J3)

, Input High Voltage 0.7 x V

+3.6 VV

, Input Low Voltage -0.3 0.3 x V

External Clock Input (J4)

, Input High Voltage 0.7 x V

+3.6 VV

, Input Low Voltage -0.3 0.3 x V

Analog Inputs (J1)

Input Voltage, Differential 0 18.5 V

PCM4201EVM User's GuideSBAU108A – January 2005 – Revised February 2005 5

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3 Hardware Description and Configuration

3.1 Power Supply Configuration

3.2 Analog Input

3.3 System Clock Configuration

Hardware Description and Configuration

This section provides hardware description and configuration information for the PCM4201EVM.

The PCM4201EVM requires three analog power supplies and one digital power supply for operation. Theanalog supplies are connected at terminal block J2, while the digital supply is connected at terminal blockJ6.

Analog supplies include +15V and –15V DC for powering the input buffer circuit, as well as +5.0V DC forpowering the analog section of the PCM4201. All supplies should be rated for at least 500mA of outputcurrent.

The digital supply requires +5.0V DC and should be rated for at least 500mA of output current. The +5.0Vsupply is regulated to +3.3V DC by an onboard Texas Instruments REG1117 linear voltage regulator(U10), which is used to power the digital section of the PCM4201 and the majority of the support logiccircuitry. The core logic and line driver sections of the AES3 transmitter (U7) utilize the +5.0V digitalsupply directly.

An optional external VDD power supply is supported at terminal block J6. Jumper JMP4 is utilized toselect either the onboard +3.3V voltage regulator (U10) or an external power source. Shorting pins 1 and2 together using the supplied jumper block selects the onboard +3.3V voltage regulator. Shorting pins 3and 4 together will select the external supply (EXT VDD) on terminal block J6. Only one source may beselected at any time.

The External VDD may be operated as low as +1.8V. However, the DIT4096 transmitter will only operateat voltages down to +2.0V. Use the audio serial port interface at header J3 when operating VDD atvoltages lower than +2.0V.

The PCM4201EVM includes a Neutrik combo XLR connector (J1), which accepts either a 3-pin male XLRor a 1/4-inch TRS phono plug. The analog input can accept up to a 18.5V

differential input signal. Thissignal is then attenuated by a factor of 3.7 by the input buffer circuit, which corresponds to the 5.0V

fullscale differential input voltage for the PCM4201 analog input.

The input buffer circuit is comprised of an OPA2134 dual audio operational amplifier and associatedpassive components. The input buffer provides active attenuation and low-pass filtering for the analoginput signal. The OPA2134 is biased to approximately +2.5V, with the bias voltage being derived from the+5V analog supply using a voltage divider.

The input buffer circuit may be configured to accept either dual or single supply op amps. Jumper JMP2allows the –15V supply to be shorted to ground. The +15V may then be adjusted to the appropriate singlesupply voltage for the op amp. When using a single supply op amp, it may be necessary to change thevalues of the buffer feedback and input resistors in order to adjust the gain or attenuation to match themaximum input/output voltage swing allowed by the single supply configuration.

The OSC1 and OSC2 elements of switch SW1 are utilized to select the system clock source for thePCM4201EVM. Table 2 summarizes the available options. The onboard oscillators support 44.1kHz,48kHz, 88.2kHz, and 96kHz sampling rates for Master mode audio serial port operation. Alternatively, theexternal clock input (J4) may be used to supply the system clock from an external source, supportingadditional sampling rates.

For Slave mode operation, the system clock is input at the SCKI pin of the audio serial port header (J3).

6 SBAU108A – January 2005 – Revised February 2005PCM4201EVM User's Guide

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3.4 Sampling Mode Selection

3.5 Digital High-Pass Filter

F3dB fS

48,000, where fSoutput sampling rate

Hardware Description and Configuration

Table 2. System Clock Source Selection

OSC2 OSC1 SYSTEM CLOCK SOURCE

LO HI X1, 22.5792MHzHI LO X2, 24.576MHzLO LO External Clock from connector J3 or J4

The PCM4201 supports three sampling modes, allowing the user to select the best power/performancecombination for a given application.

The Normal Speed Low Power mode provides the lowest overall power dissipation while supportingsampling rates up to 54kHz. The modulator oversampling rate is 64f

for this mode.

The Normal Speed High Performance mode provides the best dynamic performance at the expense ofincreased power dissipation. Sampling rates up to 54kHz are supported. The modulator oversampling rateis 128f

for this mode, improving the overall dynamic range and THD+N when compared to the LowPower mode.

The Double Speed mode supports sampling frequencies up to 108kHz with power dissipation just slightlyhigher than the Normal Speed High Performance mode. The modulator oversampling rate is 64f

for thismode.

The sampling mode is selected using the RATE VDD and RATE GND elements of switch SW1. Table 3shows the settings required for each sampling mode.

Table 3. Sampling Mode Selection

RATE VDD RATE GND SAMPLING MODE

OFF ON Double SpeedON OFF Normal Speed Low PowerOFF OFF Normal Speed High Performance

The PCM201 includes a digital high-pass filter, which is utilized to remove the DC component from thedigitized signal. The high-pass filter is located at the output of the digital decimation filter in the overall A/Dsignal chain. The –3dB corner frequency of the high-pass filter is set by the following relationship:

The digital high-pass filter may be enabled or disabled using the HPFD element of switch SW1. Table 4summarizes the HPFD switch settings. There may be a small increase distortion for low frequency inputs(less than 100Hz) when the high-pass filter is enabled.

Table 4. Digital High-Pass Filter Configuration

HPFD HIGH-PASS FILTER FUNCTION

LO EnabledHI Disabled

PCM4201EVM User's GuideSBAU108A – January 2005 – Revised February 2005 7

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3.6 Audio Serial Port Interface

3.7 Digital Interface Transmitter

Hardware Description and Configuration

The PCM4201EVM audio serial port is accessed at header J3. The port includes the audio bit clock(BCK), the audio frame synchronization clock (FSYNC), and the serial audio data (DATA). The systemclock (SCKI) is also available at the audio serial port. The audio serial port may be operated in Slave orMaster Mode.

In Slave Mode, the BCK, FSYNC, and SCKI clocks are inputs to the PCM4201EVM, and may be providedfrom an external source (DSP, FPGA, etc.) via header J3. The BCK and FSYNC clocks must besynchronous with one another and the audio data.

In Master Mode, the BCK, FSYNC, and SCKI clocks are outputs, being derived by the PCM4201 using theon-board crystal oscillators or external clock source applied at connector J4.

The Slave or Master Mode port configuration is programmed using the S/M element of switch SW1.Table 5 summarizes the available settings.

Table 5. Slave/Master Mode Configuration

S/M AUDIO SERIAL PORT SLAVE/MASTER MODE

LO MasterHI Slave

Slave or Master Mode audio serial port operation also dictates the required rate of the system clock(SCKI) supported for various sampling modes. A summary of the supported rates is shown in Table 6 andTable 7 .

Table 6. System Clock Rates for Master Mode Operation

SCKI RATE SAMPLING MODE WITH MASTER MODE AUDIO SERIAL PORT

512f

Normal Speed Low Power512f

Normal Speed High Performance256f

Double Speed

Table 7. System Clock Rates for Slave Mode Operation

SCKI RATE SAMPLING MODE WITH SLAVE MODE AUDIO SERIAL PORT

256f

or 512f

Normal Speed Low Power256f

or 512f

Normal Speed High Performance256f

Double Speed

A Texas Instruments DIT4096 digital interface transmitter provides an AES3-encoded output for thePCM4201EVM. The DIT and DITCLK elements of switch SW1 are utilized to configure the transmitter.The output of the transmitter is available at connector J5. This output is designed for use with 75 Ωcoaxialcable connections.

The transmitter is enabled using the DIT element of switch SW1. The DIT switch operation is summarizedin Table 8 .

8 SBAU108A – January 2005 – Revised February 2005PCM4201EVM User's Guide

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3.8 Reset Operations

To RST of U7

From DIT

VDD

SW4

N.O.

Hardware Description and Configuration

Table 8. Digital Interface Transmitter Configuration

DIT DIGITAL INTERFACE TRANSMITTER

LO EnabledHI Disabled

The audio data format for the transmitters is hardwired for 24-bit Left Justified data format. Only onechannel (Channel A of the AES3 stream) will carry 24-bit linear PCM audio data.

Like the PCM4201, the DIT4096 transmitters must be configured for the proper Master (or System) clockfrequency. The transmitter master clock is driven by the same source as the PCM4201 system clock, asdescribed in Section 3.3 of this document. The transmitter master clock rate selection must match thesystem clock rate selection for the PCM4201. Table 9 summarizes the master clock rate options for theDIT4096 transmitter using the DITCLK element of switch SW1.

Table 9. Transmitter Master Clock Configuration

DITCLK TRANSMITTER MASTER CLOCK RATE

LO 256f

HI 512f

The PCM4201EVM includes two reset switches, SW2 and SW3. Both are momentary contact, normallyopen pushbutton switches. Switch SW2 provides the manual reset for the PCM4201, while switch SW3provides the manual reset the DIT4096 digital interface transmitter.

The PCM4201 may be reset at any time by momentarily pressing and then releasing switch SW2. Thisgenerates a reset pulse and initiates a reset sequence for the device.

For the transmitter reset function, the output of the reset circuit is connected to the RST pin of theDIT4096 transmitter. The DIT4096 may be reset only when the DIT switch of SW1 is set LO bymomentarily pressing and then releasing switch SW3. If the DIT switch is set HI, the output of the ANDgate in the reset circuit is forced low, which will force the transmitter into power down mode. Thetransmitter reset circuit is shown in Figure 3 .

Figure 3. Transmitter Reset Circuitry

PCM4201EVM User's GuideSBAU108A – January 2005 – Revised February 2005 9

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4 Schematic, PCB Layout, and Bill of Materials

Schematic, PCB Layout, and Bill of Materials

This section provides the electrical schematic and physical layout information for the PCM4201EVM. Thebill of materials (BOM) is included as a component reference.

Note:

Board layouts are not to scale. These figures are intended to show how the board is laidout; they are not intended to be used for manufacturing PCM4201EVM PCBs.

PCM4201EVM User's Guide10 SBAU108A – January 2005 – Revised February 2005

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