Texas Instruments LMK05318B EVM Manual de usuario

SNAU253–June 2020

LMK05318B EVM

SNAU253–June 2020

LMK05318B EVM

1 Overview

The LMK05318B EVM is an evaluation module for the LMK05318B Network Clock Generator and

Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.

The EVM includes SMA connectors for clock inputs, oscillator inputs, and clock outputs to interface the

device with 50-Ωtest equipment. The device can be configured through I2C or SPI using the onboard

microcontroller. The graphic interface TICS Pro can be used to program the LMK05318B registers and on-

chip EEPROM.

2 Trademarks

All trademarks are the property of their respective owners.

3 Features

• LMK05318B DUT:

– DPLL with programmable loop bandwidth for input jitter and wander attenuation

– Two Analog PLLs (APLLs) for flexible low-jitter clock generation

– Two clock inputs supporting hitless switching and holdover

– Eight differential clock outputs, or combination of differential and up to eight LVCMOS clocks

– On-chip EEPROM for custom start-up clocks

• SMA ports for clock input, oscillator inputs, and clock outputs

• Onboard 48.0048-MHz XO and option to use external XO

• USB MCU interface for I2C/SPI and GPIO pin control using TICS Pro GUI

• Status LEDs for power supplies and device status indicators

4 What is Included

• LMK05318BBEVM

• Mini-USB cable

5 What is Needed

• Windows PC with TICS Pro Software GUI

• Test Equipment

– DC power supply (5 V, 1 A)

– Real-time oscilloscope

– Source signal analyzer

– Precision frequency counter

– Signal generator and reference clock

2SNAU253–June 2020

Submit Documentation Feedback

LMK05318B EVM User's Guide

User's Guide

SNAU253–June 2020

LMK05318B EVM User's Guide

1 EVM Quick Start

Follow below steps for EVM quick start:

1. Verify the jumper settings according to Table 1 and Figure 1.

2. Set up the board as shown in Figure 1.

3. Request, download and install Tics Pro: Texas Instruments Clocks and Synthesizers (TICS) Pro

Software. In Tics Pro, go to the page EVM Quick Start page and follow the instructions.

4. To start a new design, go to the Wizard page in Tics Pro.

Table 1. Jumper Settings

DESIGNATOR NAME DEFAUL

TDESCRIPTION

J2 REFSEL Tie pin 03 These jumpers control the voltage levels of corresponding pins of the DUT.

• Short pin 01 = pulled high

• Short pin 02 = controlled by software through onboard microcontroller

(USB2ANY)

• Short pin 03 = pulled low

J3 HW_SW_CTRL Tie pin 03

J7 GPIO0/SYNCN Tie pin 01

J8 GPIO1/SCS Tie pin 02

J5 GPIO2/SOMI Tie pin 02

J10 VDD Tie pins

1-2

This jumper decides whether the VDD pins are supplied by onboard LDO or

external power supply.

• Short pins 1-2: VDD is supplied by LDO.

• Short pins 2-3: VDD is supplied by VIN1 (external power supply).

J11 VDDO Tie pins

1-2

This jumper decides whether the VDDO pins are supplied by onboard LDO or

external power supply.

• Short pins 1-2: VDDO is supplied by LDO.

• Short pins 2-3: VDDO is supplied by VIN2 (external power supply).

J12 VDDO level Tie pin 03

This switch controls the VDDO level when VDDO is supplied by LDO.

• Short pin 01: VDDO = 1.8 V.

• Short pin 02: VDDO = 2.5 V.

• Short pin 03: VDDO = 3.3 V.

J9 XO VCC Tie pin 01 This jumper powers up or down the onboard XO.

• Short pins 1-2: VCC of onboard XO is connected to LDO.

• Short pins 2-3: VCC of onboard XO is tied to ground.

J4 I2C/SPI Tie pin

01,

pin 02

This jumper selects between I2C and SPI interface.

• To use I2C, short pin 01, pin 02 and leave other pins open.

• To use SPI, short pin 04, pin 05, pin 06, pin 07, and leave other pins open.

VIN1 = 5V

VIN2 unused

25 MHz Signal

for PRIRE

Oscilloscope

On-board

48.0048 MHz XO

www.ti.com

Device Start-Up Modes

SNAU253–June 2020

LMK05318B EVM User's Guide

Figure 1. LMK05318B EVM with Default Jumper Settings

2 Device Start-Up Modes

The LMK05318B can start-up in one of three modes depending on the 3-level input level sampled on the

HW_SW_CTRL pin upon power-on reset (POR). The start-up modes are listed in Table 2

EVM Configuration

www.ti.com

4SNAU253–June 2020

Submit Documentation Feedback

LMK05318B EVM User's Guide

(1) The input levels on these pins are sampled only during POR.

(2) FINC and FDEC pin controls are only available when DCO mode and GPIO pin control are enabled by registers.

Table 2. Device Start-Up Modes

HW_SW_CTRL(

INPUT LEVEL

START-UP

MODE MODE DESCRIPTION JUMPER CONFIGURATION

0EEPROM + I2C

(Soft pin mode)

Registers are initialized from EEPROM, and I2C interface is

enabled with slave address 11001xxb. Logic pins:

• SDA/SDI, SCL/SCK: I2C Data, I2C Clock

• GPIO0/SYNCN: Output Sync (active low)

• GPIO1/SCS(1): I2C Address LSB Select (Low = 00b,

Float = 01b, High = 10b)

• GPIO2/SDO/FINC(2): DPLL DCO Frequency Increment

(active high)

• STATUS1/FDEC(2): DPLL DCO Frequency Decrement

(active high), or Status output

To select this mode, short pin

03 of J3.

Configure the jumpers for I2C

mode:

1. For J4, short pin 01, pin 02

and leave other pins open.

2. For J5 and J8, short pin

02.

Float

(VIM)EEPROM +

SPI

(Soft pin mode)

Registers are initialized from EEPROM, and SPI interface is

enabled. Logic pins:

• SDA/SDI, SCL/SCK: SPI Data In (SDI), SPI Clock (SCK)

• GPIO0/SYNCN: Output Sync (active low)

• GPIO1/SCS: SPI Chip Select (SCS)

• GPIO2/SDO/FINC: SPI Data Out (SDO)

To select this mode, short pin

02 of J3.

Configure the jumpers for SPI

mode:

1. For J4, short pin 04, pin

05, pin 06, pin 07 and

leave other pins open.

1ROM + I2C

(Hard pin

mode)

Registers are initialized from the ROM page selected by

GPIO pins, and I2C interface is enabled with the 7-bit slave

address of 0x64. Logic pins:

• SDA/SDI, SCL/SCK: I2C Data, I2C Clock

• GPIO[2:0]: ROM page select at POR

• After POR, GPIO2/SDO/FINC and STATUS1/FDEC pins

can function the same as for HW_SW_CTRL = 0 if

enabled by registers.

To select this mode, short pin

03 of J3. Configure jumpers J7,

J8 and J5 to set voltage levels

of GPIO0, GPIO1 and GPIO2.

NOTE: To ensure proper start-up into EEPROM + SPI Mode, the HW_SW_CTRL, STATUS0, and

STATUS1/FDEC pins must all be floating or biased to VIM (0.8-V typical) before the PDN pin

is pulled high. These three pins momentarily operate as 3-level inputs and get sampled at

the low-to-high transition of PDN to determine the device start-up mode during POR. If any of

these pins are connected to a host device (MCU or FPGA), TI recommends using external

biasing resistors on each pin (10-kΩpullup to 3.3 V with 3.3-kΩpulldown to GND) to set the

inputs to VIM during POR. After power-up, the STATUS pins can operate as LVCMOS

outputs and overdrive the external resistor bias for normal status operation.

3 EVM Configuration

3.1 Power Supply

The LMK05318B has five core VDD supply pins that operate at 3.3 V ± 5% and six output VDDO supply

pins that operate at 1.8 V, 2.5 V, or 3.3 V ± 5%.

• To use onboard LDO, short pins 1-2 of J10 and short pins 1-2 of J11. Then supply 5 V power source to

J35 or VIN1 of J13. The VDDO level can be set by J12 (short pin 01 = 1.8 V, short pin 02 = 2.5 V,

short pin 03 = 3.3 V).

• To use external power supply, short pins 2-3 of J10 and short pins 2-3 of J11. Then supply 3.3 V to

J35 or VIN1 of J13, and supply 1.8 V, 2.5 V or 3.3 V to J37 or VIN2 of J13.

• To power up or power down the onboard XO, short pins 1-2 or pins 2-3 of J9.

3.2 Logic Inputs and Outputs

See Table 1 to set voltage levels for GPIO pins.

www.ti.com

EVM Configuration

SNAU253–June 2020

LMK05318B EVM User's Guide

Table 3. Logic Pin Descriptions - EEPROM + I2C Mode (HW_SW_CTRL = 0)

PIN NAME (TYPE) DESCRIPTION

PDN

(2-level input)

Chip Power-Down/Reset (active low)

When PDN rises to 1, the digital control block triggers the internal POR sequence, initializes all the registers

and logic pins for the start-up mode selected by the HW_SW_CTRL input level, restores all the internal

circuits including the serial interface to their initial state, and begins normal operation.

This pin is pulled high through internal pullup resistor, but can be pulled down by pushing toggle switch S2.

PDN STATE S2 CHIP STATE

0 Pushed Power-down/reset state: Serial interface disabled

1 (Default) Released Normal operation

GPIO0/SYNCN

(2-level input)

Output Synchronization (active low)

GPIO0 (SYNCN) can be used to mute the output clocks and trigger output divider synchronization (SYNC) if

the divider SYNC bits are enabled by registers. Alternatively, SYNC can be triggered through register

programming instead of using this pin.

GPIO0 STATE J7 OUTPUT SYNC STATE

0 Tie pin 03 SYNC asserted: Outputs muted and output dividers held

in reset

1 (Default) Tie pin 01 SYNC deasserted: Normal output operation

GPIO1/SCS

(3-level input)

I2C Slave Address LSB Select

GPIO1 is sampled on POR to configure the lower 2 bits of the 7-bit I2C address after start-up. The upper 5

bits of the I2C address are initialized from EEPROM (SLAVEADR[7:3] = 11001b).

GPIO1 STATE J8 7-BIT SLAVE ADDRESS

0 (Default) Tie pin 03 1100100b (0x64h)

Float Leave all pins open 1100101b (0x65h)

1 Tie pin 01 1100111b (0x66h)

GPIO2/SDO/FINC

(2-level input)

DPLL DCO Mode Frequency Increment (FINC)

When DCO mode and GPIO pin control are enabled by registers, a high pulse on the FINC input will

increment the DCO numerator by the programmable frequency deviation (FDEV) step size to adjust its

frequency.

FINC STATE J5 DPLL DCO NUMERATOR

0 Tie pin 02 for GPIO2 to

be controlled by the

MCU

No update

1 (Pulsed by MCU pin) Incremented

REFSEL

(2-level inputs)

DPLL Reference Clock Input Selection

The REFSEL pin selects the DPLL reference clock input when Manual Input Select mode and HW Pin

Control mode are selected by register configuration. This pin is ignored when Auto Input Select mode or SW

REFSEL STATE J2 DPLL REF INPUT

0 (Default) Tie pin 03 PRIREF

Float Leave all pins open Auto Select

1 Tie pin 01 SECREF

STATUS0,

STATUS1/FDEC

(Logic outputs)

Status Outputs

Each STATUS pin is a programmable status output that supports NMOS open-drain or 3.3-V LVCMOS

driver type. The output states of STATUS0 and STATUS1 are shown on active-high LEDs D4 and D5,

respectively.

DPLL DCO Mode Frequency Decrement (FDEC)

When DCO mode and GPIO pin control are enabled by registers, a high pulse on the FDEC input will

decrement the DCO numerator by the programmable frequency deviation (FDEV) step size to adjust its

frequency.

FDEC STATE N/A DPLL DCO NUMERATOR

0 STATUS1/FDEC is

always controlled by the

MCU

No update

1 (Pulsed by MCU pin) Decremented

EVM Configuration

www.ti.com

6SNAU253–June 2020

Submit Documentation Feedback

LMK05318B EVM User's Guide

(1) When HW_SW_CTRL = Float, STATUS[1:0] pins must not be pulled high or low externally during POR to ensure proper start-up

into EEPROM+SPI Mode.

Table 4. Logic Pin Descriptions - EEPROM + SPI Mode (HW_SW_CTRL = Float)

PIN NAME (TYPE) DESCRIPTION

GPIO1/SCS

(2-level input) SPI Chip Select (SCS)

See Table 2.

GPIO2/SDO/FINC

(2-level input) SPI Data Out (SDO / SOMI)

See Table 2

STATUS0,

STATUS1

(Logic outputs)

Status Outputs

Each STATUS pin is a programmable status output that supports NMOS open-drain or 3.3-V LVCMOS

driver type. The output states of STATUS0 and STATUS1 are shown on active-high LEDs D4 and D5,

respectively. (1)

(1) In ROM + I2C Mode, the two I2C address LSBs are forced to 00b (address = 0x64h).

Table 5. Logic Pin Descriptions - ROM + I2C Mode (HW_SW_CTRL = 1)(1)

PIN NAME (TYPE) DESCRIPTION

GPIO[2:0]

(2-level inputs)

GPIO[2:0] Function at POR: ROM Page Selection

GPIO[2:0] pins are sampled on POR to select the ROM page settings used to initialize the registers.

The GPIO[2:0] pins are controlled by J5, J8 and J7, respectively.

GPIO2 Function after POR: DPLL DCO Mode Frequency Increment (FINC)

After POR, the GPIO2 pin can be operated as an FINC input in the same way described for EEPROM + I2C

mode (see the GPIO2/FINC description in Table 3).

GPIO[2:0] STATES ROM PAGE SELECT

000b (Default) ROM Page 0

001b ROM Page 1

010b ROM Page 2

... ...

110b ROM Page 6

111b ROM Page 7

STATUS0,

STATUS1/FDEC

(Logic outputs)

Status Outputs

Each STATUS pin is a programmable status output that supports NMOS open-drain or 3.3-V LVCMOS

driver type. The output states of STATUS0 and STATUS1 are shown on active-high LEDs D4 and D5,

respectively.

DPLL DCO Mode Frequency Decrement (FDEC)

After POR, the STATUS1 pin can be operated as an FDEC input in the same way described in Table 3.

www.ti.com

EVM Schematics

SNAU253–June 2020

LMK05318B EVM User's Guide

4 EVM Schematics

Figure 2. Schematic 1 - Power Supply

EVM Schematics

www.ti.com

8SNAU253–June 2020

Submit Documentation Feedback

LMK05318B EVM User's Guide

Figure 3. Schematic 2 - Power Distribution

www.ti.com

EVM Schematics

SNAU253–June 2020

LMK05318B EVM User's Guide

Figure 4. Schematic 3 - LMK05318B and XO Input Interfaces

EVM Schematics

www.ti.com

10 SNAU253–June 2020

Submit Documentation Feedback

LMK05318B EVM User's Guide

Figure 5. Schematic 4- Clock Input Interfaces

Otros manuales para LMK05318B EVM

Tabla de contenidos

Otros manuales de Placa madre de Texas Instruments

Texas Instruments

Texas Instruments DAC3XJ8XEVM Manual de usuario

Texas Instruments

Texas Instruments DEM-OPA-SC-1A-EVM Manual de usuario

Texas Instruments

Texas Instruments OMAP-L137 EVM Manual de usuario

Texas Instruments

Texas Instruments DRV8328 EVM Series Manual de usuario

Texas Instruments

Texas Instruments ADS8568EVM-PDK Manual de usuario

Texas Instruments

Texas Instruments DRV8303EVM Manual de usuario

Texas Instruments

Texas Instruments LM5108EVM Manual de usuario

Texas Instruments

Texas Instruments DS125DF111EVM Manual de usuario

Texas Instruments

Texas Instruments DLP LightCrafter Display 4710 EVM Manual de usuario

Texas Instruments

Texas Instruments ADS1261EVM Manual de usuario

Texas Instruments

Texas Instruments ADS62PXXEVM Manual de usuario

Texas Instruments

Texas Instruments TPSF12C3QEVM Manual de usuario

Texas Instruments

Texas Instruments UCC25660 Series Manual de usuario

Texas Instruments

Texas Instruments DAC5668 Manual de usuario

Texas Instruments

Texas Instruments TPA3128D2 Manual de usuario

Texas Instruments

Texas Instruments DS90UB95x-Q1 Manual de usuario

Texas Instruments

Texas Instruments TPS389006Q1EVM Manual de usuario

Texas Instruments

Texas Instruments TPS53819A Manual de usuario

Texas Instruments

Texas Instruments AMC1210MB-EVM Manual de usuario

Texas Instruments

Texas Instruments ADS1x20EVM Manual de usuario

Texas Instruments

Texas Instruments TLV320AIC13EVM Manual de usuario

Texas Instruments

Texas Instruments TPS65033-Q1 Series Manual de usuario

Texas Instruments

Texas Instruments ADC DJ 00SE Series Manual de usuario

Texas Instruments

Texas Instruments TPS54231 Manual de usuario

Manuales populares de Placa madre de otras marcas

DFI

DFI SD170 Manual de usuario

ASROCK

ASROCK ROMED8-2T Manual de usuario

Asus

Asus P2L97A Manual de usuario

Winmate

Winmate IC70 Manual de usuario

Asus

Asus MES-B Manual de usuario

Grantech

Grantech SYS8F377VGGA-3OMN Manual de usuario

Telit Wireless Solutions

Telit Wireless Solutions SL869-3DR Manual de usuario

Gigabyte

Gigabyte GA-9IVDT Manual de usuario

Commell

Commell MS-C73 Manual de usuario

IBT Technologies

IBT Technologies MB860 Manual de usuario

Nvidia

Nvidia TEGRA DG-04927-001_V01 Manual de usuario

Biostar

Biostar M7VIT Bravo Instrucciones de funcionamiento e instalación

Intel

Intel D33217CK Manual de usuario

Asus

Asus F1A55-M LX PLUS R2.0 Manual de usuario

EPC

EPC EPC9147C Manual de usuario

Asus

Asus EX-B760M-V5 D4 Manual de usuario

EPOX

EPOX MU-8KHA0010 Manual de usuario

Ski-Doo

Ski-Doo Bombardier MPEM 219 700 090 Manual de usuario