Texas Instruments DS110DF111EVM Manual de usuario

DS110DF111EVM Evaluation Board

User's Guide

Literature Number: SNLU142A

May 2014–Revised January 2016

2SNLU142A–May 2014–Revised January 2016

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Table of Contents

Contents

1 Overview............................................................................................................................. 4

2 Features.............................................................................................................................. 5

3 Applications ........................................................................................................................ 5

4 Ordering Information............................................................................................................ 5

5 Setup.................................................................................................................................. 6

5.1 Pin Control Mode......................................................................................................... 6

5.2 SMBus Slave Mode...................................................................................................... 9

5.3 EEPROM Mode......................................................................................................... 12

6 EVM Layout ....................................................................................................................... 13

7 Schematic ......................................................................................................................... 14

8 Bill of Materials .................................................................................................................. 15

9 Example Waveforms........................................................................................................... 16

Revision History.......................................................................................................................... 18

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SNLU142A–May 2014–Revised January 2016

List of Figures

1 DS110DF111EVM........................................................................................................... 4

2 4-Level IO Control on EVM................................................................................................. 6

3 DS1xxDF111EVM Slave Mode Full Setup ............................................................................... 9

4 DS1xxDF111EVM Slave Mode Close-Up ................................................................................ 9

5 DS110DF111 High Level Page........................................................................................... 10

6 DS110DF111 Low Level Page ........................................................................................... 11

7 DS110DF111 Eye Monitor Page......................................................................................... 11

8 DS110DF111 EEPROM Hex File Generation Page................................................................... 12

9 Top Assembly Layer....................................................................................................... 13

10 Bottom Assembly Layer .................................................................................................. 13

11 10.3125 Gbps Output Waveform......................................................................................... 16

12 10.3125 Gbps RjDj Jitter Decomposition................................................................................ 17

List of Tables

1 Four-Level Logic Settings................................................................................................... 6

2 DS110DF111 VOD Levels.................................................................................................. 7

3 DS110DF111 DEM Levels.................................................................................................. 7

4 DS110DF111 Loopback Control........................................................................................... 8

5 SMBus Write Address Assignment ...................................................................................... 10

4SNLU142A–May 2014–Revised January 2016

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User's Guide

SNLU142A–May 2014–Revised January 2016

DS110DF111EVM Evaluation Board

1 Overview

The DS110DF111EVM – SMA evaluation kit provides a complete high band-width platform to evaluate the

signal integrity and signal conditioning features of the Texas Instruments signal conditioning products –

with Equalization and De-emphasis.

SMA edge launch connectors are used as the input and the output connections for this evaluation board.

Commercially available adaptor boards can be purchased to facilitate connection to cables or backplane

interconnects.

Figure 1. DS110DF111EVM

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Features

SNLU142A–May 2014–Revised January 2016

DS110DF111EVM Evaluation Board

2 Features

• Fully Adaptive CTLE up to 34 dB Boost

• Self-tuning 5-tap DFE

• Adjustable Receive Equalization

• Raw Equalized and Re-timed Data Loopback

• Adjustable Transmit VOD: 600 – 1300 mVp-p

• Settable Transmit De-emphasis Driver to -12 dB

• Low Power Consumption: 200 mW/Channel

• Locks to Half/Quarter/Eighth Data Rates for Legacy Support

• On-chip Eye Monitor (EOM), PRBS Generator

• Input Signal Detection, CDR Lock Detection/Indicator

• Programmable via Pin Selection or SMBus Interface

• Single Supply Operation: VIN = 3.3 V±10% or VDD = 2.5 V ±5%

• -40°C to +85°C Operation

• High Speed Signal Flow–thru Pin-out Package – RTW: 24-pin QFN (4 mm x 4 mm, 0.5 mm Pitch)

3 Applications

• Front Port Optical Interconnects

• SFF-8431

• 10G/1G Ethernet

• CPRI

4 Ordering Information

EVM ID DEVICE ID DEVICE PACKAGE

DS110DF111EVM DS110DF111SQ 24WQFN

HIGH

SIGNAL

RESISTOR

SIGNAL

LOW

4-LEVEL CONTROL

HIGH RESISTOR FLOAT LOW

PIN HEADER CONNECTION

Setup

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DS110DF111EVM Evaluation Board

5 Setup

This section describes the jumpers and connectors on the EVM, as well and how to properly connect, set

up and use the DS110DF111EVM.

The DS110DF111EVM – SMA evaluation kit can be used in three different modes.

1. Pin Control Mode – provides access to selected signal integrity settings.

2. SMBus Slave Mode – full access to signal integrity and control settings.

3. EEPROM Mode – full access to signal integrity and control settings. EEPROM mode is a convenient

method of programming one or more DS110DF111 devices on system power-up when a SMBus

master (micro-controller or similar) is unavailable in the design.

This EVM and documentation focus on Pin Control and SMBus Slave Mode to highlight the ease-of-use

and excellent low-jitter performance of the DS110DF111.

5.1 Pin Control Mode

In Pin Control Mode, the external control pins on the DS110DF111 are used to configure the signal

integrity and control settings of the device. In this mode only a subset of the VOD and de-emphasis

(DEMA/B) levels are available. Due to the limited number of control pins, a limited bandwidth 4-level input

scheme has been implemented across the control pin interface. This allows for improved DE and VOD

control with fewer physical pins.

The 4 levels are defined below:

Table 1. Four-Level Logic Settings

Level Input Pin Setting

Low - 0 1 kΩto GND

Resistor - R 20 kΩto GND

Float - F Open

High - 1 1 kΩto VDD

The EVM interfaces to this 4-level IO using the setup below. Only one shunt connection is required to

access any of the 4 levels. This methodology minimizes the risk of improper connections that could

damage the board or board power supply.

Figure 2. 4-Level IO Control on EVM

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Setup

SNLU142A–May 2014–Revised January 2016

DS110DF111EVM Evaluation Board

5.1.1 Pin Control Mode Configuration

The DS110DF111EVM is shipped ready to use in pin control mode. The EVM will require the following

power supply inputs and jumpers.

1. J17 - GND

2. J19 – VIN to VIH : 3.3 V supply operation, 2.5 V internal regulator is enabled

3. J15 – VIN = 3.3 V: Use internal regulator to convert 3.3 V supply to internal supply level of 2.5 V

NOTE: The 2.5 V level may be observed on J18 (VDD) or the device VDD pins. While in 3.3 V mode,

J18 (VDD) is a regulated output voltage. Do not connect a 2.5 V supply to this pin.

4. J3 – ENSMB = 1 kΩto GND (L): Pin Control Mode

5. J6 - Loopback = 1 kΩto VIN (H): Normal operation, INA - to - OUT A and INB - to - OUT B

6. J91 - VODA = 1 kΩto GND (L): 600 mV output VOD on OUT A

7. J10 - VODB = 1 kΩto GND (L): 600 mV output VOD on OUT B

8. J41 - DEMA = 1 kΩto GND (L): 0 dB De-emphasis on OUT A

9. J51 - DEMB = 1 kΩto GND (L): 0 dB De-emphasis on OUT B

10. J161 - LOCK: With shunt installed LOCK LED will light Green when DS110DF111 CDR is in the

locked state

5.1.2 VOD and De-Emphasis

The DS110DF111 silicon uses pin strapping to define the VOD and DE level of the outputs. See Table 2

and Table 3 for a complete list of VOD and DE settings.

Table 2. DS110DF111 VOD Levels

VODA/B Bit 2,

sel_vod[2] Bit 1,

sel_vod[1] Bit 0,

sel_vod[0] Output VOD (mVppd)

0 0 0 0 600

R0 0 1 700

0 1 0 800

0 1 1 900

F 1 0 0 1000

11 0 1 1100

1 1 0 1200

1 1 1 1300

Table 3. DS110DF111 DEM Levels

DEMA/B Reg 0x15

Bit [2] Reg 0x15

Bit [1] Reg 0x15

Bit [0] Reg 0x15

Bit [6] De-Emphasis (dB)

00 0 0 0 0.0

0 0 1 1 -0.9

0 0 1 0 -1.5

0 1 0 1 -2.0

0 1 1 1 -2.8

1 0 0 1 -3.3

0 1 0 0 -3.5

1 0 1 1 -3.9

1 1 0 1 -4.5

0 1 1 0 -5.0

1 1 1 1 -5.6

Setup

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Table 3. DS110DF111 DEM Levels (continued)

DEMA/B Reg 0x15

Bit [2] Reg 0x15

Bit [1] Reg 0x15

Bit [0] Reg 0x15

Bit [6] De-Emphasis (dB)

1 0 0 0 -6.0

1 0 1 0 -7.5

1 1 0 0 -9.0

1 1 1 0 -12.0

5.1.3 Equalization

There are no pin control settings for the input Equalization. The DS110DF111 input equalization will

automatically adapt for divide ratios 1 and 2. For divide ratios 4 and 8 a pre-set equalization level is used.

5.1.4 Loopback

J6 and J61 control the DS110DF111EVM loopback function according to Table 4.

Table 4. DS110DF111 Loopback Control

Loopback Mode of Operation IN A IN B

0 Loopback Output B Output A

R Fanout Input A Output A Output A

F Fanout Input B Output B Output B

1 Normal Operation Output A Output B

5.1.5 LOS and LOCK

• LOS Function: The LOS function monitors the Input of Channel A for a valid signal. When there is a

valid signal on Input A the LED will light up. Channel B does not have any effect on the LOS output

signal.

• LOCK Function: The LOCK function monitors both Channel A and Channel B for a valid Lock

condition. If either channel has a valid Lock the LED will light up.

DPS-DONGLE-EVM

SMBus Pin Headers

SCL | SDA | GND

DS1xxDF111EVM

SMBus Pin Headers

SCL

SDA

GND

DPS-DONGLE-EVM

DS1xxDF111EVM

PC running either DS110DF111 or

DS125DF111 profile in SigCon Architect

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Setup

SNLU142A–May 2014–Revised January 2016

DS110DF111EVM Evaluation Board

5.2 SMBus Slave Mode

The SMBus can also be used to control DS110DF111 devices. This method has the advantage of

independent channel control and finer signal conditioning granularity.

1. J17 – GND

2. J19 – VIN to VIH: 3.3 V supply operation (2.5 V internal regulator is enabled)

3. J15 – VIN = 3.3V: Use internal regulator to convert 3.3 V supply to internal supply level of 2.5 V

NOTE: The 2.5V level may be observed on J18 (VDD) or the device VDD pins. While in 3.3 V mode,

J18 (VDD) is a regulated output voltage. Do not connect a 2.5V supply to this pin.

4. Floating the AD[1:0] inputs will result in an SMBus Address = 00 = 30’h

5. J3 – ENSMB = H: SMBus Slave Mode

6. Connect the board signals SDA, SCL, and GND on J20 to a DPS-DONGLE-EVM or an equivalent

USB2ANY device. A pull-up resistor is needed on the SMBus clock and data signals; place jumpers on

pins 1-2 of J4 and J5 to connect a 1 kΩpull-up resistor to SCL and SDA. The address line settings on

J16 (ADR0) and J10 (ADR1) are pin strap settings which get latched on power up and retain their

value until the DS110DF111 is power cycled.

7. The DS110DF111's control and signal integrity settings are programmable with SigCon Architect, a

GUI which supports full register access through SMBus communication. An example of a

DS1xxDF111EVM connected to a PC through a DPS-DONGLE-EVM is shown in Figure 3 and

Figure 4. The possible SMBus address settings are shown in Table 5. For more information about

SigCon Architect, reference the "SigCon Architect: Installation and Starter's Guide" (SNLU178).

Figure 3. DS1xxDF111EVM Slave Mode Full Setup Figure 4. DS1xxDF111EVM Slave Mode Close-Up

Setup

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(1) A floating ADDR[1:0] pin at power-up will be interpreted as a logic 0.

Table 5. SMBus Write Address Assignment(1)

ADDR1 ADDR0 SMBus Write SMBus Read

0 0 0x30 0x31

0 1 0x32 0x33

1 0 0x34 0x35

1 1 0x36 0x37

5.2.1 Register Architecture and Bit Fields

There are two types of device registers in the DS110DF111. These are the Control/Share Registers and

the Channel Registers. The Control/Share Registers control or allow observation of settings which affect

the operation of all channels of the DS110DF111. They are also used to select which channel of the

device is to be the target channel for reads from and writes to the Channel Registers.

The Channel Registers are used to set all the configuration settings of the DS110DF111. They provide

independent control for each channel of the DS110DF111 for all the configurable device characteristics.

Any registers not described in the datasheet tables should be treated as Reserved. The user should not

try to write new values to these registers. The user-accessible registers described in the datasheet provide

a complete capability for customizing the operation of the DS110DF111 on a channel-by-channel basis.

Many of the registers in the DS110DF111 are divided into bit fields. This allows a single register to serve

multiple purposes, which may be unrelated. Often configuring the DS110DF111 requires writing a bit field

that makes up only part of a register value while leaving the remainder of the register value unchanged.

5.2.2 Using SigCon Architect

SigCon Architect can be used to program the DS110DF111EVM. In order to use SigCon Architect for

SMBus Slave Mode access control, a DPS-DONGLE-EVM (see SNLU184) or USB2ANY equivalent

adapter board must be used. This adapter board serves as an interface board to allow SMBus

communication between the PC and the DS110DF111 retimer. The SigCon Architect GUI features high

level control, low level register bit level control, and an Eye Monitor page to program the device. Examples

of these pages are shown in the following figures.

Figure 5. DS110DF111 High Level Page

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