Texas Instruments UCC21520EVM-286 Manual de usuario

Using the UCC21520EVM-286, UCC20520EVM-

286, UCC21521CEVM-286, and UCC21530EVM-

286

User's Guide

Literature Number: SLUUBG8B

June 2016–Revised November 2018

2SLUUBG8B–June 2016–Revised November 2018

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Table of Contents

Contents

1 Trademarks......................................................................................................................... 4

2 Introduction......................................................................................................................... 4

3 Description.......................................................................................................................... 4

3.1 Features................................................................................................................... 5

3.2 I/O Description............................................................................................................ 5

3.3 Jumpers (Shunt) Setting ................................................................................................ 6

4 Electrical Specifications........................................................................................................ 6

5 Test Summary ..................................................................................................................... 7

5.1 Definitions................................................................................................................. 7

5.2 Equipment................................................................................................................. 7

5.3 Equipment Setup......................................................................................................... 7

6 Power-Up and Power-Down Procedure ................................................................................. 10

6.1 Power Up ................................................................................................................ 10

6.2 Power Down............................................................................................................. 10

7 Test Waveforms (CL=0pF) With Different DT Configurations .................................................... 11

7.1 DT Connected to VCCI(J-DT Option B in ).......................................................................... 11

7.2 DT Pin Floating or Left Open (J-DT Option A in ).................................................................. 11

7.3 DT Pin Connected to RDT (J-DT Option C in )..................................................................... 12

8 Schematic ......................................................................................................................... 13

9 Layout Diagrams................................................................................................................ 14

10 List of Materials ................................................................................................................. 16

Revision History.......................................................................................................................... 17

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SLUUBG8B–June 2016–Revised November 2018

List of Figures

1 Jumpers Installation Position............................................................................................... 8

2 Bench Setup Diagram and Configuration................................................................................. 9

3 Example Input and Output Waveforms (Channels 3 and 4 are PWM Inputs, Channels 1 and 2 are Outputs) 10

4 Overlap is Allowed When DT Connected to VCCI (Channels 3 and 4 are PWM Inputs, Channels 1 and 2

are Driver Outputs) ........................................................................................................ 11

5 Test Waveforms if DT is Left Open (Channel 3 and 4 are PWM Inputs, and Channel 1 and 2 are Driver

Outputs) ..................................................................................................................... 11

6 Test Waveforms if DT Connected to RDT (Channel 3 and 4 is PWM Inputs, and Channel 1 and 2 is Driver

Outputs) ..................................................................................................................... 12

7 UCC21520EVM-286 Schematic.......................................................................................... 13

8 Top Overlay................................................................................................................. 14

9 Top Layer.................................................................................................................... 14

10 Bottom Layer................................................................................................................ 15

11 Bottom Overlay ............................................................................................................. 15

List of Tables

1 Jumpers Setting.............................................................................................................. 5

2 Jumpers Setting.............................................................................................................. 6

3 UCC2x5xxEVM-286 Electrical Specifications............................................................................ 6

4 Two-Channel Function Generator Settings............................................................................... 8

5 Oscilloscope Settings ....................................................................................................... 8

6 UCC2x5xxEVM-286 List of Materials.................................................................................... 16

4SLUUBG8B–June 2016–Revised November 2018

Submit Documentation Feedback

Using the UCC21520EVM-286, UCC20520EVM-286, UCC21521CEVM-286,

and UCC21530EVM-286

User's Guide

SLUUBG8B–June 2016–Revised November 2018

Using the UCC21520EVM-286, UCC20520EVM-286,

UCC21521CEVM-286, and UCC21530EVM-286

UCC2x5xxEVM-286 evaluation modules are designed for evaluation of TI's 5.7-kVRMS isolated dual-

channel gate driver family with 4-A source and 6-A sink peak current for driving Si MOSFETs, IGBTs and

WBG devices such as SiC and GaN transistors. This user's guide covers the UCC21520EVM-286,

UCC20520EVM-286, UCC21521CEVM-286, and UCC21530EVM-286 used to evaluate the

UCC21520DW, UCC20520DW, UCC21521CDW, and UCC21530DWK, respectively. To evaluate other

Iso-Drivers in the UCC2x5xx family, TI recommends that the user read the data sheet thoroughly before

switching the part in the EVMs covered by this user guide. In this user guide, the UCC21520EVM-286

evaluation module is shown as the primary example, and the key differences between the

UCC21520EVM-286 and the UCC20520EVM-286, UCC21521CEVM-286, and UCC21530EVM-286 will be

highlighted accordingly.

SPACER

1 Trademarks

All trademarks are the property of their respective owners.

2 Introduction

Developed for high voltage applications where isolation and reliability is required, the UCC2x5xx delivers

reinforced isolation of 5.7 kVRMS and a surge immunity tested up to 12.8 kV along with a common-mode

transient immunity (CMTI) greater than 100 V/ns. It has the industry’s fastest propagation delay of 19 ns

and the tightest channel-to-channel delay matching of less than 5 ns to enable high-switching frequency,

high-power density, and efficiency.

The flexible, universal capability of the UCC2x5xx with up to 18-V VCCI and 25-V VDDA/VDDB allows the

device to be used as a low-side, high-side, high-side/low-side, or half-bridge drivers with dual PWM input

or single PWM input. With its integrated components, advanced protection features (UVLO, dead time and

enable/disable), and optimized switching performances, the UCC2x5xx enables designers to build smaller,

more robust designs for enterprise, telecom, automotive, and industrial applications with a faster time to

market.

3 Description

The UCC2x5xx evaluation board has three independent screw terminal blocks for VCCI, VDDA, and

VDDB. The 3-position headers with jumpers for all the key input signals, such as PWM INPUTs (INA, INB

or PWM), dead time (DT) programming and enable/disable function (EN/DIS), allow designers to easily

evaluate different protection functions. A variety of testing points also support most of the key feature

probing of the UCC2x5xx. Moreover, the PCB layout is not only optimized with minimized loop area in

each gate driver loop and power supply loop with bypassing capacitors, but the layout also supports high

voltage test between the primary side and secondary side with 120-mil PCB board cutout. Importantly, the

creepage distance between two output channels are maximized with bootstrap diode in footprint of

TO252-2(DPAK), which facilitates high-voltage, half-bridge testing for a wide variety of power converter

topologies. For detail device information, refer to UCC21520DW,UCC20520DW,UCC21521CDW and

UCC21530DWK data sheets and TI's Isolated gate driver solutions.

www.ti.com

Description

SLUUBG8B–June 2016–Revised November 2018

Using the UCC21520EVM-286, UCC20520EVM-286, UCC21521CEVM-286,

and UCC21530EVM-286

3.1 Features

• Evaluation module for the UCC21520DW, UCC20520DW, and UCC21521CDW in a wide body SOIC-

16 (DW), along with the UCC21530DWK in wide body SOIC-14 (DWK) package

• 3-V to 18-V VCCI power supply range, and up to 25-V VDDA/VDDB power supply range

• 4-A and 6-A source/sink current capability

• 5.7-kVRMS Isolation for 1 minute per UL 1577

• TTL/CMOS-compatible inputs

• Onboard trimmer potentiometer for dead-time programming

• 3-position header with for INA, INB, DT and enable/disable

• PCB layout optimized for power supply bypassing cap, gate driver loop

• PCB board cutout that facilitates high voltage isolation test between primary side and secondary side

• Maximized creepage distance between two output channels

• Support for half-bridge test with MOSFETs, IGBTs and SiC MOSFETs with connection to external

power stage

• Testing points allows probing all the key pins of the UCC21520DW, UCC20520DW, UCC21521CDW,

UCC21530DWK, and other wide-body ISO driver family parts.

3.2 I/O Description

Table 1. Jumpers Setting

PINS DESCRIPTION

J1–1 VCCI positive input

J1–2 VCCI negative input

J2–1 VDDA negative input

J2–2 Driver A output

J2–3 VDDA positive input

J3–1 VDDB negative input

J3–2 Driver B output

J3–3 VDDB positive input

J-INA-1 Primary ground

J-INA-2 INA/PWM signal input

J-INA-3 Primary VCC

J-INB-1 Primary ground

J-INB-2 INB signal input

J-INB-3 Primary VCC

J-DIS-1 or J-DIS/EN-1 Primary VCC

J-DIS-2 or J-DIS/EN-2 Enable/Disable signal input

J-DIS-3 or J-DIS/EN-3 Primary ground

J-DT-1 Primary VCC

J-DT-2 Dead-time programming pin

J-DT-3 Connects to trimmer potentiometer

Description

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3.3 Jumpers (Shunt) Setting

Table 2. Jumpers Setting

JACK Jumper Setting Options FACTORY SETTING

J-INA Option A: Jumper not installed, INA/PWM signal provided by external signal and this

pin is default low if left open Option A

Option B: Jumper on J-INA-2 and J-INA-1 set INA low

Option C: Jumper on J-INA-2 and J-INA-3 set INA high

J-INB

Option A: Jumper not installed, INB signal provided by external signal and this pin is

default low if left open Option A for

UCC21520EVM-286,

UCC21521CEM-286 and

UCC21530EVM-286;

Option D for

UCC20520EVM-286

Option B: Jumper on J-INB-2 and J-INB-1 set INB low

Option C: Jumper on J-INB-2 and J-INB-3 set INB high

Option D: Header J-INB is not installed, and no connection on the device under test

J-DIS or J-

DIS/EN

Option A: Jumper not installed, the devices under test are enabled when left open on

enable/disable pin Option C for

UCC21520EVM-286 and

UCC20520EVM-286;

Option B for

UCC21521CEVM-286 and

UCC21530EVM-286

Option B: Jumper on J-DIS-2 and J-DIS-1 or J-DIS/EN-2 and J-DIS/EN-1

Option C: Jumper on J-DIS-2 and J-DIS-3 or J-DIS/EN-2 and J-DIS/EN-3

J-DT

Option A: Jumper not installed, interlock with 8-ns dead time

Option B

Option B: Jumper on J-DT-2 and J-DT-1 allows driver output overlap or driver output

follows PWM input for UCC21520EVM and UCC21521CEVM. The dead

time will be around 0 ns in this option for UCC20520EVM

Option C: Jumper on J-DT-2 and J-DT-3 set the dead time by DT (in ns) = RDT (in kΩ)

× 10. For better noise immunity and dead-time matching, TI recommends

to parallel a 2.2-nF or above bypassing capacitor from DT pin to GND.

4 Electrical Specifications

Table 3. UCC2x5xxEVM-286 Electrical Specifications

DESCRIPTION MIN TYP MAX UNIT

VCCI Primary-side power supply 3 18 V

VDDA, VDDB

Driver output power supply for UCC21520EVM-286 and

UCC20520EVM-286 9.2 25 V

Driver output power supply for UCC21521CEM-286 and

UCC21530EVM 14.7 25 V

FSSwitching frequency 0 5 MHz

TJOperating junction temperature range –40 125 °C

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Test Summary

SLUUBG8B–June 2016–Revised November 2018

Using the UCC21520EVM-286, UCC20520EVM-286, UCC21521CEVM-286,

and UCC21530EVM-286

5 Test Summary

The UCC21520EVM-286 is used as the primary example for this section. Different Jumper settings, PWM

signal input options and voltage source settings can be found in Section 3 and Section 4

5.1 Definitions

This procedure details how to configure the UCC2x5xx evaluation board. Within this test procedure the

following naming conventions are followed. Refer to the UCC21520EVM-286 Schematic in Figure 7 for

details.

VXX:External voltage supply name.

V(TPxx):Voltage at test point TPxx. For example, V(TP12) means the voltage at TP12.

V(Jxx):Voltage at jack terminal Jxx.

Jxx(yy):Terminal or pin yy of jack xx.

DMM: Digital multi-meters.

UUT: Unit under test

EVM: Evaluation module assembly, in this case the UUT assembly drawings have location for jumpers,

test points and individual components.

5.2 Equipment

5.2.1 Power Supplies

Three DC power supply with voltage/current above 25 V/1 A (for example: Agilent E3634A)

5.2.2 Function Generators

One two-channel function generator over 20 MHz (for example: Tektronics AFG3252)

5.3 Equipment Setup

5.3.1 DC Power Supply Settings

• DC power supply #1

– Voltage setting: 5 V

– Current limit: 0.05 A

• DC power supply #2

– Voltage setting: 12 V for UCC21520EVM and UCC20520EVM

– Voltage setting: 15 V for UCC21521CEVM and UCC21530EVM

– Current limit: 0.1 A

• DC power supply #3

– Voltage setting: 12 V for UCC21520EVM and UCC20520EVM

– Voltage setting: 15 V for UCC21521CEVM and UCC21530EVM

– Current limit: 0.1 A

Test Summary

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8SLUUBG8B–June 2016–Revised November 2018

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5.3.2 Digital Multi-Meter Settings

• Digital multi-meter #1

– DC current measurement, auto-range.

• Digital multi-meter #2

– DC current measurement, auto-range.

5.3.3 Two-Channel Function Generator Settings

Table 4. Two-Channel Function Generator Settings

MODE FREQUENCY DUTY DELAY HIGH LOW OUTPUT

IMPEDANCE

Channel A Pulse DC ~ 5 MHz 50% 0 ns 3.3 V 0 V High Z

Channel B 100 ns

5.3.4 Oscilloscope Setting

Table 5. Oscilloscope Settings

BANDWIDTH COUPLING TERMINATION SCALE SETTINGS INVERTING

Channel A 500 MHz or above DC 1 MΩor automatic 10× or automatic OFF

Channel B

5.3.5 Jumper (Shunt) Settings

There are two jumpers (shunts) need to be installed before test:

1. Install shunt #1 for header J-DIS on pin 2-3 for the UCC21520EVM shown in Figure 1. For the

UCC20520EVM, UCC21521CEVM and the UCC21530EVM, refer to Table 1. The UCC20520EVM is

set as disable high on the DIS pin while the UCC21521CEM and UCC21530EVM is set as enable high

on the EN pin.

2. Install shunt #2 on header J-DT on pin 1-2 as shown in Figure 1.

Figure 1. Jumpers Installation Position

Power

Supply #1

(5V/0.05A)

Power

Supply #2

(12V/0.1A)

sDMM #2

DC Current

DMM #1

DC Current

Power

Supply #2

(12V/0.1A)

CH1 CH2

EVM

Function

Generator Oscilloscope

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Test Summary

SLUUBG8B–June 2016–Revised November 2018

Using the UCC21520EVM-286, UCC20520EVM-286, UCC21521CEVM-286,

and UCC21530EVM-286

5.3.6 Bench Setup Diagram

The current bench setup diagram includes the function generator and oscilloscope connections.

Follow the connection procedure below and use Figure 2 as a reference:

• Make sure all the output of the function generator, voltage source are disabled before connection;

• Function generator channel-A channel applied on JINA ←→ TP14 as seen in Figure 2;

• Function generator channel-B channel applied on JINB ←→ TP15 as seen in Figure 2. For the

UCC20520EVM, JINB, J-INB and TP15 are not installed because the UCC20520 is a single PWM

input, dual-channel output Iso-Driver;

• Power supply #1: positive node applied on J1 pin-1 (or TP0), and negative node applied on J1 pin-2

(or TP13);

• Power supply #2: positive node connected to input of DMM #1 and DMM #1 output connected to J2

pin-3 (or TP10), negative node connected directly to J2 pin-1 (or TP17);

• Power supply #3: positive node connected to input of DMM #2 and DMM #2 output connected to J3

pin-3 (or TP 11), negative node connected directly to J3 pin-1 (or TP19);

• Oscilloscope channel-A probes TP9 ←→ TP17, smaller measurement loop is preferred;

• Oscilloscope channel-B probes TP12 ←→ TP19, smaller measurement loop is preferred;

Figure 2. Bench Setup Diagram and Configuration

Power-Up and Power-Down Procedure

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10 SLUUBG8B–June 2016–Revised November 2018

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6 Power-Up and Power-Down Procedure

6.1 Power Up

1. Make sure that Section 5.3.6 is implemented for setting up all the equipment before starting the power-

up sequence. Figure 3 can be used as a reference.

2. Enable supply #1;

3. Enable supply #2 and #3, the quiescent current on DMM1 and DMM2 ranges from 1 mA to

approximately 3 mA if everything is set correctly;

4. Enable the function generator, two-channel outputs: channel-A and channel-B;

5. There will be:

1. Stable pulse output on the channel-A and channel-B in the oscilloscope (refer to Figure 3);

2. Scope frequency measurement is the same with function generator output;

3. DMM #1 and #2 read measurement results should be around 10 mA, ±2 mA under no load

conditions. For more information about operating current, refer to the UCC21520 data sheet.

Figure 3. Example Input and Output Waveforms (Channels 3 and 4 are PWM Inputs, Channels 1 and 2 are

Outputs)

6.2 Power Down

1. Disable function generator;

2. Disable power supply #2 and #3;

3. Disable power supply #1;

4. Disconnect cables and probes;

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