Texas Instruments Bq24165 Manual de usuario

User's Guide

SLUU497B –December 2011–Revised June 2012

Chipscale-Packaged bq24165, 24166, 24167 Evaluation

Modules

The bq24165, 24166, 24167 evaluation module is a complete charger module for evaluating a compact,

flexible, high-efficiency, USB-friendly, switch-mode charge management solution for single-cell, Li-ion and

Li-polymer batteries used in a wide range of portable applications.

Contents

1 Introduction .................................................................................................................. 2

1.1 bq2416x IC Features .............................................................................................. 2

1.2 bq24165, 24166, 24167 EVM Features ......................................................................... 2

1.3 Schematic ........................................................................................................... 3

1.4 I/O Description ...................................................................................................... 4

1.5 Test Points .......................................................................................................... 4

1.6 Control and Key Parameters Setting ............................................................................ 5

1.7 Recommended Operating Conditions ........................................................................... 5

2 Test Summary ............................................................................................................... 6

2.1 Definitions ........................................................................................................... 6

2.2 Recommended Test Equipment ................................................................................. 6

2.3 Recommended Test Equipment Setup .......................................................................... 7

2.4 Recommended Test Procedure .................................................................................. 8

3 Printed-Circuit Board Layout Guideline ................................................................................. 10

4 Bill of Materials and Board Layout ...................................................................................... 11

4.1 Bill of Materials .................................................................................................... 11

4.2 Board Layout ...................................................................................................... 13

List of Figures

1 bq24165/166/167EVM (HPA741) Schematic............................................................................ 3

2 BAT Load (PR1010) Schematic........................................................................................... 7

3 Original Test Setup for bq24165/166/167 EVM (HPA741) ............................................................ 8

4 Top Assembly Layer ...................................................................................................... 13

5 Top Layer .................................................................................................................. 13

6 Bottom Layer............................................................................................................... 14

7 First Internal Layer ........................................................................................................ 14

8 Second Internal Layer .................................................................................................... 15

List of Tables

1 Bill of Materials - HPA741A ............................................................................................. 11

SLUU497B –December 2011–Revised June 2012 Chipscale-Packaged bq24165, 24166, 24167 Evaluation Modules

Introduction

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1 Introduction

1.1 bq2416x IC Features

The bq24165, 24166, 24167 integrates a synchronous PWM controller, power MOSFETs, input current

sensing, high-accuracy current and voltage regulation, charge termination and power path management

into a chipscale package. Key integrated circuit (IC) features include:

• High-efficiency, fully integrated, NMOS-NMOS, synchronous buck charger with 1.5-MHz frequency

• Integrated power FETs for up to 2.5-A charge rate

• Power path management between battery and system voltages

For details, see the bq24165, 24166, 24167 data sheet (SLUSAP4).

1.2 bq24165, 24166, 24167 EVM Features

The bq24165, 24166, 24167 evaluation module (EVM) is a complete charger module for evaluating

compact, flexible, high-efficiency, USB-friendly, switch-mode battery charge and power path management

solution for single-cell, Li-ion and Li-polymer battery-powered systems used in a wide range of portable

applications. Key EVM features include:

• Programmable charge current, input current on, and VINDPM threshold using jumpers

• Input power connectors for both USB input and ac adapter

• Programmable charge current, input current on, and VINDPM threshold using jumpers

• IN operating range of 4.2 V – 10 V

• USB operating range of 4.2 V – 6 V

• LED indication for status signals

• Test points for key signals available for testing purposes. Easy probe hook-up

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Introduction

1.3 Schematic

Figure 1. bq24165/166/167EVM (HPA741) Schematic

NOTE: EVMs with a printed-circuit board label that contain the suffix -X may have been assembled with

incorrectly marked ICs. Regardless of the IC’s marking, the EVM was assembled with the correct part

number as specified in the EVM bill of material.

SLUU497B –December 2011–Revised June 2012 Chipscale-Packaged bq24165, 24166, 24167 Evaluation Modules

Introduction

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1.4 I/O Description

Header/Terminal Block Description

J1-IN Adapter positive header

J2-IN Adapter positive terminal

J2-GND Adapter negative terminal

J3-GND Adapter negative header

J4-USB USB positive header

J5-SYS System output positive header

J6-USB USB positive terminal

J6-GND USB negative terminal

J7-SYS System output positive terminal

J7-GND System output negative terminal

J8-GND USB negative header

J9-GND System output negative header

J10-BAT+ Battery positive header

J11-BAT+ Battery positive terminal

J11-GND Battery negative terminal

J12-GND Battery negative header

J13-DRV DRV reference voltage positive header

J14-DRV DRV reference voltage positive terminal

J14-GND DRV reference voltage negative terminal

J15-GND DRV reference voltage negative header

J16–IN External thermistor positive terminal

J16–GND Ground connection for external thermistor

1.5 Test Points

Test Point Description

TP1 Kelvin to IN

TP2 Kelvin to USB

TP3 SW

TP4 Kelvin to SYS

TP5 GND

TP6 GND

TP7 IUSB3

TP8 Kelvin to BAT

TP9 IUSB1

TP10 IUSB2

TP11 ISET

TP12 ILIM

TP13 CE2 for bq24165 or TS for bq24166/167

TP14 CE1 for'bq24165 or CE for bq24166/167

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1.6 Control and Key Parameters Setting

Jum Default Factory

IC Description

per Setting

1-2: FET GATE = BGATE: External PFET's gate tied to BGATE pin and therefore controlled

by IC. 1-2 (FET GATE =

All JP1 2-3: FET GATE = SYS: External PFET's gate tied to SYS and therefore disabled. BGATE)

It is recommended that this jumper be changed only when the device is not enabled or in Hi-Z

mode so that the PFET's gate is never left open.

1-2: CE1 = HI: Active-low enable for reduced VBAT voltage (if CE2 = LO) or suspended

bq241 charging (if CE2 = HI)

JP2 2-3 (CE1 = LO)

65 2-3: CE1 = LO: Active-low enable for full current charging (if CE2 = LO) or charging at half

current (if CE2 = HI)

bq241

66 1-2: CE = HI: Active-low charge enable high to disable charge and enter Hi-Z mode

JP2 2-3 (CE = LO)

bq241 2-3: CE = LO: Active-low charge enable low for normal operation

67 1-2: IUSB3 = HI

2-3: IUSB3 = LO

All JP3 2-3 (IUSB3 = LO)

See data sheet Table 1 for description of USB input current limit and VINDPM threshold

setting. Default setting is for 500-mA input current limit and 4.68-V threshold.

1-2: IUSB2 = HI

2-3: IUSB2 = LO

All JP4 2-3 (IUSB2 = LO)

See data sheet Table 1 for description of USB input current limit and VINDPM threshold

setting. Default setting is for 500-mA input current limit and 4.68-V threshold.

1-2: IUSB1 = HI

2-3: IUSB1 = LO

All JP5 1-2 (IUSB1 = HI)

See data sheet Table 1 for description of USB input current limit and VINDPM threshold

setting. Default setting is for 500-mA input current limit and 4.68-V threshold.

1-2 (CE2 = HI): Active-low enable for charging at half current (if CE1 = LO) or suspended

bq241 charging (if CE1 = HI)

JP6 2-3 (CE2 = LO)

65 2-3 (CE2 = LO): Active-low enable for full current charging (if CE1 = LO) or reduced VBAT

voltage (if CE1 = HI)

1-2 (TS = EXT): Connects the TS pin to an external thermistor. The resistor divider formed by

bq241 R4 and R5 has been sized to accommodate a 10-kΩthermistor. If a different thermistor is

66 used, R4 and R5 need to be resized.

JP6 2-3 (TS = INT)

bq241 2-3 (TS = INT): Connects a potentiometer to the TS pin so the potentiometer can emulate a

67 thermistor. The potentiometer has been preset to approximately 3.4 kΩso that the TS voltage

is 0.5 x V(DRV).

1.7 Recommended Operating Conditions

Min Typ Max Unit

Supply voltage, VIN Operating input voltage from ac adapter 4.2 10 V

USB voltage, VUSB Operating input voltage from USB or equivalent supply 4.2 6 V

Battery voltage, VBAT Voltage applied at VBAT terminal (depends on status of CE1 4.02 4.2 4.24 V

and CE2)

System voltage, VSYS Voltage output at SYS terminal (depends on VBAT voltage 3.4 4.37 V

and status of VINDPM)

Supply current, IIN(MAX) Maximum input current limit for ac adapter input (set by 1.5 2.5 A

user-selectable resistor)

Supply current, IUSB(MAX) Maximum input current limit for USB input (set by USBx 0.1 0.5 1.5 A

input pins)

Max fast charge current, Battery charge current 0.550 2.5 A

ICHRG(MAX)

Operating junction temperature range, TJ-40 125 °C

SLUU497B –December 2011–Revised June 2012 Chipscale-Packaged bq24165, 24166, 24167 Evaluation Modules

Test Summary

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2 Test Summary

This procedure describes one test configuration of the HPA741 evaluation board for bench evaluation.

2.1 Definitions

The following naming conventions are followed.

VXXX : External voltage supply name (VIN, VUSB)

LOAD#: External load name

V(TPyyy): Voltage at internal test point TPyyy. For example, V(TP12) means the voltage at

TP12.

V(Jxx): Voltage at header Jxx

V(TP(XXX)): Voltage at test point XXX. For example, V(ACDET) means the voltage at the test

point which is marked as ACDET.

V(XXX, YYY): Voltage across point XXX and YYY.

I(JXX(YYY)): Current going out from the YYY terminal of header XX.

Jxx(BBB): Terminal or pin BBB of header xx

JPx ON : Internal jumper Jxx terminals are shorted.

JPx OFF: Internal jumper Jxx terminals are open.

JPx (-YY-) ON: Internal jumper Jxx adjacent terminals marked as YY are shorted.

Measure: →A,B Check specified parameters A, B. If measured values are not within specified limits

the unit under test has failed.

Observe →A,B Observe if A, B occur. If they do not occur, the unit under test has failed.

Assembly drawings have location for jumpers, test points, and individual components.

2.2 Recommended Test Equipment

2.2.1 Power Supplies

1. Power Supply number 1 (PS1) capable of supplying 6 V at 3 A is required.

2. If not using a battery as the load, then power supply number 2 (PS2) capable of supplying up to 5 V at

5 A is required to power the circuit shown in Figure 2.

2.2.2 Load #1 between BAT and GND

Testing with an actual battery is the best way to verify operation in the system. If a battery is unavailable,

then a circuit similar to the one shown inFigure 2 can simulate a battery when connected to a second

power supply.

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Test Summary

Figure 2. BAT Load (PR1010) Schematic

2.2.3 Load #2 Between SYS and GND

Although not required, a resistive load capable of sinking up to 3 A can be used.

2.2.4 Meters

Four equivalent voltage meters (VMx) and two equivalent current meters (CMx) are required. The current

meters must be able to measure at least 3-A current.

2.3 Recommended Test Equipment Setup

1. For all power connections, use short, twisted-pair wires of appropriate gauge wire for the amount of the

current.

2. Set Power Supply number 1 for 6 V ± 100 mV, 3-A current limit, and then turn off supply.

3. If BAT_Load (PR1010) as shown in Figure 2 is used, connect Power Supply number 2 (PS2) set to

approximately 3.6 V to the input side (PS2+/-) of BAT_Load (PR1010), then turn off PS2.

4. Connect the output side of the battery or BAT_Load (PR1010) in series with current meter (multimeter)

number 2 (CM2) to J2 and J6 or J3 (BAT, GND). Ensure that a voltage meter is connected across J2

or TP3 and J6 or TP9 (BAT, GND).

5. Connect VM3 across J5 or TP4 and J9 (SYS, GND).

6. Connect VM4 across J13 and J15 (DRV, GND).

7. Ensure jumpers are at the default factory settings per Section 1.6

8. After the preceding steps are accomplished, the test setup for HPA741 is as shown in Figure 3

SLUU497B –December 2011–Revised June 2012 Chipscale-Packaged bq24165, 24166, 24167 Evaluation Modules

VM#2

CM#2

ICHRG

VM#3

CM#1

IIN

VM#1

-+ +

VM#4

V+

BAT_Load

PS#2

Test Summary

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Figure 3. Original Test Setup for bq24165/166/167 EVM (HPA741)

2.4 Recommended Test Procedure

The following test procedure may be useful for evaluating the charger IC outside of a real system, if no

battery is available to connect to the output and a simulated battery is needed.

2.4.1 Charge Voltage and Current Regulation of IN

1. Ensure that the Section 2.3 steps are followed.

2. Move JP2 (CE1 or CE) = HI and JP6 = HI.

3. Connect the output of Power Supply #1 (PS #1) in series with current meter number 1 (CM1) to J2 (IN,

GND).

4. Connect voltage meter number 1 (VM1) across J1 or TP1 and J3 or TP6 (IN, GND).

5. With PS2 disabled, turn on PS1.

6. Measure:

Measure on VM3 →V(J5/TP4(SYS),J9(GND)) = 4.3 ± 100 mV

Measure on VM4 →V(J13(DRV),J15(GND)) = 5.2 ± 200 mV

7. Move JP2 (CE1 or CE) = LO and JP6 = LO. Adjust the power supply so that VM1 still reads 6 V ± 100

mV if necessary.

8. Enable PS2 and adjust PS2 so that the voltage measured by VM2, across BAT and GND, measures

3.2 V + 50 mV

9. Measure and Observe:

Measure on CM2→ICHRG = 2500 mA ± 150 mA

Measure on CM1 →IIN = 1800 mA ± 180 mA

Observe →D1 and D2 are on.

10. Turn off PS1 and PS2.

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Test Summary

2.4.2 Charge Voltage and Current Regulation of USB

1. Ensure that the Section 2.3 steps are followed.

2. Move JP2 (CE1 or CE) = HI and JP6 = HI.

3. Connect the output of Power Supply number 1 (PS1) in series with current meter (multimeter) number

1 (CM1) to J4 and J8 or J6 (USB, GND).

4. Connect voltage meter 1 (VM1) across J4 or TP2 and J8 or TP5 (USB, GND).

5. With PS2 disabled, turn on PS1.

6. Measure:

Measure on VM3 →V(J5/TP4(SYS),J9(GND)) = 4.3 ± 100 mV

Measure on VM4 →V(J13(DRV),J15(GND)) = 5.2 ± 200 mV

7. Move JP2 (CE1 or CE) = LO and JP6 = LO while keeping the default settings for JP3 (USB3), JP4

(USB2) and JP5 (USB1). Adjust PS1 so that VM1 still reads 6 V ± 100 mV if necessary.

8. Enable PS2 and adjust PS2 so that the voltage measured by VM2, across BAT and GND, measures

3.2 V ± 50 mV.

9. Measure:

Measure on CM2→ICHRG = 735 mA ± 75 mA

Measure on CM1 →IIN = 475 mA ± 50 mA

Observe →D1 and D2 are on.

10. Turn off PS1 and PS2.

2.4.3 Helpful hints

1. To observe the taper current as the battery voltage approaches the set regulation voltage, allow the

battery to charge or, if using BAT_Load (PR1010), slowly increase the PS2 voltage powering

BAT_Load (PR1010). Use VM2 across BAT and GND to measure the battery voltage seen by the IC.

2. To observe the VINDPM function, lower the current limit on PS1.

3. To observe battery supplement mode, apply a resistive load across SYS and GND that is higher than

the maximum charge current.

SLUU497B –December 2011–Revised June 2012 Chipscale-Packaged bq24165, 24166, 24167 Evaluation Modules

Printed-Circuit Board Layout Guideline

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3 Printed-Circuit Board Layout Guideline

1. To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND,

must be placed as close as possible to the bq2416x.

2. Place 4.7-µF input capacitor as close to PMID pin and PGND pin as possible to make high-frequency

current loop area as small as possible. Place 1-µF input capacitor GNDs as close to the respective

PMID capacitor GND and PGND pins as possible to minimize the ground difference between the input

and PMID_.

3. The local bypass capacitor from SYS to GND must be connected between the SYS pin and PGND of

the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and

back to the PGND pin.

4. Place all decoupling capacitors close to their respective IC pins and as close as to PGND (do not place

components such that routing interrupts power stage currents). All small control signals must be routed

away from the high-current paths.

5. The PCB must have a ground plane (return) connected directly to the return of all components through

vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal

components). It is also recommended to put vias inside the PGND pads for the IC, if possible. A star

ground design approach is typically used to keep circuit block currents isolated (high-power/low-power

small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this

design gives good results. With this small layout and a single ground plane, no ground-bounce issue

occurs, and having the components segregated minimizes coupling between signals.

6. The high-current charge paths into IN, USB, BAT, SYS, and from the SW pins must be sized

appropriately for the maximum charge current in order to avoid voltage drops in these traces. The

PGND pins must be connected to the ground plane to return current through the internal low-side FET.

7. For high-current applications, the balls for the power paths must be connected to as much copper in

the board as possible. This allows better thermal performance because the board conducts heat away

from the IC.

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