Texas Instruments THVD1454EVM Manual de usuario
EVM User's Guide: THVD1454EVM
THVD1454EVM User's Guide
ABSTRACT
This document is the EVM User’s guide for the THVD1454EVM which provides a quick way to evaluate the TI
THVD1454, a half duplex RS-485 transceiver with selectable data rate and switchable integrated termination
resistors, in the VSON (DRC) package.
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Board Description...................................................................................................................................................................4
3 Board Component Overview..................................................................................................................................................4
4 Powering the Board................................................................................................................................................................6
5 Operation of THVD1454EVM..................................................................................................................................................7
5.1 Default Operation............................................................................................................................................................... 7
5.2 Potential Modifications....................................................................................................................................................... 7
6 Design Documents................................................................................................................................................................. 9
6.1 Schematics.........................................................................................................................................................................9
6.2 Layout...............................................................................................................................................................................11
6.3 Bill of Materials.................................................................................................................................................................13
7 References............................................................................................................................................................................ 13
Trademarks
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THVD1454EVM User's Guide 1
Copyright © 2023 Texas Instruments Incorporated
Figure 1-2. Bottom View of THVD1454EVM
Information About Cautions and Warnings
The information in the warning statement is provided for personal protection and the information in the caution
statement is provided to protect the equipment from damage. Read each caution and warning statement
carefully.
This EVM contains components that can potentially be damaged by electrostatic discharge. Always transport
and store the EVM in its supplied ESD bag when not in use. Handle using an antistatic wristband. Operate on an
antistatic work surface. For more information on proper handling, see Electrostatic Discharge (ESD).
www.ti.com Introduction
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THVD1454EVM User's Guide 3
Copyright © 2023 Texas Instruments Incorporated
2 Board Description
Features
• Ready to Use out of Box with THVD1454 Pre-Installed
• Two 10 uF and Two 47 uF Decoupling Caps Pre-Installed on VCC to GND and GND to EARTH Connections
• Two Resistor Pads to create resistive link between GND and EARTH
• One 4x2 Header Connection for Feature Control Signals
• External Termination Resistor and Capacitor Pads on shared bus
• Common Mode Voltage Connection Points Located at J11 and J12
3 Board Component Overview
The THVD1454EVM is ready to operate directly out of box with a THVD1454 installed at U1. All the Signal
and Power Jumpers/Inputs (J1 – J12) come pre-installed on board. See Table 3-1 for component overview for
Jumpers.
Table 3-1. Power Jumpers/Inputs (J1 – J12)
Jumper ID Function Package Comment Installed?
J1 “R” Pin output 4x2 Header N/A Y
J2 “/RE” Pin Input 4x2 Header N/A Y
J3 “DE” Pin Input 4x2 Header N/A Y
J4 “D” Pin Input 4x2 Header N/A Y
J5 VCC Terminal 3-Pin Terminal Block N/A Y
J6 Control Signal Header 4x2 Header N/A Y
J7 Bus Header #1 4x1 Header Between Series Resistor
and IC
Y
J8 Bus Header #2 4x1 Header Between Series Resistor
and Terminal
Y
J9 Differential Bus
Connection Terminal
3-Pin Terminal Block N/A Y
J10 “A” Line Common Mode
Input
4x1 Header N/A Y
J11 “B” Line Common Mode
Input
4x1 Header N/A Y
J12 Differential Bus Common
Mode Input
4x1 Header N/A Y
Resistor Pad IDs (R1-R20), function, package, comment, and default installation status are shown inTable 3-2.
Table 3-2. Resistor Pad IDs (R1-R20)
Resistor ID Function Package Comment Installed?
R1 0 Ohm Series Resistor 0603 "R" Pin Y
R2 Pull-Up Resistor 0603 "R" Pin N
R3 LED Current Limiting
Resistor
0603 "R" Pin LED Y
R4 0 Ohm Series Resistor 0603 "/RE" Pin Y
R5 Pull-Down Resistor 0603 "/RE Pin" N
R6 Pull-Up Resistor 0603 "/RE Pin" N
R7 0 Ohm Series Resistor 0603 "DE Pin" Y
R8 Pull-Up Resistor 0603 "DE Pin" N
R9 Pull-Down Resistor 0603 "DE Pin" N
R10 0 Ohm Series Resistor 0603 "D Pin" Y
R11 Pull-Up Resistor 0603 "D Pin" N
R12 Pull-Down Resistor 0603 "D Pin" N
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Table 3-2. Resistor Pad IDs (R1-R20) (continued)
Resistor ID Function Package Comment Installed?
R13 LED Current Limiting
Resistor
0603 "D Pin LED" Y
R14 GND to EARTH Resistor 0603 N/A N
R15 LED Current Limiting
Resistor
0603 "VCC LED" N
R16 Termination Resistor Pad 0805 N/A N
R17 0 Ohm Series Resistor 0603 "A Pin" Y
R18 0 Ohm Series Resistor 0603 "B Pin" Y
R19 Common Mode Resistor
"A Pin"
0603 N/A N
R20 Common Mode Resistor
"B Pin"
0603 N/A N
Capacitor Pad IDs (C1 - C10), function, package, comment, and default installation status are shown in Table
3-3.
Table 3-3. Capacitor Pad IDs (C1 - C10)
Capacitor ID Function Package Comment Installed?
C1 Capacitive Load on "R"
Pin
0603 N/A N
C2 IC HF Decoupling
Capacitor
0603 N/A Y
C3 GND to Earth 47uF
Decoupling Capacitor
0805 N/A Y
C4 VCC to GND 47uF
Decoupling Capacitor
0805 N/A Y
C6 VCC to GND 10uF
Decoupling Capacitor
0805 N/A Y
C7 Earth to GND 10uF
Decoupling Capacitor
0805 N/A Y
C8 Termination Capacitor Pad 0805 N/A N
C9 "A" Pin Common Mode
Decoupling Capacitor
0603 N/A Y
C10 "B" Pin Common Mode
Decoupling Capacitor
0603 N/A Y
Other component IDs, function, package, comment, and default installation status are shown in Table 3-4.
Table 3-4. Other component IDs
Other Component ID Function Package Comment Installed?
D1 LED indicator for Data
Reception at "R" pin
Custom "Red" Y
D2 LED Indicator For Data
Transmission at "D" pin
Custom "Green" N
D3 LED Indicator for Board
Power
Comment "Blue" Y
U1 Main EVM IC DRC N/A Y
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THVD1454EVM User's Guide 5
Copyright © 2023 Texas Instruments Incorporated
4 Powering the Board
Powering the THVD1454EVM is a quick process. To power on the board have top side of board facing upwards
with J5 at the top of the EVM. From left to right the power terminal pins of J5 are connected to Earth, GND, and
VCC respectively - this is also noted on the EVM.
If the test setup includes an Earth or Chassis connection, connect this to the left pin of J5. If no Earth or Chassis
connection exist in the test setup connect this pin to GND. Next connect the GND connection to the center pin
of J5 as this is what the THVD1454 references as its GND connection. Finally connect the positive terminal of
a 3.3V to 5V supply voltage to the right most pin on J5. The board is now ready to be powered on; this is done
correctly when the blue LED "D3" lights up.
The Proper orientation of the J5 Terminal Block is shown in Figure 4-1.
Figure 4-1. Power Connection Block View: J5
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5 Operation of THVD1454EVM
5.1 Default Operation
After powering up the EVM with instructions listed Powering The Board, the EVM is ready to ready to operate
without modification. If all pins, besides VCC and GND, are left floating after power up the following each pin is in
the states listed in Table 5-1.
Table 5-1. Default Pin States THVD1454
Pin on THVD1454 Associated Jumper Default State Comment
R J1 Hi-Z /RE is pulled high by default
leaving RX disabled
/RE J2 Logic High Internal pull-up leaves /RE ~ VCC
by default. RX disabled
DE J3 Logic Low Internal pull-down leaves DE
~GND by default. TX disabled
D J4 Logic High Internal pull-up leaves "D" high -
preventing floating input on data
input pin
TERM J6 Logic Low Internal pull-down disables
integrated termination resistor by
default
B J7, J8, and J9 Hi-Z Driver disabled by default.
A J7, J8, and J9 Hi-Z Driver Disabled by default
SLR J6 Logic Low Slew Rate Control is disabled
by default allowing for maximum
speeds of 20Mbps
To transmit data under the default setup see Table 5-2.
Table 5-2. TX Function Table
DE (J3) D (J4) A (Output) B (Output)
Low X Hi-Z Hi-Z
High Low Low High
High High High Low
Under the default conditions the A and B pins are unterminated and can handle data up to a speed of 20Mbps.
To receive data under the default setup see receiver function table below. For best results on reception DE
should be held low to disable the driver.
Table 5-3. RX Function Table
/RE (J2) VA - VB (J7, J8, and J9) R (J1)
High X Hi-Z
Low ≥ -45 mV High
Low ≤ -200 mV Low
Low -45 mV ≤ VA - VB ≤ -200 mV Indeterminate
For potential modifications and deviations away from default setup, please see Potential Modifications .
5.2 Potential Modifications
With a understanding of the board in its default state there are a few modifications that can be made either via
the header blocks or by adding addition components.
Figure 5-1 shows the control header J6, which with the addition of two shunts can control the Slew Rate Control
(SLR) feature and Integrated Termination (TERM) features.
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THVD1454EVM User's Guide 7
Copyright © 2023 Texas Instruments Incorporated
Figure 5-1. Control Block View: J6
The J6 header has pin one on the bottom right hand corner and pin two on the top right hand corner. The pins
increment up from right to left with the top row even pin numbers and the bottom row odd numbers. A signal map
is shown in Table 5-4.
Table 5-4. J6 Pin Mapping
J6 Pin # SIGNAL
1 SLR
2 SLR
3 VCC
4 GND
5 TERM
6 TERM
7 VCC
8 GND
A function table of SLR and TERM is shown in Table 5-5.
Table 5-5. J6 Function Table
Pin | Jumper Pin State Function Comment
TERM | J6-5, J6-6 Low Integrated Termination Disabled For non-terminated nodes
TERM | J6-5, J6-6 High Integrated Terminatino Enabled Terminated with 120Ω between A
and B.
SLR | J6-1, J6-2 Low Slew Rate Control Disabled Max Speed is 20Mbps
SLR | J6-1, J6-2 High Slew Rate Control Enabled Max Speed is 500Kbps
Beyond the controllable features accessed through J6 there are also pads for external pull-up, pull-down, and
capacitive loads available on J1, J2, J3, and J4. For typical applications capacitive loads are placed on "R"
pin and the other pins may or may not have external pull-up or pull-down resistors. All the pads are in 0603
packages and can be varied based on customers testing needs.
The final modifications are around the differential bus pins - A and B. To help simulate capacitive loading of
a cable a 0805 termination capacitor pad, ID = C8, is available between A and B pins. The option to add an
external termination resistance is also possible with a 0805 pad, ID = R16. This external termination when
paired with the integrated termination resistor can allow for quick measurements of power measurements on a
terminated bus. The power testing can be expanded with the addition of common mode loading resistances R19
and R20.
Operation of THVD1454EVM www.ti.com
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Copyright © 2023 Texas Instruments Incorporated
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