Tews Technologies TIP606 Manual de usuario

The Embedded I/O Company

TIP606

Digital Input Module for

Avionic Applications

Version 1.0

User Manual

Issue 1.3

September 2006

D75606800

TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC

Am Bahnhof 7

25469 Halstenbek, Germany

www.tews.com

Phone: +49-(0)4101-4058-0

Fax: +49-(0)4101-4058-19

e-mail: [email protected]

9190 Double Diamond Parkway,

Suite 127, Reno, NV 89521, USA

www.tews.com

Phone: +1 (775) 850 5830

Fax: +1 (775) 201 0347

e-mail: [email protected]

TIP606 User Manual Issue 1.3 Page 2 of 15

TIP606-10

Digital Input Module for Avionic Applications

This document contains information, which is

proprietary to TEWS TECHNOLOGIES GmbH. Any

reproduction without written permission is forbidden.

TEWS TECHNOLOGIES GmbH has made any

effort to ensure that this manual is accurate and

complete. However TEWS TECHNOLOGIES GmbH

reserves the right to change the product described

in this document at any time without notice.

TEWS TECHNOLOGIES GmbH is not liable for any

damage arising out of the application or use of the

device described herein.

Style Conventions

Hexadecimal characters are specified with prefix 0x,

i.e. 0x029E (that means hexadecimal value 029E).

For signals on hardware products, an ‚Active Low’ is

represented by the signal name with # following, i.e.

IP_RESET#.

Access terms are described as:

W Write Only

R Read Only

R/W Read/Write

R/C Read/Clear

R/S Read/Set

2000-2006 by TEWS TECHNOLOGIES GmbH

IndustryPack is a registered trademark of SBS Technologies, Inc

TIP606 User Manual Issue 1.3 Page 3 of 15

Issue Description Date

1.0 First Issue March 2000

1.1 General Revision October 2003

1.2 Correction of figure “Input Circuit” in chapter “Functional

Description” January 2006

1.3 New address TEWS LLC September 2006

TIP606 User Manual Issue 1.3 Page 4 of 15

Table of Contents

1PRODUCT DESCRIPTION.........................................................................................6

2TECHNICAL SPECIFICATION...................................................................................7

3ID PROM CONTENTS................................................................................................8

4IP ADDRESSING........................................................................................................9

4.1 I/O Addressing.................................................................................................................................9

4.2 Input Register (INPUT)....................................................................................................................9

4.3 Global Control Register (GLBCONT) ..........................................................................................10

4.4 Interrupt Enable Register Rising Edge (INTENALH) .................................................................10

4.5 Interrupt Enable Register Falling Edge (INTENAHL).................................................................11

4.6 Interrupt Status Register Rising Edge (INTSTATLH) ................................................................11

4.7 Interrupt Status Register Falling Edge (INTSTATHL)................................................................11

4.8 Interrupt Vector Register (IVEC)..................................................................................................12

4.9 Debounce Time Register (DEBTIME)..........................................................................................12

5FUNCTIONAL DESCRIPTION .................................................................................13

6PIN ASSIGNMENT – I/O CONNECTOR ..................................................................15

TIP606 User Manual Issue 1.3 Page 5 of 15

Table of Figures

FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6

FIGURE 2-1 : TECHNICAL SPECIFICATION...................................................................................................7

FIGURE 3-1 : ID PROM CONTENTS ...............................................................................................................8

FIGURE 4-1 : REGISTER SET .........................................................................................................................9

FIGURE 4-2 : INPUT REGISTER (INPUT).......................................................................................................9

FIGURE 4-3 : GLOBAL CONTROL REGISTER (GLBCONT)........................................................................10

FIGURE 4-4 : INTERRUPT ENABLE REGISTER RISING EDGE (INTENALH)............................................10

FIGURE 4-5 : INTERRUPT ENABLE REGISTER FALLING EDGE (INTENAHL)..........................................11

FIGURE 4-6 : INTERRUPT STATUS REGISTER RISING EDGE (INTSTATLH) ..........................................11

FIGURE 4-7 : INTERRUPT STATUS REGISTER FALLING EDGE (INTSTATHL)........................................11

FIGURE 4-8 : INTERRUPT VECTOR REGISTER (IVEC)..............................................................................12

FIGURE 4-9 : DEBOUNCE TIME REGISTER (DEBTIME).............................................................................12

FIGURE 5-1 : INPUT CIRCUIT.......................................................................................................................13

FIGURE 5-2 : HIGH SIDE AND LOW SIDE SWITCHING..............................................................................14

FIGURE 6-1 : PIN ASSIGNMENT I/O CONNECTOR.....................................................................................15

TIP606 User Manual Issue 1.3 Page 6 of 15

1 Product Description

The TIP606 is an IndustryPack® compatible module designed for avionic test environments. It

provides 16 optically isolated differential inputs for high unipolar input voltage which may exceed the

supply voltage of the module. The inputs can withstand input voltage up to 44V maximum between the

two differential input pins.

Due to the differential inputs of the TIP606, it is even possible to use the module in noisy

environments. The TIP606 provides a high differential input resistance of 112 kohms typically.

The interface circuit will detect a logic 1, if the differential voltage is typically greater than +14.0V and it

will detect a logic 0, if the input voltage is typically lower than +3.5V. The inputs are isolated from the

IP interface via optocouplers. Each input is capable of generating interrupts on rising or falling edges

of the input signal. It is also possible to disable the generation of interrupts and poll the input register

for new data.

All inputs have an electronic debounce circuit. The debounce time is programmable in a range from

900µs up to 230ms in 256 steps of 900µs. The debounce circuit can also be disabled.

Figure 1-1 : Block Diagram

TIP606 User Manual Issue 1.3 Page 7 of 15

2 Technical Specification

IP Interface

Interface Single Size IndustryPackLogic Interface compliant to

ANSI/VITA 4-1995

ID ROM Data Format I

Interrupts INTREQ0# used

DMA Not supported

Clock Rate 8 MHz

Module Type Type I

Wait States No wait states

Interrupts Interrupt generation for each input

programmable on Low -> high transition, High -> low transition

Number of Inputs 16 differential

Maximum Input Voltage 44V between U_in+ and U_in-

Input Isolation Voltage 500Vpp

Input Switching Level High level: >14.0V typical @+25°C (13.0V-16.0V)

Low level: <3.5V typical @ +25°C (3.1V-4.6V)

Input Impedance 112 kohms typical

Debounce Timer Time minimum: 900µs +/-15%

Time maximum: 230.4ms +/-15%

Step size: 900µs

Interface Connector 50-conductor flat cable

Power Requirements 150mA typical @ +5V DC

Physical Data

Temperature Range Operating

Storage -40 °C to +85 °C

-55°C to +125°C

MTBF 124109 h

Humidity 5 – 95 % non-condensing

Weight 28 g

Figure 2-1 : Technical Specification

TIP606 User Manual Issue 1.3 Page 8 of 15

3 ID PROM Contents

Address Function Contents

0x01 ASCII ‘I’ 0x49

0x03 ASCII ‘P’ 0x50

0x05 ASCII ‘A’ 0x41

0x07 ASCII ‘C’ 0x43

0x09 Manufacturer ID 0xB3

0x0B Model Number 0x2E

0x0D Revision 0x10

0x0F Reserved 0x00

0x11 Driver-ID Low - Byte 0x00

0x13 Driver-ID High - Byte 0x00

0x15 Number of bytes used 0x0C

0x17 CRC 0x0E

0x19 Version 0x0A

Figure 3-1 : ID PROM Contents

TIP606 User Manual Issue 1.3 Page 9 of 15

4 IP Addressing

4.1I/O Addressing

The complete register set of the TIP606 is accessible in the I/O space of the IP.

Address Symbol Description Size (Bit) Access

0x00 INPUT Input Register 16 R

0x03 GLBCONT Global Control Register 8 R/W

0x04 INTENALH Interrupt Enable Register Rising Edge 16 R/W

0x06 INTENAHL Interrupt Enable Register Falling Edge 16 R/W

0x08 INTSTATLH Interrupt Status Register Rising Edge 16 R/W

0x0A INSTATHL Interrupt Status Register Falling Edge 16 R/W

0x0D IVEC Interrupt Vector Register 8 R/W

0x0F DEBTIME Debounce Time Register 8 R/W

Figure 4-1 : Register Set

4.2Input Register (INPUT)

Bit Symbol Description Access Reset

Value

15:0 16 bit input data. Register reflects the actual state of the

inputs. R

Figure 4-2 : Input Register (INPUT)

TIP606 User Manual Issue 1.3 Page 10 of 15

4.3Global Control Register (GLBCONT)

After power up or reset all bits of this register are reset to ‘0’.

Bit Symbol Description Access Reset

Value

7 Global interrupt flag

1 = an interrupt request of at least one of the 16 input

channels is pending.

Bit will be cleared if the appropriate interrupt is acknowledged

by writing ‘1’ to one of the interrupt status registers.

6:3 Not used, undefined during reads R/W

2 Debounce control bit

1 = enables debounce circuit for all 16 inputs

0 = disables debounce circuit

R/W

1 Not used, undefined during reads R/W

0 Global interrupt enable bit

1 = enables all possible interrupts of the TIP606 on interrupt

request line INTREQ0# of the IP bus

0 = disables all interrupts

R/W

Figure 4-3 : Global Control Register (GLBCONT)

4.4Interrupt Enable Register Rising Edge (INTENALH)

Bit Symbol Description Access Reset

Value

Interrupt enable bit of corresponding channel for the rising

edge

Bit 0 enables interrupts of input channel 1 and bit 15 enables

interrupt of input channel 15 rising edge.

1 = interrupt enabled

0 = interrupt disabled

R/W

Figure 4-4 : Interrupt Enable Register Rising Edge (INTENALH)

An interrupt on interrupt request line INTREQ0# of the IP bus is only generated if the global

interrupt enable bit of the Global Control Register is set to ‘1’. After power up or reset all bits of

this register are reset to ‘0’.

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