Teledyne SP Devices ADQ3 Series Manual de usuario

ADQ3 Series FWDAQ

Development Kit

User Guide

Author(s): Teledyne SP Devices

Document ID: 20-2507

Classification: Public

Revision: B

Print date: 2022-03-31

Classification Revision

Public B

Document ID Print date

20-2507 2022-03-31

Contents

1 Introduction 4

1.1 Definitions and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Prerequisites 5

3 Development Environment and Tools 6

3.1 Unpacking the Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.2 OpeningtheDevelopmentKit.................................. 7

3.3 SettingUptheProject ...................................... 7

3.3.1 Configuration....................................... 7

3.4 BuildingtheDesign........................................ 8

3.5 WorkingwiththeDesign..................................... 8

3.5.1 TypicalDesignFlow ................................... 8

3.6 Analyzing the Implemented Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 General Concepts 13

4.1 ParallelDigitalDesign ...................................... 13

4.2 DataFlow............................................. 13

4.3 Clock Domain Crossing Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3.1 CDC Synchronization of a 1-bit Signal . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3.2 CDC Synchronization of a Multi-Bit Signal . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 AXIControlBus ......................................... 18

4.4.1 ControlBusSignals ................................... 18

4.5 DataBus ............................................. 18

4.5.1 TwoBusDefinitions ................................... 18

5 Data Bus Signals 20

5.1 Timestamp ............................................ 21

5.2 TimestampSynchronization................................... 21

5.2.1 SampleIndex....................................... 21

5.2.2 Count ........................................... 21

5.2.3 Event ........................................... 22

5.3 Trigger............................................... 22

5.3.1 SampleIndex....................................... 22

5.3.2 SampleIndexFraction.................................. 22

5.3.3 Rising........................................... 22

5.3.4 Event ........................................... 22

5.3.5 Inhibit ........................................... 22

5.4 Overrange............................................. 23

5.5 GeneralPurpose......................................... 23

5.6 SampleData ........................................... 23

5.7 Valid................................................ 23

5.8 Record .............................................. 23

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5.8.1 Start, Start Index, Stop and Stop Index . . . . . . . . . . . . . . . . . . . . . . . . 23

5.8.2 Number.......................................... 25

5.9 UserID .............................................. 25

5.10 Differences relative to ADQ14, ADQ7 and ADQ8 . . . . . . . . . . . . . . . . . . . . . . . 25

6 User Logic 1 26

6.1 DefaultContents ......................................... 26

6.2 RegisterFile ........................................... 26

6.3 DefaultRegisterFile....................................... 27

7 User Logic 2 29

7.1 DefaultContents ......................................... 29

7.2 RegisterFile ........................................... 30

7.3 DefaultRegisterFile....................................... 30

7.4 PortControl............................................ 33

7.4.1 PortImpedance ..................................... 33

7.4.2 ADQ32-PCIe,ADQ33-PCIe............................... 33

7.4.3 ADQ36-PXIe ....................................... 34

8 Timing Closure 35

9 Troubleshooting 36

9.1 DebuggingonHardware..................................... 36

9.1.1 CreatingtheDebugCore ................................ 36

9.1.2 Connecting to the Debug Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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Document History

Revision Date Section Description Author

B 2022-03-31 - Updated for ADQ36-PXIe release TSPD

2021-11-16 7.4 Add section on user logic 2 port control TSPD

A 2021-06-21 - Initial revision TSPD

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1 Introduction

This document is the user guide for the development kit of the data acquisition firmware for ADQ3 series

digitizers. There are different versions of the development kit depending on the device-to-host interface

and the target number of channels. Make sure the development kit matches the target hardware.

The development kit centers around the user logic areas. These areas target strategic points in the

data path and are specifically intended to contain custom HDL designs.

The first user logic area, UL1, described in Section 6, operates on the full-rate data stream—before

the trigger information has been decoded to create records. The second user logic area, UL2, described

in Section 7, operates on complete records, potentially with a reduced sampling rate.

1.1 Definitions and Abbreviations

Table 1lists the definitions and abbreviations used in this document.

Table 1: Definitions and abbreviations used in this document.

Item Description

ADC Analog-to-digital converter

CDC Clock domain synchronization

Devkit Development kit

DBT1 Data bus type 1

DBT2 Data bus type 2

FWDAQ The data acquisition firmware

GiB Gibibyte (10243bytes)

PCB Printed circuit board

RTL Register transfer level

Tcl Tool command language—scripting language used in Vivado.

UL1 User logic 1—the first open FPGA area, see Section 6.

UL2 User logic 2—the second open FPGA area, see Section 7.

VHDL VHSIC hardware description language

Verilog Hardware description language

Vivado Xilinx FPGA design suite

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2 Prerequisites

The development kit has the following prerequisites:

•A license for the development kit purchased from Teledyne SP Devices.

•A license for the Xilinx design tools. For current versions of the development kit, a license for

Vivado 2020.2 is required.

–Minimum tooling is the Vivado Design Edition.

–The Vivado WebPack does not support this development kit.

–Xilinx ISE cannot be used.

•Previous experience with defining custom logic using Verilog or VHDL.

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3 Development Environment and Tools

This section describes the development kit workflow and the associated tools.

3.1 Unpacking the Development Kit

The development kit is delivered as a .zip archive containing the project files, source files and doc-

umentation. The first level of the archive contains a README file and another archive that is password

protected. By unpacking the password protected archive, the user agrees to the terms of the develop-

ment kit license. Make sure to extract the archive to a directory where the current user has read and

write permissions.

Important

By unpacking the password protected archive, the user agrees to the terms of the development kit

license.

The extracted archive is organized as follows:

<Extract root>/

constraints/ Contains the constraint files for the design.

documentation/ Contains the documentation for the development kit.

framework/ Contains the files representing the base design along with header files

to interact with the data bus. Apart from the file config.vh (see Sec-

tion 3.3.1, the files in this directory should not be modified by the user.

user_logic/ Contains the Verilog source files for the user logic areas.

license.txt Development kit license file.

devkit.tcl The Tcl file that is sourced to enable the development kit.

Note

Apart from the file config.vh (see Section 3.3.1, the files in the framework directory are not intended

to be edited by the end user.

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3.2 Opening the Development Kit

To open the development kit in Vivado, follow the steps outlined below.

1. Start Vivado

2. In the menu bar, select Tools > Run Tcl Script...

3. Open the file <Extract root>/devkit.tcl. The Tcl console will output message similar to this:

*** ADQ3 Series Development Kit ***

Revision: r59529

Usage:

devkit_setup - Create project

devkit_build - Build project

devkit_analyze - Analyze implemented design

devkit_mcs - Generate .mcs firmware file.

(Not needed if devkit_build is used.)

At this point, the Tcl commands specific to the development kit have been defined and are available in

the Tcl console. The project is now ready to be set up for first-time use.

Note

The development kit for ADQ3 series digitizers works differently compared to previous products since

building the user logic areas no longer requires special Tcl commands. See Section 3.5 for details.

3.3 Setting Up the Project

To set up the development kit, execute the command

devkit_setup

in the Tcl console. The process may take a moment to finish. Once the setup is complete, a Vivado

project has been created and the design is ready to be built. This step only has to be completed once,

after which the following directories will have been created:

<Extract root>/

artifacts/

latest/ Contains firmware files from the most recent build.

log/ Contains firmware files from previous builds.

build/ Contains all generated project files.

reports/ Contains the results from the development kit analyzer tool (see Section 3.6).

3.3.1 Configuration

The file framework/config.vh contains parameters that influence the base design. Some parameters

should not be changed by the user—these are clearly marked. Other parameters may be modified and

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serve as a way to remove modules in the base design to free up FPGA resources, provided that the

application does not require the features they provide. For example, the parameter REMOVE_FILTER

removes the built-in FIR filter if set to a nonzero value. This frees up DSP and routing resources in the

FPGA fabric.

3.4 Building the Design

To build the entire design, execute the command

devkit_build

in the Tcl console. Depending on the computer specifications and the complexity of the design as a whole,

i.e. the precomplied design and the user logic together, this may take several hours. Once the process

is complete, an .mcs file has been generated in the artifacts/latest/ directory. This file represents

a new firmware for the digitizer and may be uploaded using the ADQUpdater application. Refer to the

ADQUpdater user guide [1] for instructions on how to manage the digitizer’s firmware.

3.5 Working with the Design

This section describes the workflow of adding customized logic functions to the digitizer firmware.

3.5.1 Typical Design Flow

This section outlines the typical design flow for the development kit.

1. Set up the development kit project as described in Section 3.3.

2. Modify or insert new Verilog code into user_logic1.v or user_logic2.v. This operation can be

broken down into four steps:

(a) Extract data,data valid and other relevant bus signals using the bus extraction macros (see

Section 5).

(b) Process the extracted signals, i.e. stimulate the custom user design.

(see Section 5).

(d) Set the correct value for the BUS_PIPELINE delay parameter to keep the correct time relation

between signals that were not manually inserted.

3. Generate the FPGA configuration file (.mcs file) by using one of the two methods outlined below:

•Automatic

(a) Execute the command

devkit_build

in the Tcl console.

•Manual

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(a) Start the build by selecting Generate Bitstream in Vivado. This action will rebuild the

design and end with the bitstream generation.

(b) Once the bitstream is available, generate the FPGA configuration file by executing the

command

devkit_mcs

in the Tcl console. The configuration (.mcs) file can be found in the artifacts/latest/

directory after the process is complete.

4. Analyze the design for potential problems by executing the command

devkit_analyze

in the Tcl console and then open the HTML report in the reports/ folder. See Section 3.6 for

details.

5. Program the configuration file representing the custom design into the digitizer using the ADQUp-

dater application. Refer to the corresponding user guide [1] for details on the programming process.

6. Test the custom firmware using either

•one of the software examples available in the ADQAPI library or

•a custom user application.

3.6 Analyzing the Implemented Design

When the implementation step has completed it is highly recommended to analyze the design to detect

the most common issues. To do this, execute the command

devkit_analyze

in the Tcl console. This will run a set of checks and summarize the results into a report. The generated

report includes the current results and the difference with respect to the previous report. To keep track of

design parameter trends, it is encouraged to generate the report after every run even if no timing errors

occurred. The report is saved as an HTML file that should be opened in a web browser, see Fig. 1. There

are also several log files produced and placed in the reports/ folder that offers additional details on the

reported issues.

Tip

If a continuous integration tool is used to automate the workflow, consider integrating the output from

devkit_analyze as a part of the process.

The report is divided into six different sections. Each section has several parameters and result values.

For parameters with a maximum value the format is

Percentage[Value/Maximum value] (Difference)

ADQ3 Series FWDAQ Development Kit spdevices.com Page 9 of 38

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