ST L5965 Manual de usuario

Introduction

L5965 is a multichannel voltage regulator specifically designed to support applications that need to fulfill functional safety

requirements as defined by Automotive Safety Integrity Level (ASIL).

It is available in VQFPN-48 package.

This document describes how to use the L5965 application board in order to check device's performance.

Please refer to the datasheet.

Figure 1. L5965 evaluation board

L5965 evaluation board

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User manual

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For further information contact your local STMicroelectronics sales office.

www.st.com

1Board description

The demo board is an evaluation tool for L5965. L5965 embeds 1 controller and 1 buck that can both be supplied

by the car battery and used as pre-regulators, 2 buck post-regulators, 1 boost, 1 linear regulator and 1 precise

voltage reference. For further details on the device please refer to the datasheet.

Useful connectors available on the board:

• J1 = VBUCK1 (Buck1 output connector)

• J2 = VBAT1 (Battery input power supply, supplying Buck1 and Buck2)

• J3 = SYNCIN and ground pin connections

• J4 = SYNCOUT and ground pin connections

• J5 = Service/Voltage signals/VREF output connector

• J6 = EXTSUP (Alternative IC power supply connector)

• J11 = VBUCK2 (Buck2 output connector)

• J12 = SPI bus connector

• J14 = VBUCK3 (Buck3 output connector)

• J17 = VBUCK4 (Buck4 output connector)

• J18 = VSLDO LDO (Ldo input power supply connector)

• J21 = LDO (Ldo output connector)

• J22 = VBOOST (Boost output connector)

Figure 2. Board top view design

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2Board operation

The demonstration board is already set to allow the evaluation of the PMIC features. For a basic use, no

preliminary operation is necessary. Just connect a compatible voltage to the connector J2 (VBAT1) and check the

output signals on proper connectors.

Buck2, Buck3, Buck4, Boost and Vref are switched on automatically.

Buck1 and Ldo have been programmed in order to be enabled by SPI (for instruction, please read the product

datasheet, chapter 5). The Ldo input (J18) has to be connected by a wire with the output of a Buck regulator

(Buck2, for instance, on J11).

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3Programming option

The L5965 mounted on this demonstration board is programmed as follows (see product datasheet, chapter 6.8).

Figure 3. OTP programming

Buck2 is the main regulator and provides 3.3 V at 3 A and 0.4 MHz. This is the pre-regulator that supplies the

others. Buck3 is the second regulator to switch on, and provides 2 V. Buck4 is the third regulator, supplying 1.8 V.

The fourth regulator to start is the Boost, providing 5 V and the latest one is the VREF, 3.3 V.

The reset is released after the Power Good of the main regulator (Buck2). In case of failures, the RESET_B signal

doesn’t affect the State Machine, then the regulator can still be evaluated in this condition. Also an overvoltage

cannot assert a reset. All these regulators turn on with a delay of 10 ms among them.

Buck1 and Ldo should be enabled by SPI. Once enabled, Buck1 provides 1.2 V and the Ldo supplies 1.3 V at 600

mA.

A watchdog is not required to operate the PMIC and rewriting OTP programming is forbidden.

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Programming option

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4SPI connector

SPI signals are available on the J12 connector.

The SPI bus can be also used to monitor the PMIC diagnostics.

Figure 4. Demo board SPI connector

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SPI connector

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5Board schematic

Figure 5. Board schematic

SYN CIN

SYN COUT

REF

RESET _B

VREG

Debug

CLK

CSN

WDI

CLK

CSN

REF

WKU P

WDI

RESET _B

FAULT

VREG

FAULT

WKU P

C11

47nF

0.06R 1W 683-6580

C2 100nF

0 n.m.

47K

R12 100K

R23 0R

C14 2.2nF

CONN 2.54X7

R280R

L5 6.8uH

C17

3.3uF

R35

1.25K

C21

220nF

C26

3.3uF

0 n.m.

2.2uF 25V

C20

47nF

J12

CONN 2.54X6

R130R

L3 2.2uH

C10

100nF

J25

C16

47nF

R140 n.m.

10uF

J21

+C29

22uF 40V

J26

C22

3.3uF

C24

100nF

C23

3.3uF

R10 20K

R15 100K

C1100nF

R22 0R

2J1

C18

3.3uF

2J22

R70R

R5 47K

+C28

100uF 40V

J24

R190R

R24 0R

2J11

2J17

C12

10uF

C25

3.3uF

C9 910pF

100nF

R16 10K

C27

3.3uF

C15

100nF

J10

C19

100nF

R30 1.8K

2J14

+C8

470uF 40V

R17 10K

R21 0R

L1 15uH

R27 10K

C13

10uF

VBOOST_S 28

EX TSU P

VREG

BST1 5

GH1 6

PH1 7

GL1 8

PGND1 9

DGND

VREG 1_S 13

COMP1 12

VBAT2 33

BST2 34

PH2 32

PGND2 31

VREG 2_S 30

COMP2 29

VIN3 16

BST3 15

PH3 17

PGND3 18

PH4 22

BST4 24

VIN4 23

VREG 3_S 19

VBAT1

AGND

SGND

Sensen 11

SYNCIN

Sensep 10

SYNCOUT

REF

VSLD O

LD O

FAULT

WDI

RESET_B

WKUP

Debug

CSN

CLK

PGND5

PH5 26

VREG 4_S 20

PGND4 21

L5965_QFN48

J18

R330R

10uF

GNDANA

VBUCK2

VBUCK2_po l

VBAT1

VBUCK2_po l

VBAT1

VBUCK2_po l

VBUCK1

VBUCK3

VBUCK4

VBUCK5

VBUCK2_po l

VBUCK2

LD O

VBAT1

EX TSU P

VBUCK1

VBAT1

SYNCIN

SYNCOUT

No Jumpe r

VBAT1

EXSUP

VSLDO

1.3V

VBUCK5 5V

VBUCK4 1.8V

VBUCK3 2V

VBUCK2 3.3V 3A

VBUCK1 1.2V

VBAT1

CSN

CLK

GND

Debu g

WDI

REF

WKUP

RESET_B

FAULT

VREG

GND

C30

100uF 40V

1 5

ST L11N4LLF5

XAL1010-153

C31

100uF 40V

L2 15uH

XAL1010-153

C32

100uF 40V

XAL7070-222

L4 2.2uH

XAL7070-222

C33

100uF 40V

XAL1010-682

TP1

PGND

C34100nF

C35100nF

PGND5

PGND5 PGND5

PGND5

PGND4 PGND4

PGND3 PGND3

PGND2 PGND2

PGND1PGND1

PGND1

PGND2

PGND3

PGND4

PGND4PGND3PGND2PGND1

R9 0R

R11 0R

1 2

ST PS5 L60-Y

GNDANA

3.3V

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Board schematic

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6Information on board use

This evaluation board/kit is intended for the following uses:

• Engineering development

• Demonstrations

• Evaluation purposes only

It is not considered by ST Microelectronics (STM) to be a finished end-product fit for general consumer use. The

people who handle the product(s) must have electronics training and must observe good engineering standard

practices.

For this reason the goods being provided are not intended to be complete in terms of required design, marketing,

and/or manufacturing-related protective considerations, including product safety and environmental measures

typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation

board/kit does not fall within the purpose of the European Union directives regarding electromagnetic

compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the

technical requirements of these directives or other related directives.

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Revision history

Table 1. Document revision history

Date Version Changes

17-Jun-2019 1 Initial release.

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Contents

1Board description .................................................................2

2Board operation ...................................................................3

3Programming option...............................................................4

4SPI connector .....................................................................5

5Board schematic ..................................................................6

6Information on board use ..........................................................7

Revision history ........................................................................8

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IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST

products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST

products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of

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No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service

names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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Tabla de contenidos

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