SpinCore Technologies PulseBlasterESR DualCore 8M Manual de usuario
PulseBlasterESR DualCore 8M™
Owner’s Manual
SpinCore Technologies, Inc.
http://www.spincore.com
PulseBlasterESR DualCore 8M
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Technologies, Inc.
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© 2009-2013 SpinCore Tec nologies, Inc. All rig ts reserved.
SpinCore Tec nologies, Inc. reserves t e rig t to make c anges to t e product(s) or information erein wit out notice. PulseBlaster-
DualCore™, PulseBlaster™, SpinCore, and t e SpinCore Tec nologies, Inc. logos are trademarks of SpinCore Tec nologies, Inc. All ot er
trademarks are t e property of t eir respective owners.
SpinCore Tec nologies, Inc. makes every effort to verify t e correct operation of t e equipment. T is equipment version is not intended for
use in a system in w ic t e failure of a SpinCore device will t reaten t e safety of equipment or person(s).
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PulseBlasterESR DualCore 8M
Table of Contents
I. Introduction ............................................................................................................................... 4
Product Overview ................................................................................................................... 4
Programming Paradigm ......................................................................................................... 4
Specifications .......................................................................................................................... 5
II. Installing and Using Your PulseBlasterESR DualCore ......................................................... 6
Installation ............................................................................................................................... 6
General API Programming Information .................................................................................. 6
Triggering PulseProgram Execution ....................................................................................... 7
Stopping PulseProgram Execution ......................................................................................... 7
III. Test Programs ....................................................................................................................... 8
Example Programs ................................................................................................................. 8
Example 1 ........................................................................................................................ 8
Example 2 .......................................................................................................................... 9
Example 3 ........................................................................................................................ 10
Example 4 ......................................................................................................................... 11
Example 5 ......................................................................................................................... 12
Example 6 ......................................................................................................................... 12
IV. Appendices ......................................................................................................................... 13
Appendix A: Connectors ....................................................................................................... 13
HW_TRIG/RESET Header ............................................................................................... 13
CLOCK Header ................................................................................................................. 14
Appendix B: Hardware Triggering/Reset .............................................................................. 14
Appendix C: Sync ronization of Multiple Boards ................................................................. 15
V. Related Products and Accessories ....................................................................................... 16
VI. Contact Information ............................................................................................................. 17
VII. Document Information ....................................................................................................... 18
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PulseBlasterESR DualCore 8M
I. Introduction
Product Overview
T e SpinCore PulseBlasterESR DualCore 8M is a dual-core PulseBlaster design implemented on a new
series of PulseBlasterESR PCI boards wit up to 4194304 instruction per core. T e dual-core design uses two
of SpinCore's proprietary PulseBlaster processor cores on a single c ip. T is new design allows t e user to
program and run completely independent programs on eac core, in parallel, w ile maintaining precise timing
sync ronization between eac core.
Diagram 1 : SpinCore PulseBlasterESR DualCore Design Arc itecture
Bot cores are driven by t e same single clock source at 500 MHz. T ey are sync ronized to start at t e
same time and run unique pulse programs/sequences concurrently. At 500 MHz, t e available resolution of
eac pulse/delay/interval is 2.00 ns (one clock cycle), t e minimum pulse/delay/interval lengt is 18 clock cycles,
or 36 ns, and t e maximum pulse/delay/interval lengt is 229 clock cycles (~1.07 seconds). Eac core as 4M
(4194304) memory words available for writing pulse programs, i.e., t ere can be up to 4194304 lines in your
pulse program per core.
T e basic arc itecture of t e individual PulseBlaster processor core is described in multiple documents,
including t e manuals for PulseBlaster and PulseBlasterESR boards, available on-line at t e SpinCore's website
www.spincore.com. (Note t at t e PulseBlasterESR DualCore uses simplified PulseBlaster Cores t at allow for
'continue' and 'stop' operations only.)
Programming Paradigm
Eac core can be individually programmed wit an arbitrary sequence of intervals. Eac interval can be of
unique lengt , and up to 4M intervals can be accommodated per sequence. Since eac interval can be a pulse
or a delay, t e programming of eac core involves t e loading of two basic parameters per interval: t e output
state (logical 0 or 1), and t e duration of t e state (in nanoseconds, microseconds, milliseconds).
Eac core can be independently programmed and triggered. T e low-level interaction is accomplis ed
t roug a dedicated Application Programming Interface (API) package called t e DualCore SpinAPI, available
for download on SpinCore's website: www.spincore.com. Virtually any ig er-level application package
(Matlab, LabVIEW etc.) can interact wit t e board t roug t e provided SpinAPI functions.
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PCI Interface
SRAM
4M Words
PulseBlasterTM
Timing Core 1
Host PC
SRAM
4M Words
PulseBlasterTM
Timing Core 0
Memory Controller
Memory Controller
Clock and Triggering
Circuitry
Flag 0
Flag 1
PulseBlasterESR DualCore 8M
Specifications
Parameter Min Typ Max Units
Digital Outputs Number of Digital Outputs 2
Logical 1 Output Voltage 2.00(1) 3.3 V
Logical 0 Output Voltage 0 V
Output Drive Current 40 mA
Rise/Fall Time <1 ns
Digital Inputs
(HW_Trig, HW_Reset)
Logical 1 Input Voltage 1.7 3.3 V
Logical 0 Input Voltage -0.5 0.7 V
Pulse Program Number of Cores 1 2 > 4
Number of Instruction (per Core) 4194304 instructions
Pulse Resolution 2.00 ns
Pulse Lengt 36 ns ~1.07 s
Supported Operations CONTINUE, STOP
Table 1: Specifications of t e PulseBlasterESR DualCore Design
(1)T is value is wit a 50Ω terminating resistance.
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PulseBlasterESR DualCore 8M
II. Installing and Using Your PulseBlasterESR DualCore
Installation
To install t e board you must complete t e following t ree steps:
1) Install t e latest MultiCore SpinAPI package, available ere.
–T e DualCore PulseBlasterESR board requires a specialized version of SpinAPI called t e
MultiCore SpinAPI.
2) S ut down computer, insert t e PulseBlasterESR DualCore 8M card, and fasten t e PC bracket.
–Your system s ould detect t e board as a “PulseBlaster Multicore” device.
3) Power up and follow t e installation prompts.
Now you are ready to run t e test programs provided in t e SpinAPI package.
Note: To compile and run your own C programs, you may want to download t e SpinAPI Tools package t at
contains a pre-configured compiler; t e SpinAPI Tools package is also available for download at t e URL above.
General API Programming Information
Seven test programs (executables and t eir C source files) are available for testing. Assuming t e default
installation, t e test programs will be available on t e computer at t e following location: Start → All Programs
→ SpinAPI → Examples → DualCore Examples (t e default installation location is:
“C:\SpinCore\SpinAPI\Examples\DualCore Examples”). T e .c files can be modified and recompiled to create
custom test programs.
T e SpinAPI programming paradigm is simple:
1.Include t e “spinapi. ” in your C-file and link your executable to t e SpinAPI library.
2.Initialize t e API by calling t e function pb_init(). T is function must be called and return successfully in order
for t e API to function properly.
3.If t ere is more t an one board installed in your system, select t e correct board by calling
pb_select_board(board_number).
4.Tell t e API t e board's internal operating clock frequency. T is can be done by calling
pb_set_clock(clock_freq) wit t e appropriate internal operating frequency (500 MHz for t e PulseBlasterESR
DualCore 8M.)
5.Start programming a PulseProgram memory device. T is can be accomplis ed by calling
pb_start_programming(device). T e available devices on t e PulseBlasterESR DualCore 8M are t e
C RE0_MEM (core 0's PulseProgram memory) and C RE1_MEM (core 1's PulseProgram memory.)
6.Begin programming a PulseProgram sequence. A CONTINUE instruction can be programmed by calling
pb_inst(flag, time_ns). A STOP instruction can be programmed by calling pb_inst_stop().
Note: T e last instruction in t e PulseProgram must be a STOP instruction, or t e program will loop infinitely.
7.Stop programming t e selected device. T is can be accomplis ed by calling pb_stop_programming().
8.Select w ic cores are enabled by calling pb_core_select(core_mask). Eac bit of t e core mask corresponds
to t at core being enabled (i.e. bit 0 corresponds to core 0.)
9.Trigger t e selected cores by using pb_start(), or reset t e board wit pb_stop().
10.Close t e API by calling pb_close().
For more information on using t e DualCore SpinAPI, see t e “SpinAPI Reference Manual.pdf” found in t e
SpinAPI directory.
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PulseBlasterESR DualCore 8M
Triggering PulseProgram Execution
T e PulseBlasterESR DualCore can be triggered in two ways, eit er by software trigger or ardware trigger.
T e software trigger is initiated by sending a command from t e ost PC via t e pb_start() function. Since t e
PulseBlasterESR DualCore boards are typically used wit non real-time operating systems, t e exact time
between issuing a software trigger and t e board acting on t at trigger cannot be precisely specified. For
precision control, t e pulse program can also be triggered by setting t e HW_Trigger pin to a logical 0. T is will
cause t e pulse program to be triggered wit a latency of seven clock cycles. For more information on t e
ardware trigger, see Appendix B: Hardware Reset/Triggering.
Stopping PulseProgram Execution
T e PulseBlasterESR DualCore can be stopped by using eit er t e software or ardware reset. T e
software reset is initiated by sending a command from t e ost PC via t e pb_stop() function. Since t e
PulseBlasterESR DualCore boards are typically used wit non real-time operating systems, t e exact time
between issuing a software reset and t e board acting on t at reset cannot be precisely specified. For precision
control, t e pulse program can also be reset by setting t e HW_Reset pin to a logical 0. T is will cause t e
pulse program stop and t e program counter to reset wit in one clock cycle. For more information on t e
ardware reset, see Appendix B: Hardware Reset/Triggering.
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PulseBlasterESR DualCore 8M
III. Test Programs
Example Programs
Seven test programs ave been packaged wit t e SpinAPI driver suite to illustrate t e basic features and
functionality of t e PulseBlasterESR DualCore 8M design. All programs can be found at: Start → All Programs
→ SpinAPI → Examples → DualCore Examples (t e default installation location is:
“C:\SpinCore\SpinAPI\Examples\DualCore Examples”).
Example 1
T e first test program, pb_dualcore_example1.c demonstrates t at bot cores (c annels) can generate
identical pulses t at are precisely sync ronized.
An excerpt from t e code to program t e cores is as follows:
PulseProgram 1: Excerpt from pb_dualcore_example1.c
In Example 1, bot cores are programmed wit identical content. Later in t e program, bot cores are
triggered at t e same time using pb_start(). T e resulting output s ould be four identical 50.0 ns pulses on
BNC0 and BNC1.
NOTE: W en attac ing an oscilloscope to t e board to observe t e pulses, care s ould be taken to use
cables of t e same type and lengt for eac c annel, as skew can be induced due to propagation delays.
Conversely, any in erent variations in on-c ip propagation delays can be compensated by appropriate variations
in cable lengt .
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//********* Program Core0 ******************-/
pb_start_programming (CORE0_MEM);
pb_inst(1, 50.0 * ns);
pb_inst(0, 50.0 * ns);
pb_inst(1, 50.0 * ns);
pb_inst(0, 50.0 * ns);
pb_inst(1, 50.0 * ns);
pb_inst(0, 50.0 * ns);
pb_inst(1, 50.0 * ns);
pb_inst_stop();
instruction_count += pb_stop_programming ();
//******** Program Core1 ************************-/
pb_start_programming (CORE1_MEM);
pb_inst(1, 50.0 * ns);
pb_inst(0, 50.0 * ns);
pb_inst(1, 50.0 * ns);
pb_inst(0, 50.0 * ns);
pb_inst(1, 50.0 * ns);
pb_inst(0, 50.0 * ns);
pb_inst(1, 50.0 * ns);
pb_inst_stop();
instruction_count += pb_stop_programming ();
PulseBlasterESR DualCore 8M
Example 2
T e second example is composed of two separate files: pb_dualcore_example2a.c and
pb_dualcore_example2b.c. Eac of t ese examples are used to program one core wit a pulse sequence (50 ns
on/50 ns off) t at will occupy t e entire 4M instruction memory, and one core wit a single pulse t at is on for t e
equivalent pulse program time. T is allows for verification t at t e core's full memory is working properly and
t at t ere are no timing inaccuracies in any of t e 4M instructions.
•pb_dualcore_example2a.c : Tests core0's entire Pulse Program memory, and uses core1 to generate t e
equivalent time pulse.
•pb_dualcore_example2b.c : Tests core1's entire Pulse Program memory, and uses core0 to generate t e
equivalent time pulse.
An excerpt from t e code to program t e cores is as follows:
PulseProgram 2: Excerpt from pb_dualcore_example2a.c
Later in t e program, all bot cores are triggered at t e same time using pb_start().
NOTE: W en attac ing an oscilloscope to t e board to observe t e pulses, care s ould be taken to use
cables of t e same type and lengt for eac c annel, as skew can be induced due to propagation delays.
Conversely, any in erent variations in on-c ip propagation delays can be compensated by appropriate variations
in cable lengt .
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//********* Program Core0 ******************-/
pb_start_programming (CORE0_MEM);
i=0;
w ile(i<FULL_MEMORY_SIZE-2) {
pb_inst(1, 50.0*ns);
pb_inst(0, 50.0*ns);
i+=2;
}
pb_inst(1, 50.0*ns);
pb_inst_stop();
instruction_count_count += pb_stop_programming ();
//******** Program Core1 ******************-/
pb_start_programming (CORE1_MEM);
pb_inst(1, (FULL_MEMORY_SIZE*50.0)*ns);
pb_inst_stop();
instruction_count_count += pb_stop_programming ();
PulseBlasterESR DualCore 8M
Example 3
T e t ird test program, pb_dualcore_example3.c, demonstrates creating Pulse Programs wit an adjustable
offset between t e first pulse as low as 2.00 ns. W en t e program is run, t e user will be prompted for t e
offset between t e two cores. T is must be a multiple of 2.00 ns.
An excerpt from t e code to program t e cores is as follows:
PulseProgram 3: Excerpt from pb_dualcore_example3.c
Later in t e program, all bot cores are triggered at t e same time using pb_start(). W en t e board is
triggered, t ere s ould be two 50.0 ns pulses on BNC0 and BNC1, wit t e pulses on BNC0 starting t e
specified offset after t e pulses on BNC1.
Note t at t e offset of down to 2.00 ns is created by aving an initial instruction wit at least t e minimum
pulse lengt .
NOTE: W en attac ing an oscilloscope to t e board to observe t e pulses, care s ould be taken to use
cables of t e same type and lengt for eac c annel, as skew can be induced due to propagation delays.
Conversely, any in erent variations in on-c ip propagation delays can be compensated by appropriate variations
in cable lengt .
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//********* Program Core0 ******************-/
pb_start_programming (CORE0_MEM);
pb_inst(0, 36.0*ns + offset);
pb_inst(1, 50.0*ns);
pb_inst(0, 50.0*ns);
pb_inst(1, 50.0*ns);
pb_inst_stop();
instruction_count += pb_stop_programming ();
//********* Program Core1 ******************-/
pb_start_programming (CORE1_MEM);
pb_inst(0, 36.0*ns);
pb_inst(1, 50.0*ns);
pb_inst(0, 50.0*ns);
pb_inst(1, 50.0*ns);
pb_inst_stop();
instruction_count += pb_stop_programming ();
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