REFERENCE MANUAL Si5361/62/63
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10 March 21, 2023
3.1. Dividers
The Si5361/62/63 has both fractional and integer frequency dividers. The block diagrams in Figures 6 and 7 show
the location of each divider and how it fits into the signal flow for all the three devices. The ClockBuilder Pro soft-
ware will choose the optimal divide values based on the frequency plan the user wishes to create. A description of
each type of divider is listed below:
• Input P Divider: P3, P3b, P2, P2b, P1, P0
- Integer or Fractional Divide Value
- Minimum value is 1
• DSPLL P Output Q Divider: Q17-Q0
- Integer Only Divide Value
- Open loop divider taps directly off VCO
• DSPLL A/B Output NA, NB Divider
- MultiSynth Divider
- Fractional Divide Value
• DSPLL A/B Feedback MA, MB Divider
- Fractional Divide Value
• Output R Divider: R17-R0
- Integer Only Divide Value
- Minimum value is 2 if signal comes from NA/NB; Minimum value is 1 if signal comes from Q divider
3.2. DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. The DSPLL loop bandwidth is
configurable within the range of 20 Hz to 4 kHz. The loop bandwidth is controlled digitally and remains stable with
less than 0.1 dB of peaking for any loop bandwidth selected. The DSPLL loop bandwidth can be set using
ClockBuilder Pro or from Device API commands during operation. In general, increasing PLL bandwidth speeds up
lock acquisition while decreasing jitter attenuation. For DSPLL P, using loop bandwidth between 20 Hz to 40 Hz
provides a good optimization for both jitter and wander performance.
Selecting a low DSPLL loop bandwidth will generally lengthen the lock acquisition time but also increase jitter
attenuation. The Fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock
acquisition process to reduce lock time. Higher Fastlock loop bandwidth settings enable the DSPLLs to lock faster.
Once lock acquisition has completed, the loop bandwidth of the DSPLL automatically reverts to the nominal DSPLL
Loop Bandwidth setting. The Fastlock feature can be enabled or disabled independently using ClockBuilder Pro. If
enabled, when LOL is asserted Fastlock will be automatically applied. When LOL is no longer asserted Fastlock will
automatically be disabled. The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL
feature can be found in the fault monitoring section.
For more information, see AN1365: Si5361/62/63 Lock Time Parameters.
3.3. Output Skew Control
Output skew control allows outputs that are derived from the Q dividers to be phase adjusted in steps of 1/fVCO
or 1/(4*fVCO), when fine adjust is enabled. Output skew is programmable and the output delay adjustment range
is displayed in ClockBuilder Pro.
In addition to output skew control, groupings of Q divider clock outputs can be adjusted with dynamic phase
adjust. Dynamic phase adjustment changes the phase of grouped clock outputs to be earlier or later. For more
information see the Device API documentation.
