Seattle Computer Products 8086 CPU Manual de usuario

Instruction Manual

Model

SCP

2008

BOB6CPU

16-BitProcessorforthe

5-100

Bus

Rev.S

10-1-80

Asaattla

(omputar

Products,Inc.

1114 Industry Drive. Seattle.

WA.

98188

(206) 575-1830

TABLE

CONTENTS

Features

Configuration

Options.

Technical

Description.

General

2.0

Features

and

Comparisons

IEEE

Standard.

3.0

S-100

Connector

Layout.

4.0

A.C.

Characteristics.

Theory

Operation.

One-Year

Limited

Warranty.

- 2 -

.10

.14

.21

Features

>Advanced

16-bit

architecture

the

8086 includes aversatile range

addressing modes,

hardware

multiply and

divide,

and high-speed

string

operations.

>Fully meets IEEE-696 standard

for

16-bit

operation

the

5-100

bus,

allowing

maximum

throughput.

Completely

compatible

with

8-bit

memory

and

I/O

devices

with

reduced

performance.

Directly

addresses up

1megabyte

memory,

eliminating

the need

for

"bank select".

>Has aminimum

instruction

execution

time

only

250 nanoseconds,

yet

needs

"wait

states"

with

static

memory

250 nsec.

faster.

>Entire design

conforms

IEEE-696 standard

for

the

5-100

bus.

>Configurable

meet awide range

system requirements

through

its numerous switches and

jumpers.

Configuration Options

SWITCH

SELECTED

OPTIONS

5-1,

located

near the

top

the

board

between U4 and U5 has

three

active

segments. The

segments

the

switch

and

their

function

are:

Segment 1:

Not

used

this

board.

Segment 2: Sixteen aCknowledge

the closed

position

allows the

CPU

look

the

sXTN*

line

determine

the

peripheral

being accessed can

asixteen

bit

transfer.

The open

position

forces

the

CPU

all

eight

bit

transfers. The

switch

provided

because

some

the

early

eight-bit

systems used this line (60)

for

another

purpose.

The

switch

allows the user

another

capability

well.

It allows

him

compare

program

execution

time

differences

while

using

eight-bit

sixteen-bit

memories.

Segment

This

switch

selects between

and

operation

with

8MHz

CPU

cards.

The

closed

position

selects 4MHz, open selects 8MHz. On 4MHz CPU cards this

switch

segment is

defeated by ajumper and

has

effect;

the

CPU

always runs

4MHz.

Segment 4: Closing this

switch

adds

one

wait

state

each

bus

cycle.

If a

peripheral

has

it's

own

wait

state

generator,

closing

segment 4adds one

wait

state

addition

the one(s) requested

the

peripheral.

With

the

4MHz

clock,

memory

chip speed requirements

are

in excess

450n5.

8MHz, 250nS

faster chips must be used. Thus,

with

most

memory,

and a4MHz

clock,

wait

states are required and the

switch

segment should remain in the "open"

off

position.

- 3 -

JUMPERS

There are six jumpers on the

board

allow

configuring

your

CPU

for

special

situations.

The

chart

below

shows

their

"normar

positions.

NAME

NO~MAL

POSITION

~EMA~KS

STV (Status

Valid)

"0" Used

with

OMA

STK

"E"

Used

with

DMA

1-0

"8" Puts

lower

8-bit

1-0

address on

upper

8-bits

PHANTOM*

"+"

Connects

PHANTOM* line

SXI<Q

(sXTRQ*)

"+"

Connects Sixteen Request line

MWRITE

"+"

Connects

MWRITE

line

Each

these jumpers

will

be discussed in

detail

enable

you

determine

you

should change them

the alternate

position.

STV (Status

Valid)

this jumper

controls

the

function

the pSTVAL* line (S-100

25)

during

OMA:

the

"E"

position

the CPU always drives the pSTVAL*line.

the

"Ui

position

this line

three-stated

when

COSH*

(control

disable, S-100

19)

low

allowing

the OMA

device

drive

it.

STK

this jumper

controls

the

function

the

"SPEED"

line (S-100 pin

98)

during OMA.

the

"E"

position

the CPU always drives this line

with

ahigh

indicate

8MHz

operation

low

indicate

operation.

the

"D"

position,

this line

three-stated

when

SDSl:3·

(status disable,

5-100

18)

low

allowing

the

UMA

device

drive

it.

1-0

the

normal

"8"

position,

this jumper copies the

lower

8bits

I-Q

address

information

onto

the

higher

8address bits. If

your

1-0

devices

use

16-bit

address, the

jumper should

in the

16-bit

position.

Most

existing

I-Q

devices use addressing in

which

the

lower

and middle address bytes are the same.

The

upper address byte,

A16-A23,

never used in

I/O

addressing.

PHANTOM*

This

CPU

board

generates aPHANTOM* signal whenever

addresses

memory

locations

located

above

the

lowest

64K. This signal may be used

disable

older,

8-bit

memory

cards

which

not

have extended addressing. Through the

use

this PHANTOM· signal, asystem

may be

composed

64K

the

older,

non-extended

addressable

memory

which

would

located

in the

lowest

64K and

newer,

extended addressable

memory,

located

in the higher

addresses. The PHANTOM* signal

would

prevent

the

older

memory

from

interfering

with

the

memory

located

the higher addresses. If

your

system

uses

this signal

for

some

other

purpose,

the

PHANTOM* generated

the CPU

board

should be disconnected

from

the

bus

putting

the

PHANTOM* jumper in the "_"

position.

sXT~Q*

The Sixteen Request signal

generated by the

CPU

whenever

wants

16-bit

transfer.

our

system, using

16-bit

memory,

this jumper should be

connected

in the

"+"

postion.

you

not

have

16-bit

memory

your

system, the signal

would

serve

purpose and

the jumper

could

either

position.

your

system

uses

bus

line 58

for

some

other

purpose, the

sXT~Q*

line should be

disconnected

between the

CPU

and the

bus

by placing the jumper in the "_"

position.

- 4 -

•

MWRITE

This jumper connects the

MWRITE

line

the

CPU

board

the bus. It

normally

connected

and used by

most

systems

the

primary

write

line. It should be disconnected

MWRITE

generated somewhere else in the system, such

on a

control

panel

the

motherboard.

Disconnect by placing the jumper in the

"_"

position.

Technical

DescrlpUon

1.0 General

The SCP-2oo

CPU

card

Intel 8086

CPU

chip

with

the

electrical

and mechanical hardware

interface

the 5-100

bus

accordance

with

the

proposed

IEEE

standard. It may be used

upgrade the

performance

present S-1oo systems by swapping

CPU

cards

may

form

the

foundation

ahigh

performance

16-bit

computer.

Some

prior

knowledge

the fundamentals

the S-1oo

bus

is essential

understanding this

document.

thorough

understanding requires

familiarity

with

the

IEEE-696 standard

for

the S-100

bus. The asterisk

(*)

denotes

active-low

signal.

2.0

Features and Comparisons

Proposed Standard

2.1

Clock

All

timing

signals are

derived

from

on-board

24 MHz

oscillator.

The

clock

rate

the

8086 chip itself

either

8MHz. A

lower-priced

version

the

board

capable

4MHz

operation

only,

while

the

higher-priced

version

has

switch

selection

either

a 4

8MHz

clock.

All 4

MHz-only

CPU cards are

factory

upgradable

4/8

MHz.

On the bus, CLOCK (pin 49) is always 2MHz,

while

pSTVAL*

(formerly

m1,

25)

and

(formerly

~2,

pin 24) are equal

the

clock

frequency

the

CPU

8MHz). All three are

approximately

square waves. pSTVAL*and

are equal in phase,

but

pSTVAL*may be

configured

be disabled

(tristate)

by CDSB* (pin

19)

while

never disabled.

The 8086 allows 3

clock

cycles

for

memory

access (minus delays and setup

time).

8MHz,

250

memory

required

while

4MHz,

over

500

access

time

allowed.

(see

section

4.)

time

is required, the

card

may

switched

insert

wait

state in

every

bus

cycle•

addition, the line

formerly

named sSTACK (pin 98)

driven

with

clock

speed

status--high

for

MHz,

low

for

MHz.

This may be used

control

wait

state

generators

peripherals.

2.2 Data

Bus

The 8086

CPU

chip

is a

16-bit

processor

which

interfaced

the S-100 bus by the

support

logic in

either

two

modes:

8-bit

mode

16-bit

mode.

The

mode

selected dynamically

the

beginning

each

bus

cycle, depending on

CPU

status and

bus

response,

follows:

2.2.1 sXTKQ*, SIXTN*

the

processor

wishes

read

write

16 bits, sXTRO* (pin 58) on the

bus

driven

low.

The

addressed device may then respond by pulling

low

SIXTN* (pin 60)

can

perform

16-bit

parallel

transfer.

Timing

for

SIXTN* is the same

the READY lines

(RDY/XRDY)--it

must be valid 50

before

the rising edge

that

ends pSYNC. An

exception

this

that

wait

state

requested (externally

on-board),

SlXTN* may be delayed until

near

the end

the last

wait

state.

SIXTN*

latched on the rising edge

either

near the end

pSYNC

near the end

the last

wait

state, and changes

after

this

time

are

irrelevant.

If, at the

time

SIXTN*

latched,

high

(inactive),

then sXTRO*

removed

and

double

8-bit

mode

is selected.

Utherwise,

sXTRO* is kept

low

and

16-bit

mode is selected.

Should

the

8086 CPU .card be used in asystem

which

previously

defined a

conflicting

use

for

bus

pins

60,

either

both

these lines may

disconnected

from

CPU

logic.

this case,

16-bit

mode

not

possible.

- 5 -

2.2.2

8-Bit

Mode

2.2.2.1

Simple

8-Bit

Mode. This

mode

used when the

processor

wishes

transfer

only

byte.

Logic

the

card

routes

data

from

the

bus

the processor's

low

8data lines (read even

location);

from

the

bus

the processor's high 8

data

lines (read

odd

location);

from

the

processor's

low

8data lines

the

bus

(write

even

location);

from

the processor's high 8

data lines

the

bus

(write

odd

location).

2.2.2.2

Double 8-l:Jit Mode. This

mode

is used when the

processor

wishes

transfer

word

even address but the

memory

I/O

device

not

capable

16-bit

operation.

The

processor

put

into

wait

state

for

least 4

clock

periods

while

on-board

logic

runs

two

bus

cycles

back

-to-back,

first

the even address, then

the

odd.

Each

bus

cycle

essentially the same

simple

8-bit

mode

above,

except

the data resulting

from

the

first

two

read cycles is latched until

the second

cycle

complete.

2.2.3

16-l:Jit Mode

this mode, 16 bits

data are

transferred

in parallel in one

bus

cycle.

The DO lines

carry

data

to/from

the even addressed

location

(processor's

low

8data lines), and

the

lines

carry

data

to/from

the odd addressed

location

(processor's high 8

data

lines).

2.2.4 Data

Driver

Disable

I:Jringing

low

OOOSB* (pin

23)

will

disable

both

the data

input

and data

output

drivers.

2.2.5 Co

mpatibility

The techniques

for

mode

selection and

16-bit

transfer

are in

strict

accordance

with

the

proposed

IEEE

standard. They allow the CPU

run

without

modification

with

ordinary

8-bit

memory

(for

easy upgrade),

with

new

16-bit

memory

(for

high

performance),

even

amixed

environment

(e.g.,

16-bit

memories

time-critical

code

areas).

2.2.6

Oata Line

Connector

]1, a

16-pin

socket,

provided

allow

monitoring

the data lines

the 8086

CPU

chip.

Pins

this

socket

are

connected

ADO

AD15

the

8086, respectively.

Further,

by using

DOD5~*

disable the data

drivers

when the

board

reading (pOBIN

active),

arbitrary

instructions

data may be fed

8086

through

this

connector.

2.3

Address

!:Jus

2.3.1

Memory

Address

The

proposed

IEEE

standard dedicates 24 pins on the

bus

for

memory

address

information.

All 24 are

driven

by the CPU

card;

however

since

the

8086 chip

itself

generates

only

bits

address,

A20-A23

are always

driven

low.

2.3.1.1 Phantom

Traditionally,

5-100

memory

cards have decoded

only

the

lowest

16 address lines,

limiting

their

address space

64K bytes.

Ordinarily,

use

such cards in asystem

with

than

64K

not

possible because these cards

will

appear in the same

relative

position

in each 64K

block.

However,

special

provision

has

been made on

the

8086 CPU card, selected by ajumper: Whenever a

memory

location

ABOVE

the

lowest

64K is addressed, PHANTOM* (pin 67)

driven

low,

which

may

used

disable

memories

with

16-bit

address.

Thus

these memories appear only in the

lowest

64K, when PHANTOM* is

not

being

driven.

The

PHANTOM*-driving

circutiry

on the

CPU

card

continues

function

during DMA. Thus

OMA

controllers

which

use

24-bit

address need

not

concerned

with

the presence

memories

using

only

16-bit

address. - 6 -

2.3.2

"put/Output

Address

The

proposed

standard allows and the 8086

CPU

chip

supports a

16-bit

I/O

address.

However,

traditionally

the

lower

8bits and

upper

8bits

the address have been the same, and

/".

unfortunately

many devices have been designed

which

decode

their

I/O

address

from

the upper 8

lines. To maintain

compatibility

with

such devices the

support

logic

can be jumpered

throw

away

the

high 8bits

the 8086's

I/O

address and substitute

the

low

bits.

2.3.3 Address

Driver

Disable

Bringing

low

ADSB* (pin

22)

will

disable the address

drivers.

2.4 Status

Bus

The

CPU

card

drives all status lines in

accordance

with

the

proposed

standard. They are:

NAME

sMEMR

sM1

slNP 46

sOUT 45

sWO* 97

slNTA 96

sHLTA

sXTRQ* 58

2.4.1 Status

Driver

Disable

Hringing

low

SDSH*

(pin 18)

will

disable the status

drivers.

Clock

speed status, pin 98, may

optionally

disabled by this signal

necessary,

be consistent

with

its

traditional

definition

the

sST

ACK status line.

2.5

Control

Bus

All

control

lines are in

accordance

with

the

proposed

standard. They are:

OUTPUTS

INPUTS

pSYNC

ROY

pSTVAL- 25

XROY

pDBIN

I-

pWI<-

77 NMI-

lOA

HalO-

SIXTN- 60

Traditionally,

another

control

line

has

been

pWAIT

(pin

27).

This line is

driven

by the

CPU

card

and

goes high

pSYNC goes

low

the

bus

put

into

wait

state.

2.5.1

Control

Driver

Disable

Bringing

low

CUSH- (pin 19)

will

disable the

control

drivers.

Traditionally,

pin 25,

now

pSTVAL

has

not

been disabled by this signal. Ajumper

provided

select whether

not

will

be disabled.

- 7 -

2.6

Power

Supply

Only

+8V (pins 1&

51)

and GROUND (pins 50 &

100)

are used

for

power.

Two

on-card

regulators

provide

Vat

1.2 A

(typical)

all

circuitry.

2.7

Other

lines

2.7.1 Reset

POC* (pin 99)

totem-pole

output

driven

low

momentarily

when

power

first

applied

the

card.

During this

time

RESET*

(pin 75),

normally

input,

also

driven

low.

The

CPU may be

reset

any

time

driving

RESET·

low

for

cycles.

After

reset,

the

8086

will

begin

program

execution

OFFFFOH.

See

Intel's 8086 Family User's

Manual

rdetails.

2.7.2

MWKITE

The

CPU

card

normally

generates

MWKITE

(pin

68).

this

signal is generated elsewhere

the

system, this

function

may

defeated by

removing

ajumper.

2.8

Front

Panel

mpatibility

There

currently

hardware

front

panel

for

the 8086

the S-100 bus. With one simple

modification,

IMSAI

front

panel may be used

run, stop, single step, and observe address and

data.

Note

that

EXAMINE

and

DEPOSIT

functions

will

not

work.

16-pin

socket

directly

connected

the

8086's Address/Data lines

provided,

with

pins

1-16

wired

ADO-AD15, respectively. This

may be used

with

IMSAI

front

lJanel

observe 8data bits

time.

Only pins 9

through

the

IMSAI

front

panel

connector

are used. To observe the

low

(even) data byte, plug pins 16

into

pins 1

the

socket

(the cable should extend

downward).

For

the high

(odd)

data byte,

pins 9

the cable plug

into

pins 16

the

socket

(the cable should extend

upward).

When

the

processor

does a·double

gulp·--two

8-bit

reads when 16 bits are

needed--both

halves

the

word

will

be displayed sequentially on the high data lines.

The

modification

the

IMSAI

front

panel

allow

single stepping

made on the

front

the

circuit

board,

near the edge

connector

below

address

switch

Cut

the trace

connector

pi n39

(this

trace

comes

degrees). Install ajumper

from

this

trace

the

trace

connected

44 (the

trace

the

right).

will

be necessary

scrape away a

portion

the solder mask

from

both

traces.

This change

will

not

affect

operation

the

front

panel

with

8080 CPUs.

- 8 -

3.0

S-100

Connector

Layout

NAME

NAHE

/...•

Volts

2+16

Volts

-16

Volts

XRDY

555

757

858

sXIRQ*

959

A19

SIXIN*

A20

NMI*

A21

A22

A23

A18

A16

A17

PHANTOM*

SDSB*

MWRITE

CDSB*

ADSB*

RDY

DODSB*

INT*

HOLD

pSTVAL*

RESET*

pHLDA

pSYNC

pWAIT

pWR*

pDBIN

A15

A12

DOl

Al3

DOO

A14

AIO

All

D04

D02

D05

D03

D06

D07

DI2

DI4

DI3

DI5

DI7

DI6

44 sMl

DI1

sOUT

DIO

sINP

sINTA

sMEHR

sWO*

sHLTA

SPEED

CLOCK

POC*

GROUND

100

GROUND

- 9 -

4.0

A.C.

Characteristics

The

symbol

the

left

column

the

form

TAYBZ

where

Tmeans a

timing

measurement;

A,B

are

abbreviations

signal

Y,Z

are

abbreviations

signal

means

the

time

from

the

first

signal

second

signal

reaches

the

second

level.

The

following

abbreviations

are

Signal

Names

A -

Address

bus

C -

Clock

(~)

D -

pDBIN

I -

Data-in

H -

HWRITE

o -

Data-out

R -

Ready

(RDY

/XRDY

/SIXfN*)

S -

Status

bus

V -

pSTVAL*

W -

pWR*

Y - pSync

names;

levels.

reaching

the

first

level

until

the

used:

Signal

Levels

H -

High

L -

Low

V -

Valid

X -

Invalid

For

example,

TRVCH

means "Time

from

Ready becomes

Valid

until

Clock

goes

High."

Times

specified

are

nanoseconds,

either

minimum

maximum

appropriate

for

worst-case

specification.

Times

listed

are

for

a 4

MHz

clock,

for

an 8

MHz

clock,

and

for

comparison

purposes,

the

requirements

the

proposed

S-100

standard

411Hz. The maximum

clock

speed

covered

the

standard

MHz.

-10 -

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