SeaLevel ACB-V Manual de usuario

ACB-V

User Manual | 4012

Contents

CONTENTS...........................................................................................................................................................2

BEFORE YOU GET STARTED ...............................................................................................................................3

INSTALLATION .................................................................................................................................................... 4

CARD SETUP ........................................................................................................................................................5

TECHNICAL DESCRIPTION ................................................................................................................................. 9

PROGRAMMING THE ACB-V CONTROL/STATUS PORT.................................................................................10

INSTALLATION ..................................................................................................................................................13

ENVIRONMENTAL SPECIFICATIONS ...............................................................................................................14

APPENDIX A – TROUBLESHOOTING................................................................................................................15

APPENDIX B – SAFETY INSTRUCTIONS..........................................................................................................16

APPENDIX G – COMPLIANCE NOTICES ..........................................................................................................17

WARRANTY ........................................................................................................................................................18

................................................................................................................................................................................

Before You Get Started

What’s Included

The ACB-V is shipped with the following items. If any of these items are missing or damaged, please contact

Sealevel for replacement.

•ACB-V (P/N: 4012)

Advisory Conventions

Warning

The highest level of importance used to stress a condition where damage could result to the

product, or the user could suffer serious injury.

Important

The middle level of importance used to highlight information that might not seem obvious or a

situation that could cause the product to fail.

Note

The lowest level of importance used to provide background information, additional tips, or other

non-critical facts that will not affect the use of the product.

Installation

The ACB-V can be installed in any of the PC expansion slots. Remove the PC case, remove the blank metal

slot cover, and insert the board. Replace the screw, replace the cover, and the installation is complete.

Be sure to set the address and jumper options before installation.

Card Setup

Address Selection

The ACB-V occupies 8 consecutive I/O locations. A dip-switch (SW1) is used to set the base address for

these locations. Be careful when selecting the base address as some selections conflict with existing PC

ports. The following table shows several examples that usually do not cause a conflict.

Address

Binary

Switch Settings

A9-----------A0

238-23F

1000111XXX

Off

280-287

1010000XXX

Off

2A0-2A7

1010100XXX

Off

2E8-2EF

1011101XXX

Off

300-307

1100000XXX

Off

328-32F

1100101XXX

Off

3E8-3EF

1111101XXX

Off

Typically COM1:=3F8H; COM2:=2F8H; COM3:=3E8H; COM4:=2E8H.

Figure 1

The following illustration shows the correlation between the dip-switch setting and the address bits used

to determine the base address. In the example below, the address 300 Hex through 307 Hex is selected.

300 Hex =11 0000 0XXX in binary representation.

Note that setting the switch "On" or "Closed" corresponds to a "0" in the address, while leaving it "Off" or

"Open" corresponds to a "1".

The relative I/O address of the 8530 SCC registers is as follows:

Base+0 Channel A Data Port

• Base+1 Channel A Control Port

• Base+2 Channel B Data Port

• Base+3 Channel B Control Port

• Base+4 Board Control / Status Port

Where "Base" is the selected board base address.

OFF

1 2

Figure 2

Option Selection

The ACB-V contains several jumper straps which must be set for proper operation.

E2- This header selects DMA mode of operation. Channel A of the SCC can operate in either half-duplex or

full duplex DMA mode. Full duplex DMA can transmit and receive data simultaneously. Half-duplex DMA

can transmit or receive data, but not in both directions simultaneously. Both channels A and B can be used

in half-duplex mode. The various options for E1 and E2 jumper settings are as follows:

If DMA is not used, remove all of the jumpers on E1 and E2. Refer to Page 3 for the most

common DMA settings.

1 DACK 1 Or 3 Acknowledge For Two Channel Mode

2 Two Channel A/B Mode A3B1

3 Two Channel A/B Mode A1B3

4 On = Ch. A Only / Off = Ch. B Only

5 DACK 3 DMA Acknowledge Channel 3

6 DACK 1 DMA Acknowledge Channel 1

Figure 3

2 3 4 5 6 7 8

1 A or B Ch 3

2 A only Ch 3

3 A or B Ch 1

4 A only Ch 1

5 B Enable

6 A Full Duplex

7 DMA Always Enabled

8 Control Port Bit 7 Enables DMA (See Below)

Figure 4 Header E1 DMA Mode Options

Header E2 DMA Mode Options

23456

E1: Positions 7 and 8 enable or disable DMA operation. A jumper “ON” position 7 permanently enables the

DMA tri-state drivers. A jumper “ON” position 8 places DMA under software control via the DMA enable

control port bit (located at Base+4). Removing the jumper disables the drivers, and no DMA can be

performed.

The power on reset signal disables the DMA enable signal. A jumer placed in position 7 of E1 will

override any software uses of the DMA enable / disable status port bit.

Commonly Used DMA Jumper Options

Option

Program 8530

No DMA Channel A or B.

None

N/A

Single Channel DMA (Half Duplex Only):

Ch.A DMA Ch.1 Half Duplex Ch.B

No DMA.

4,6

WAIT/REQ A

Ch.A DMA Ch.3 Half Duplex Ch.B

No DMA.

4,5

WAIT/REQ A

Ch.B DMA Ch.1 Half Duplex Ch.A

No DMA.

6 Only

3,5

WAIT/REQ B

Ch.B DMA Ch.3 Half Duplex Ch.A

No DMA

5 Only

1,5

WAIT/REQ B

Both DMA Channels (1 and 3) Selected:

Ch.A DMA Ch.1 Half Duplex Ch.B

DMA Ch.3 Half Duplex

1,3

1,4,5

WAIT/REQ A

WAIT/REQ B

Ch.A DMA Ch.3 Half Duplex Ch.B

DMA Ch.1 Half Duplex

1,2

2,3,5

WAIT/REQ A

WAIT/REQ B

Full Duplex Channel A with Both DMA Channels 1 and 3:

Ch.A DMA Ch.1 Receive Data Ch.A

DMA Ch.3 Transmit Data

1,4

1,4,6

WAIT/REQ A

DTR/REQ A

Ch.A DMA Ch.3 Receive Data Ch.A

DMA Ch.1 Transmit Data

1,4

2,3,6

WAIT/REQ A

DTR/REQ A

Channel B of the ACB-V does not support full duplex DMA.

Figure 5

E3: This header selects the interrupt request line for the port. The diagram below shows IRQ 5 selected in

a shared configuration. If no interrupt is desired, remove the jumper.

Selects IRQ2

Selects IRQ3

Selects IRQ4

Selects IRQ5

Selects Normal (1 IRQ Per Board) IRQ Mode

Selects "Multi-IRQ" (Shared) IRQ Mode

Figure 6

The factory default setting for E3 is: “5” and “M”.

EPROM Usage

The EPROM socket on the ACB-V is provided for convenience only and does not affect the communication

functions of the board in any way. If the EPROM is not used, the socket should be disabled (dip-switch SW2

position 5 off). The following table shows several EPROM base address examples.

The EPROM is a 27128 device occupying 16K bytes of memory at or above C800 Hex to be recognized by

the PC on boot up. Address lines A19, and A18 are always a binary 1, forcing a selection of C000 Hex or

greater.

Address Address Lines Switch position setting (SW1)

A17

A16

A15

A14

C000-C3FF

C400-C7FF

Off

C800-C9FF

Off

D000-D3FF

Off

D400-D7FF

Off

D800-DBFF

Off

E000-E3FF

Off

E400-E7FF

Off

Figure 7 EPROM Address Examples

Some “AT” class machines cannot use addressee E000 and above.

Figure 8 illustrates the correlation between the dip-switch setting and the address bits used to determine

the base address.

Switch position 5 enables and disables the EPROM socket. The default setting is with the EPROM socket

disabled. The ACB-V will be shipped with the dip-switch in the configuration illustrated in Figure 8.

Figure 8 Dip-Switch Illustration (SW2)

1 2 3 4

OFF

Technical Description

Advanced Communications Board IV Specifications

The Sealevel ACB-V advanced communications board provides the PC with two high speed sync/async

ports. The ACB-V can be used in a variety of sophisticated communication applications such as SDLC,

HDLC, X.25, and high speed async. Features included on the card are:

•Two channels of sync / async communications using 8530 chip

•DMA supports data rate greater than 1 million bps (bits per second)

•Selectable Port Address, IRQ level (2,3,4,5), and DMA channel (1 or 3)

•CCITT V.35 interface with full modem control supports TD, RD, RTS, CTS, DSR, DCD, DTR,

TXC, RXC signals

•Jumper options for clock source

•Software programmable baud rate

•High Speed Enhanced Serial Communications Controller (85C30,85230) compatible

The ACB-V utilizes the ZILOG 8530 Serial Communications Controller (SCC). This chip features

programmable baud rate, data format and interrupt control, as well as DMA control. Refer to the 8530

technical manual, the ZILOG SCC user’s manual, and the ACB Developers Toolkit Diskette for details on

programming the SCC.

CCITT V.35

The Comite Consultatif Internationale de Telegraphie et Telephonie also known as the CCITT is the agency

that set the V.35 standard. V.35 specifies an electrical, mechanical, and physical interface that is used

extensively by high-speed digital carriers such as AT&T Dataphone Digital Service (DDS). CCITT V.35 is an

international standard that is often referred to as "Data Transmission at 48 Kbps Using 60 - 108 KHz Group-

Band Circuits." CCITT V.35 electrical characteristics are a combination of unbalanced voltage and balanced

current mode signals. Data and clock signals are balanced current mode circuits. These circuits typically

have voltage levels from 0.5 Volts to -0.5 Volts (1 Volt differential). The modem control signals are

unbalanced signals and are compatible with RS-232. The physical connector is a 34 pin connector that

supports 24 data, clock, and control signals. The physical connector is defined in the ISO-2593 standard.

CCITT V.35 is implemented with both DTE and DCE interfaces, the ACB-V is implemented using the DTE

interface. The ACB-V will not generate a clock signal without a modification. because the CCITT V.35

specification does not specify a clock output signal for a V.35 DTE. If an output clock signal is required for

the V.35 interface, please call Sealevel Systems Technical Support . The ACB-V is compatible with CCITT

V.36 and V.37.

Programming the ACB-V Control/Status Port

The ACB-V occupies eight Input/Output (I/O) addresses. The first four are used by the SCC chip, while the

fifth address (Base+4) is the address of the on-board Control/Status Port. This port is used to set the Data

Terminal Ready (DTR) signal, to enable or disable DMA under software control, and to monitor the Data Set

Ready (DSR) input signals from the modem. The following table lists bit positions of the Control/ Status

port.

Bit:

Output Port Bits

Input Port Bits

DTR A 1=On, 0=Off

DSR A

1=On, 0=Off

DTR B 1=On, 0=Off

DSR B

1=On, 0=Off

Not Used

1=On, 0=Off

Not Used

1=On, 0=Off

Not Used

1=On, 0=Off

Not Used

1=On, 0=Off

Not Used

1=On, 0=Off

DMA Enable 1=On, 0=Off

Not Used

1=On, 0=Off

Figure 11

Software Examples

Function

Program Bits

Turn On CH.A DTR

Write Out Base+4,XXXX XXX1

Turn On CH.B DTR

Write Out Base+4,XXXX XX1X

Turn Off CH.A DTR

Write Out Base+4,XXXX XXX0

Turn Off CH.B DTR

Write Out Base+4,XXXX XX0X

Enable DMA Drivers

Write Out Base+4,1XXX XXXX

Disable DMA Drivers

Write Out Base+4,0XXX XXXX

Test CH.A DSR

Read In Base+4, Mask=0000 0001

Test CH.B DSR

Read In Base+4, Mask=0000 0010

Figure 12

Assembly language programs should not do two successive I/O accesses, which violates the

8530 SCC recovery time specification. Please refer to the 8530 technical reference for more

details.

Correct: Incorrect:

MOV DX,3E0H MOV DX,3E0H

OUT DX,AL OUT DX,AL

JMP $+2 OUT DX,AL

OUT DX,AL

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