SDS 925 Manual de usuario

Price:

$3.50

SDS

925/930/9300

INPUT/OUTPUT

INTERFACE

DESIGN MANUAL

SDS

900561 A

December 1965

SCIENTIFIC

DATA

SYSTEMS. 1649 Seventeenth

Street.

Santa Monica, Calif

.•

(213) 871-0960

Scientific Data Systems, Inc.

ii

PREFACE

This manual describes

the

Input/Output

System

available

with

the

SDS

925/930/9300

Computers with special emphasis

placed

on

the

available

interface

signals and

con-

nections. The

interface

described represents

the

junction between

the

Input/Output

communication channels and

the

external equipment. In

the

case of System Priority

Interrupts

it

describes

the

junction requirements between external interrupt input

sig-

nals

and

the

Priority Interrupt Chassis.

Detailed

descriptions of

each

available

interface

connection

is

stressed to

facilitate

the

efficient

design

or

implementation

of

the

coupling

electronics

required to

connect

external units to

the

computeri therefore,

the

reader should

be

familiar with

the

following publications

pertinent

to his

specific

appl ication.

SDS

925 Reference Manual

SDS

925 Theory of Operation Manual

SD

S 930 Reference ManuaI

SDS

930 Theory of Operation Manuai

SDS

9300 Reference Manual

SDS

9300 Theory

of

Operation

ManuaI

Models 93200/93202

TMCC

Model 91602 Data Multiplex Channel -

DMC

Model 91500 Memory

Interface

Connection

900099A

900633

9000648

900066

900050C

900570

900685

900828

900808

CONTENTS

Section

Page

Section

Page

INPUT/OUTPUT

SYSTEMS

1-1

Output

Termination

3-8

Interlace

Operation

3-8

General

Description 1-1

Direct

Access Communication

Time-Mu

Itiplexed

Communication

Channel

(DACC)

3-9

Channel

(TMCC) 1-1 Memory

Interface

Connection

(MIC)

3-12

POT, PIN Instructions

1-3

Data

Multiplexing

System (DMS)

3-12

Single-Bit

Input/Output

1-3

Data

Subchannel (DSC)

3-14

Mu Itiple Access to Memory

1-3

DSC-I

Operation

3-14

Direct

Access Communication DSC-II

Operation

3-14

Channe

I (DACC)

1-3

Input/Output

Usi

ng ExternaI

Data

Multiplexing

System (DMS)

1-3

Interlace

3-19

Data

Multiplex

Channel

(DMC)

1-3

Word

Increment

Function

3-19

Data

Subchannels (DSC)

1-3

Priority

Interrupt

Operation

3-20

External

Interlace

(EIN)

1-4

Interrupt

States

3-20

Memory

Interface

Connection

(MIC)

1-4

Interface

Signals 3-21

Priority Interrupt

1-4

II INPUT/OUTPUT INSTRUCTIONS 2-1 IV INTERFACE CIRCUIT

AND

CABLE

REQUIREMENTS 4-1

General

2-1

Energize

Output

M (EOM) 2-1

General

4-1

Buffer Control E

OM

2-1

Cable

Requirements 4-1

Internal

Control EOM 2-1

Connector

Requirements

4-1

Input/Output

Control EOM 2-1

Circuit

Requirements

4-1

System Control EOM 2-1

Output

Circuits

4-1

E

OM

Interface

Signa

Is

2-2

low-Speed

Outputs,

Type

01

4-1

Energize

Output

to

Direct

Access

low-Speed

Outputs,

Circuit

Type

02

4-3

Channels

(EOD)

2-2

High-Speed

Outputs,

Circuit

EOD

Interface

Si

goo

Is

2-2

Type

03

4-3

Parallel

Output

(POT)

2-3

Input

Circuits

4-4

POT

Interface

Si

gna

Is

2-3

Input

Circuit

Type

11

4-4

Parallel

Input

(PIN)

2-4

Input

Circuit

Type

12

4-5

Interface

Signals

2-4

Input

Circuit

Type

13

4-5

SDS 925

Specia

I

I/O

Operations

2-5

Input

Circuit

Type 14

4-5

Input

(BPI)

2-5

Drivi ng Input Signals

4-5

Output

(BPO)

2-5

Hi

gh-

Speed Inputs

4-6

Skip If Signal

Not

Set (SKS)

2-6

Formulae for lRC

Circuits

4-6

S

KS

Interface

Si

gna

Is

2-6

Standard

Cables

4-6

III INPUT/OUTPUT CHANNEL V INTERFACE

CONNECTOR

DESCRIPTION 3-1 DESCRIPTIONS

5-1

General

3-1

General

5-1

Time

Multiplexed

Communication TMCC

Interface

Connectors

5-1

Channel

(TMCC) 3-1 DACC

Interface

Connectors

5-21

Interlace

3-1 MIC

Interface

Connector

5-36

Input

3-1 DSC-I

Interface

Connectors 5-41

Input

Clock

Characteristics

3-5

DSC-II

Interface

Connectors

5-41

Input

Termination

3-5

System Priority

Interrupt

Interface

Output

Timing

3-5

Connectors

5-50

iii

Figures

Tables

Page Page

1-1

925/930/9300

General Computer 1-1 TMCC Models 1-1

Configuration

1-2

3-1 Unit Address Codes

3-3

2-1 Signals

Generated

by EOM Instructions

2-2

3-2

Interlace

Extended Mode Termina I

3-8

2-2

Signals

Generated

by EOD Instruction

2-2

3-3

DACC Terminal Functions Extended Mode 3-11

2-3

Signals

Generated

by

POT

Instruction

2-4

3-4

Unit Address Codes 3-11

2-4

Signals

Generated

by PIN Instruction

2-5

3-5

EOM/POT/SKS

Function Combinations

3-15

2-5

Signals

Generated

by 925

BPI

Instruction

2-6

3-6

Relationship

of

DMC Functions

and

2-6

Signals

Generated

by 925 BPO Instruction

2-7

Interface

Signals

3-17

2-7

Signa

Is

Generated

by

S

KS

Instruction

2-7

4-1 R/L Network Values

4-2

3-1 TMCC Simplified Block Diagram

3-2

4-2

Standard Cables Assemblies

4-6

3-2

Input Timing

Characteristics

5-1 TMCC W Buffer

Interface

Connectors

Asynchronous Mode

3-4

(AU)0N~A)

5-1

3-3

Input

Clock

Timing Diagram

3-6

5-2

TMCC W Buffer

Interface

Connector

3-4

TMCC Input Timing, Synchronous

Clock

3-7

(DISCW)

5-3

3-5

TMCC

Output

Timing, Synchronous Clock

3-7

5-3

TMCC W Buffer

Interface

Connectors (PIN)

5-5

3-6

DACC Timing, Asynchronous Input Mode

3-9

5-4

TMCC W Buffer

Interface

Connectors (POT)

5-7

3-7

DACC Timing, Synchronous Input Mode

3-9

5-5

TMCC W Buffer

Interface

Connector

3-8

DACC Timing, High-Speed Synchronous

(MAGW)

5-9

Input Mode

3-10

5-6

TMCC W Buffer

Interface

Connectors

(WRDW)

5-11

3-9

MIC Input Timing ( Zo True)

3-13

5-7

TMCC Y Buffer

Interface

Connectors

3-10

MIC

Output

Timing ( Zo False)

3-13

(AUXY-B)

5-13

3-11 Timing Diagram DSC-II Terminating

5-8

TMCC Y Buffer

Interface

Connector (DISCY)

5-15

Input/Output

with External Address

3-16

5-9

TMCC Y Buffer

Interface

Connector

(MA

GY)

5-17

3-12

Timing Diagram DSC-II Terminating

5-10

TMCC Y Buffer

Interface

Connectors

(WRDY)

5-19

Input/Output

with ExternarAddress

3-18

5-~

11

DACC

Interface

Connectors (AUX) 5-21

3-13

Timing Diagram DSC-II

Input/Output

5-12

DACC

Interface

Connector

(DISC)

5-23

Using Internal

Interlace

3-19

5-13

DACC

Interface

Connector

(MA

G)

5-25

3-14

Timing Diagram DSC-II Word

5-14

DACC

Interface

Connectors (PIN)

5-27

Increment Function

3-20

5-15

DACC

Interface

Connectors (POT)

5-29

3-15

System Priority Interrupt Configuration 3-21

5-16

DACC

Interface

Connectors

(WRD)

5-31

4-1 Typical AND

Gate

4-1

5-17

DACC

Interface

Connectors (ZIN)

5-33

4-2

Cable

Driver AK53 4-1

5-18

DACC

Interface

Connectors (ZOUT)

5-35

4-3

Typical

Interface

Connection, Low-Speed

5-19

MIC

Interface

Connectors

(MCTL)

5-36

Outputs, Type

01

4-2

5-20

MIC

Interface

Connectors (MIN)

5-38

4-4

Cable

Driver AK57

Output

4-3

5-21 MIC

Interface

Connectors (MOUT)

5-39

4-5

Low-Speed Output,

Circuit

Type

02

4-3

5-22

DSC-II

(W)

Interface

Connector

4-6

Cab

Ie

Driver A

K56

4-3

(DSC

Control) 5-41

4-7

High-Speed

Output,

Circuit

Type

03

4-3

5-23

DSC-II

(X)

Interface

Connector

4-8

Cable

Driver AK56 Loading

4-4

(DSC Control)

5-44

4-9

Interface

Inverter,

NB50

4-4

5-24

DSC-II

(W)

Interface

Connector

(DSC

In)

5-46

4-10

Input Signal

Gating

4-4

5-25

DSC-II

(X)

Interface

Connector

(DSC

In)

5-48

4-11 Input

Circuit

Type

13

4-5

5-26

DSC-II

(Wand

X)

Interface

Connectors

4-12

Interrupt Inputs Type

14

4-5

(DSC

Out)

5-49

4-13

Low-Speed Input Cab

Ie

Driver AX14

4-5

5-27

ChanneI Priority Interrupt, Arming

4-14

AX14 Driving Low-Speed Input

4-5

Interrupt 5-51

4-15

High-Speed Input Connection

4-6

5-28

Directory Priority Interrupt

5-52

iv

SECTION

I

INPUT/OUTPUT

SYSTEMS

GENERAL

DESCRIPTION

The standard

I/O

system provided with a

II

SDS

925/930/

9300 Computers allows operations with a

II

standard

SDS

peripheral equipment as

well

as with

special

purpose

devices.

Alternate

I/O

system options

are

available

which

are

of

particular

use for systems handling multiple sources

of

data

and

for systems requiring very high

data

acquisition

rates.

Two

separate

paths

along

which

I/O

data

can

flow

to

and

from memory

are

provided for

the

SDS

925/930/9300

Computers. Figure 1-1 shows

input/output

memory paths

and

systems configuration.

The

first path is the normal path

that

exists

between

memory and

the

central

processor;

the

second path exists between memory

and

the

I/O

control

units

via

a

Multiple

Access to Memory unit (MAM).

Advantages of

the

multiple

access

to memory

feature

are:

I/O

memory accessing without loss of computation time;

higher

data

transfer rates;

and

program simplification.

Although

all

I/O

channels

avai

lable with

the

multiple

access

to

memory option

are

available

to

the

SDS

925, this

computer treats

all

input

and

output

operations on a priority

time multiplexed basis only

since

the

SDS

925 can have no

more

than

one memory bank.

The first path of

data

flow

between

memory and

central

processor uses

the

following methods

of

I/O

information

transfer:

a.

Time

Multiplexed

Communication Channels (TMCC)

b. Parallel Input (PIN)

c.

Parallel

Output

(POT)

d. Single-Bit

Input/Output

The second path of

data

flow

between

memory and

I/O

control units

and

devices

uses

the

following methods of

transfer:

a.

Data

Multiplexing

System (DMS)

b.

Direct

Access Communication Manuals (DACC)

c.

Memory

Interface

Connection

(MIC)

All second path to memory systems communicate with

memory through a

Multiple

Access to Memory unit (MAM).

Two

or more

separate

memory banks

are

a prerequisite for

taking

full

advantage

of the multiple access to memory

option.

TIME-MULTIPLEXED

COMMUNICATION

CHANNEL

(TICC)

The basic

925/930/9300

configuration includes one TMCC

for

6-bit

character

input/output.

This

TMCC

is

referred to

as the W

channel

in

the

925/930

and

as the A channel in

the 9300. The TMCC

is

capable

of

controlling

I/O

devices

such as

typewriter,

paper

tape,

card,

magnetic

tape,

and

line printers on a time multiplexed basis. A computer may

have

from

one

to four TMCC's

connected

to

it. Additional

channels

are

designated Y

(B

on 9300),

C,

and

D.

The

basic model number

is

93200. Model numbers for

additional

channels and optional features

are

listed in

table

1-1.

Any

6-bit

TMCC

can

be

expanded

to

12 bits by

adding

the

Model 93201 option

or

to

24 bits by

addition

of

the

Model

93202 option. With

the

12-

and/or

24-bit

options

character

size

is

controlled

by

the

external

device.

The

24-bit

buffer

can

handle

either

6,

12, or 24

bit

characters

according

to

device

requirements.

Table

1-1.

TMCC Models

Used on

Model Description Channel

93200

6-bit

characters,

without

interlace,

W(A), C

single

channel

91210

Interlace

option for 93200

93201

12-bit

character

extension option

for 93200

93202

24-b

it

character

extension option

for 93200

93221

6-bit

characters,

without

interlace,

W(A}plus

two

channe

Is

Y(B}

or

91210

Interlace

option for

either

channel C plus D

of

93221

93201

12-bit

character

extension option

for

either

channel of 93221

93202

24-b

it

character

extension option

for

either

channel

of 93221

The memory

interlace

feature

may be

added

to

any

TMCC

by

adding the Model 91210 Memory

Interlace

Control unit.

This optional

feature

is

useful for

input/output

of large

blocks of

data

at

high transfer rates.

Jhe

memory

interlace

automatically

controls the transfer of

data

words for its

associated

channel

buffer by maintaining a current memory

address and word

count

during

input/output

operations.

1-1

I

'"

"

to

C

(i

I

-0

'"

01

~

W

o

~

w

o

G)

(1)

:J

(1)

a

()

o

3

"0

c

m

....

()

o

:J

:;,:

to

C

9-

o·

:J

~

Priority Control

00000000000000

< Single-Bit

I/O

EOM/EOD -

SKS-----:.

< Direct Parallel

I/O

POT/PIN

~

< Block Parallel

Transfer-------

@

~--~x--~

d5:~D::

(1)

Part

of

Standard

925/930/9300

0) Available

on

930/9300 only

--

®

EIN

Option

EIN

Option

Memory

Bank

First Path

to Memory

Second Path to Memory

0000[>

Priority Control

~

.....

IIIIIIII~

Syste~

Interrupt

EIN

Option

.---

....

,0

Priority

DODD

[>Control

The

interlace

also

controls terminal functions

and

provides

end-of-record

and

zero

word

count

interrupts.

Channels C

and

D (and B on the 9300) must always have

interlace

installed

since

no computer instructions

exist

in

the 9300 to a Ilow use of these

channels

without

interlace.

Any TMCC

operating

with

interlace

has priority over the

centra

I processor for memory

access

with

channel

priority

in

the

order:

Channels D,

C,

Y(B), W(A).

The maximum

data

transfer

rate

of a TMCC is one word

every

two memory

cyc

les or

280,000

words per second.

POT

,PIN

INSTRUCTIONS

The

925/930/9300

Computers

include

two instructions,

parallel

output

and

parallel

input, which permit

the

transfer

of words

between

core memory

and

external

equipment

with-

out

interfering

with

the

operation

of

other

I/O

channels.

The

execution

of

either

the

POT

or

PIN instruction causes a

signal

to

be

sent

to

the

external

device

requesting it to

acknowledge

when it

is

ready

to

receive

or transmit the

data

word.

After

the

request signal

is

sent,

the

computer sus-

pends

operations

until

the

acknowledge

signal

is

received.

The maxi

mum

data

transfer

rate

for

PI

N operations

is

114,000

words

per

second

(five

cycles

for

each

word transfer). The

maximum

data

transfer

rate

for POT

operations

is

143,000

words

per

second

(four

cycles

for

each

word transfer).

The Block POT

and

Block PIN (BPO/BPI) operations

which

are

unique

to

the

SDS

925 transfer words

at

a maximum

rate

of

570,

000 words

per

second (one

cyc

Ie for

each

word

transfer).

SINGLE-BIT

INPUT/oUTPUT

The two instructions, Energize

Output

M (EOM)

and

Skip If

Signal

Not

Set

(SKS) when

operating

in the systel1l mode

are

used

to

provide

single-bit

input/output

transmission.

Execu-

tion

of

an

EOM

operating

in

the

system mode causes a

sig-

nal

to

be

transmitted to

one

of a possible

8,

192 signal

des-

tinations.

The maximum signal transfer

rate

is

570,000

pulses

per

second. Execution

of

an

S

KS

in the

specia

I

system

test

mode permits the computer to

test

the

condition

of

anyone

of

a possible

8,

192

input

lines. The maximum

test

rate

depends on

the

condition of

the

line:

286,000

per

second if program does not skip

190,000

per

second

if

program does skip

the

MULTIPLE

ACCESS

TO

MEMORY

The

Mu

Itiple

Access to Memory

feature

(MAM) provides

the

necessary modules on both main frame

and

memory

to

permit

memories

to

be

accessed

via

the

second

memory

path.

Trans-

fer of

one

word

over

this path in

either

direction

requires

one

memory

cycle.

If the computer has two or more memory

banks,

the

main frame

can

communicate

with

one memory

via

the

first

path

to

one memory

while

some peripheral

device

is

communicating with

the

other

memory

via

the

second path

without

interference

or loss

of

computation time.

The

Multiple

Access to Memory

feature

(MAM)

is

required

for the

attachment

of

Direct

Access Communication Channels

(DACC), Data

Multiplex

Channels

(DMC), or Memory

Interface

Connections (MIC).

DIRECT

ACCESS

COMMUNICATION

CHANNEL

(DACC)

The

Direct

Access Communication

Channel,

Model 92220,

is

avai

lab

Ie

for systems

requiring

high-speed

input/output

simultaneous with computation.

Up

to

four

DACCs

may be

connected

to

the

core memory through

the

Multiple

Access

to

Memory (MAM), Model 92990 (Model 92992 for

the

925)

for

each

memory modu Ie. The four

channels

are

designated

E,

F,

G,

and

H.

Simultaneous

access

to

memory wi II

occur

if

the

channel

and

computer

are

addressing

separate

memory

modules.

If

simultaneous

access

to

the

same memory module

is

required,

priority

is

in

the

order:

MAM, TMCC, Central

Processor.

The maximum

data

transfer

rate

in

the

high-speed

mode

is

one

word

every

memory

cycle,

or

approximately

570,000

words

per

second.

The DACC communicates

with

external

equipment

by means

of

a

bidirectional

24-bit

register

using

6-,

8-,

12-,

or

24-bit

characters

plus a

parity

bit.

Character

size

is

con-

trolled

by

the

external

device.

DATA

MULTIPLEXING

SYSTEM

(OMS)

The

data

multiplex system consists of two basic

elements:

a.

The Data

Multiplex

Channel

(DMC) for com-

municating

with

several

data

sources/destinations,

and

for

synchronizing

I/O

operations

with

memory.

b.

One

or

more Data Subchannels (DSC) for

interfac-

ing

between

periphera

I devices or systems

and

the

DMC.

Data

Multiplex

Channel

(DMC}

The

data

multiplex

channel

is

equipped

with

an

internal

interlace

feature

that

allows

specified

input/output

tables

in memory to be processed

by

the

addressed peripheral

device

via

the

associated

subchannel.

Data

Subchannels

(OSC)

Two

standard subchannels

are

available.

Model 91711

DSC-I provides

character

oriented

operations,

and

Model

91712 DSC-lI

is

full-word

(24-bit)

oriented.

Up

to

128

DSCs

can

be

attached

to

the

DMC.

Two

or more

DSCs

can

be

active

simultaneously using

an

internal

priority

arrange-

ment

to

determine which subchannel

can

transmit

to

the

DMC

at

any

given time.

1-3

External

Interlace

(EIN)

An ExternaI I

nter

lace

ModeI 91800

can

be

attached

to

any

DSC. The EIN controls

the

transmissions of

the

DSC

at

a

maximum rate

of

one

vV'ord

per memory

cycle.

Maximum

data

transfer

rate

using

internal

interlace

is

190,000

words

per

second.

With

external

interlace

the

maximum transfer

rate

is

increased

to

570,000

words

per

second.

MEMORY

INTERFACE

CONNECTION

(MIC)

The Memory

Interface

Connection,

Model 91500, is

avail-

able

for

direct

access

to

core

memory under control or

external

equipment.

A

prerequisite

for MIC is a

Multiple

Access

to

Memory (MAM) ModeI 92990 for

each

memory

module. The 925 Computer requires

the

Mu Itiple Access

to

Memory (Model 92992). The

external

device

must provide

signals

to

the

MIC

indicating

when

an

I/O

operation

is

to

take

place,

it

must

specify

the

memory address,

and

must

indicate

whether

the

function

is

an

input

or

an

output.

The MIC

checks

parity

on inputs

and

generates

parity

on

outputs.

Data

transfer

is

in

the

form

of

24-bit

words plus

odd

parity.

The maximum

data

transfer

rate

is

570,000

words per second.

1-4

PRIORITY

INTERRUPT

The

925/930/9300

Computers

are

capab

Ie

of

program

sequence

interruption

by signals

generated

by communica-

tion channels, special features, and external equipment,

on a

priority

basis. Each

925/930/9300

includes

a

basic

interrupt

unit

that

provides two interrupts (four for 9300)

with 22 more

avai

lable

(20 more for 9300) for use

with

optional

I/O

channels

and

special

features.

Up

to

896

system

priority

interrupts for

genera

I purpose use

are

avai

1-

able

for

external

systems

by

adding

Model 93280

interrupt

control units. Each Model 93280

can

control

up

to

32

priority

interrupts. The Model 93280 does not

include

the

interrupts. However, interrupts may

be

added

to

the

Model

93280

by

connecting

a Model

93290

priority

interrupt.

Each

Model 93290

contains

two

levels

of

priority

interrupti

thus

16 ·Model

93290's

(32

levels

of

interrupt)

can

be

added

to

each

interrupt

control

un

it.

An arming

feature

may

be

added

to

the

interrupt

control

unit

by

adding

a Model 92280 arming

option

to

provide

arming for

the

first

16

levels

of

interrupt

on a Model 93280.

Arming for

the

second

16

levels of interrupts

can

be

added

by

adding

a Model 92290 arming

option

to

the

Model

92280.

SECTION

II

INPUT/OUTPUT

INSTRUCTIONS

GENERAL

Five

instructions

control

input/output

operations

of

the

925/930/9300

Computers. These

are:

a.

Energize

Output

M

(E

OM)

b.

Energize

Output

to

Direct

Access

Channels

(EOD)

c.

Parallel

Input (POT)

d.

Parallel

Input (PIN)

e.

Skip

If

Signal

Not

Set (SKS)

In

addition

to

the

five instructions

above

the

SDS

925

pro-

vides for a b lock transfer

variation

of

the

POT

and

operations,

BPO

and

BPI.

In this manual emphasis

is

placed

on

interface

information

and

the

reader

should

refer

to

the

925,

930,

or

9300

reference

manual for a

detailed

descrip-

tion

of

each

instruction.

ENERGIZE

OUTPUT

M

(EOM)

The EOM

instruction

is used primarily

to

control

input/

output

through

all

channels

except

the

DACC. This

instruc-

tion

operates

in four basic modes

that

are

program se

lect-

able

by

the

setting

of two bits

(Cl0,

Cll)

within

the EOM

instruction

format:

Cl0

Cll

Function

0 0 Buffer Control

0

Input/Output

Control

0

Interna

I Control

System ControI

One

computer

cyc

Ie

(1. 75

I-Isec)

is required to

execute

an

EOM

instruction

in

any

mode. During

the

execution

of

the

EOM

instruction

the

control

register

(C

register)

of

the

computer

is

held

stable.

At

that

time this

24-bit

register

(CO-C23)

contains

the

EOM

instruction

word. The

output

of

this

register

is

avai

lable

to

the

TMCC and

to

the

external

units.

If

an

interrupt

occurs during

the

execution

of

any

EOM in

any

mode,

it

wi II

not

be

acknow

ledged

unti I

the

execution

of

the

instruction following

the

E

OM

is

complete.

Buffer

Control

EO

M

The EOM

instruction

operating

in

the

buffer control mode

prepares

the

channel

and

device

for

data

transmissions

or

other

peripheral

activities.

The

channel

to

be

used, the

peripheral

unit

on

that

channel,

the

operation

to

be

performed, and the type

of

character

format to be used,

are

all

detailed

within

the

EOM in this mode. The use

of

BCD

or

binary

data

transmission,

the

allowance

or

not

of

a

leader

(as

in

paper

tape

functions),

and

the

direction

of

operation

(in

magnetic

tape

functions)

are

all

detailed

to

the

channel

and

its

connected

periphera

I unit. Execution of such

an

EOM

connects

the

specified

peripheral

unit to

the

channel.

Interlace

can

also

be

alerted

with

EOM in this mode.

Internal

Control

EOM

The EOM in the

internal

control

mode is used to

enable

and

disable

the

interrupt

system, to

prepare

the

system for

the

selective

arming

and

disarming of the system

interrupt

levels,

to

reset

the

overflow, and

to

record

exponent

overflow.

The EOM,

internal

control mode, does not

apply

directly

to

I/O

control,

and

therefore,

it

does

not

generate

interface

signa

Is.

Input/Output

Control

EOM

The EOM in

the

input/output

mode is used

to

direct

periph-

eral

devices

to

perform

nontransmitting

operations

such as

rewind

magnetic

tape

and

upspace

the

printer.

Selection

of

certain

channel

operations such as

interrupt

response and

the

input/output

terminal

function

desired

is

made

with

this

EOM. It

is

also

used

to

alert

peripheral

devices

that

a

Parallel

Input (PIN)

or

Parallel

Output

(POT) instruction

is

to

follow. The C

register

outputs,

C18 through

C23,

must

be

decoded

by

the

external

unit

during

this instruction

to

avoid

interference

with

standard

device

control.

System

Control

EOM

The EOM in

the

system control mode

can

control

internal

equipment

by

providing

a

single-bit

output

of

approximately

1.4

I-Isec

to

any

add~essable

connector.

The system control

mode

can

be

divided

into two

distinct

submodes

by

gating

bit

9 with bits

10

and

11

of

the

system mode EOM.

Cl

C9

Cl0

Cll

x

X

o E

OM

System ControI (Externa

I)

EOM System Control

(Internal)

The

internal

system control submode provides control for

standard

I/O

systems such as the DMS,

data

communications,

and

display. The

external

system control submode provides

a means of

controlling

special

non-standard

I/O

equipment

or

systems.

Cl

must always

be

included

in

the

decoding

circuitrY.!1nce

the

term

Cl

separates

the

Data

Mu

Itiplex

System (C1) from

other

I/O

buffer units (C1).

2-1

EO

M I

nterface

Signals

Four signals

generated

by the

EOM

instruction

are

available

at

the

TMCC

I/O

connectors. See figure

2-1.

These

sig-

nals, when

true,

indicate

that

the contents

of

the C register

(CO-C23)

are

to be transferred to external equipment. The

four signals

are:

a.

~

b.

~

(Buffer Control Mode)

c.

0;)

(I/o

Control Mode)

d.

GV

(System Control Mode)

The signals,

@,

Q,

and®,

indicate

to the

external

system which EOM mode

is

currently

being

executed.

The

Eom

signal

is

generated

by all EOM instructions,

and

is

true during periods

T7

-

Tr

(1. 4 flsec). The

Eom

pulse

is

also

generated

during

the

FILL

operation.

The

Eom

signal

is

inhibited during

the

second EOM instruction

of

the

interlace

loading

sequence

and

during

time-share

operations.

The

signals,~

and~are

derived

from

the

EOM

instruction

according

to configuration

of

bits

Cl,

Cl0,

and

Cll.

Signal

W(A)

Y(B)

Cl

Cl0

Cll

Cl

Cl0

Cll

Time

----t

..

~

TMCC

C,

D

Cl

C10

Cll

Cl

C10

Cll

r----EOM Instruction

~

I (1.75

~ec)

I

18171615141312111°IRIPI

~

L

~

L

@ through

E=:C

Register

Stable

-~-~

I

@ !

900561A.21 1

Figure 2-1. Signals

Generated

by EOM Instructions

2-2

The terms C17 and C17 must be used by the external system

to distinguish between TMCC-W(A)

and

TMC-Y(B),

and,

similarly, between TMCC-C

and

TMCC-D.

C

17

TMCC-W(A)

or

TMCC-C

C17 TMCC-Y(B)

or

TMCC-D

The ® signal

is

derived from

the

EOM instruction

{external system submode}

according

to bits

C9,

C

10

and

C11. ® =

C9

ClO

Cl1

If

the

contents

of

the

C

C~)er

(CO,

C',

C2,

C12-C23)

are

decoded

during the

Sys

signal,

up

to

32,768

single-

bit outputs

can

be

obtained.

ENERGIZE

OUTPUT

TO

DIRECT

ACCESS

CHANNELS

(EOO)

The

EO

D instruction

is

used to control

input/output

through

the DACC. This instruction

is

similar

to

the

EOM instruc-

tion

and

performs analogous functions for the

direct

access

channels

E,

F,

G,

and

H.

EOO

Interface

Signals

Four signais

generated

by

the

roo instruction

are

available

at

the

DACC

I/O

connectors. See figure

2-2.

These

sig-

nals, when

true,

indicate

that

the contents

of

the C register

Time

----t.~

r----

EOO Instruction

....

1

/ (1.75

~ec)

Signal

/8

171615/4/3/211101

RIP/

l®

~ L

@

~

L

cg

,

@throughE:-C

Register

Stable==--

,@

I

I 900561A.22

Figure 2-2. Signals

Generated

by

EO

D Instruction

SDS 925 Manual de usuario

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