Renesas V850E/D 3 Series Manual de usuario

User Manual

www.renesas.com

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

Jun 27, 2012

R01UH0129ED0701, Rev. 7.01

V850E/Dx3 - DJ3/DL3

32-bit Single-Chip Microcontroller

Hardware

μPD70F3421

μPD70F3422

μPD70F3423

μPD70F3424

μPD70F3425

μPD70F3426A

μPD70F3427

R01UH0129ED0701 Rev. 7.01 2

User Manual

Notice

1. All information included in this document is current as of the date this document is issued. Such

information, however, is subject to change without any prior notice. Before purchasing or using any

Renesas Electronics products listed herein, please confirm the latest product information with a

Renesas Electronics sales office. Also, please pay regular and careful attention to additional and

different information to be disclosed by Renesas Electronics such as that disclosed through our

website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other

intellectual property rights of third parties by or arising from the use of Renesas Electronics

products or technical information described in this document. No license, express, implied or

otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of

Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product,

whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to

illustrate the operation of semiconductor products and application examples. You are fully

responsible for the incorporation of these circuits, software, and information in the design of your

equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third

parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the

applicable export control laws and regulations and follow the procedures required by such laws and

regulations. You should not use Renesas Electronics products or the technology described in this

document for any purpose relating to military applications or use by the military, including but not

limited to the development of weapons of mass destruction. Renesas Electronics products and

technology may not be used for or incorporated into any products or systems whose manufacture,

use, or sale is prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this

document, but Renesas Electronics does not warrant that such information is error free. Renesas

Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors

in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades:

“Standard”, “High Quality”, and “Specific”. The recommended applications for each Renesas

Electronics product depends on the product’s quality grade, as indicated below. You must check the

quality grade of each Renesas Electronics product before using it in a particular application. You

may not use any Renesas Electronics product for any application categorized as “Specific” without

the prior written consent of Renesas Electronics. Further, you may not use any Renesas

Electronics product for any application for which it is not intended without the prior written consent

of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or

losses incurred by you or third parties arising from the use of any Renesas Electronics product for

an application categorized as “Specific” or for which the product is not intended where you have

failed to obtain the prior written consent of Renesas Electronics.

R01UH0129ED0701 Rev. 7.01 3

User Manual

The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly

specified in a Renesas Electronics data sheets or data books, etc.

8. You should use the Renesas Electronics products described in this document within the range

specified by Renesas Electronics, especially with respect to the maximum rating, operating supply

voltage range, movement power voltage range, heat radiation characteristics, installation and other

product characteristics. Renesas Electronics shall have no liability for malfunctions or damages

arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products,

semiconductor products have specific characteristics such as the occurrence of failure at a certain

rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not

subject to radiation resistance design. Please be sure to implement safety measures to guard them

against the possibility of physical injury, and injury or damage caused by fire in the event of the

failure of a Renesas Electronics product, such as safety design for hardware and software including

but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for

aging degradation or any other appropriate measures. Because the evaluation of microcomputer

software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as

the environmental compatibility of each Renesas Electronics product. Please use Renesas

Electronics products in compliance with all applicable laws and regulations that regulate the

inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.

Renesas Electronics assumes no liability for damages or losses occurring as a result of your

noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior

written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the

information contained in this document or Renesas Electronics products, or if you have any other

inquiries.

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measurement equipment; audio and visual equipment; home electronic

appliances; machine tools; personal electronic equipment; and industrial robots.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control

systems; anti-disaster systems; anti-crime systems; safety equipment; and

medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control

systems; medical equipment or systems for life support (e.g. artificial life support

devices or systems), surgical implantations, or healthcare intervention (e.g.

excision, etc.), and any other applications or purposes that pose a direct threat to

human life.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics

Corporation and also includes its majority-owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or

for Renesas Electronics.

R01UH0129ED0701 Rev. 7.01 4

User Manual

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage

notes on the products covered by this manual, refer to the relevant sections of the manual. If the

descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the

manual differ from each other, the description in the body of the manual takes precedence.

1. Handling of unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

– The input pins of CMOS products are generally in the high-impedance state. In operation with an

unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI,

an associated shoot-through current flows internally, and malfunctions occur due to the false

recognition of the pin state as an input signal become possible. Unused pins should be handled

as described under Handling of Unused Pins in the manual.

2. Processing at power-on

The state of the product is undefined at the moment when power is supplied.

– The states of internal circuits in the LSI are indeterminate and the states of register settings and

pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states of pins

are not guaranteed from the moment when power is supplied until the reset process is

completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function

are not guaranteed from the moment when power is supplied until the power reaches the level at

which resetting has been specified.

3. Prohibition of access to reserved addresses

Access to reserved addresses is prohibited.

– The reserved addresses are provided for the possible future expansion of functions. Do not

access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock signal

has stabilized.

– When the clock signal is generated with an external resonator (or from an external oscillator)

during a reset, ensure that the reset line is only released after full stabilization of the clock

signal. Moreover, when switching to a clock signal produced with an external resonator (or by an

external oscillator) while program execution is in progress, wait until the target clock signal is

stable.

5. Differences between products

Before changing from one product to another, i.e. to one with a different part number, confirm that

the change will not lead to problems.

– The characteristics of MPU/MCU in the same group but having different part numbers may differ

because of the differences in internal memory capacity and layout pattern. When changing to

products of different part numbers, implement a system-evaluation test for each of the products.

R01UH0129ED0701 Rev. 7.01 5

User Manual

Preface

Readers This manual is intended for users who want to understand the functions of the

concerned microcontrollers.

Purpose This manual presents the hardware manual for the concerned microcontrollers.

Organization This system specification describes the following sections:

• Pin function

• CPU function

• Internal peripheral function

Module instances These microcontrollers may contain several instances of a dedicated module.

In general the different instances of such modules are identified by the index

“n”, where “n” counts from 0 to the number of instances minus one.

Legend Symbols and notation are used as follows:

• Weight in data notation: Left is high order column,

right is low order column

• Active low notation: xxx (pin or signal name is

over-scored) or

/xxx (slash before signal name)

• Memory map address: High order at high stage

and low order at low stage

Note Additional remark or tip

Caution Item deserving extra attention

Numeric notation: • Binary: xxxx or xxxB

• Decimal: xxxx

• Hexadecimal: xxxxHor 0x xxxx

Prefixes representing powers of 2 (address space, memory capacity):

• K (kilo): 210 = 1024

• M (mega): 220 = 10242= 1,048,576

• G (giga): 230 = 10243=

1,073,741,824

Diagrams Block diagrams do not necessarily show the exact wiring in hardware but the

functional structure.

Timing diagrams are for functional explanation purposes only, without any

relevance to the real hardware implementation.

Further Information For further information see http://www.renesas.eu/.

R01UH0129ED0701 Rev. 7.01 6

User Manual

Table of Contents

Chapter 1 Introduction............................................. 18

1.1 General ............................................................ 18

1.2 Features Summary .................................................. 19

1.3 Product Series Overview ............................................. 23

1.4 Description......................................................... 24

1.5 Ordering Information................................................. 28

Chapter 2 Pin Functions........................................... 29

2.1 Overview........................................................... 29

2.1.1 Description .................................................. 30

2.1.2 Terms ...................................................... 34

2.1.3 Noise elimination.............................................. 34

2.2 Port Group Configuration Registers .................................... 35

2.2.1 Overview .................................................... 35

2.2.2 Pin function configuration ....................................... 36

2.2.3 Pin data input/output ........................................... 41

2.2.4 Configuration of electrical characteristics ........................... 43

2.2.5 Alternative input selection ....................................... 46

2.3 Port Types Diagrams................................................. 51

2.4 Port Group Configuration ............................................. 56

2.4.1 Port group configuration lists..................................... 57

2.4.2 Alphabetic pin function list....................................... 64

2.4.3 External memory interface of µPD70F3427 ......................... 70

2.4.4 Port group 0 ................................................. 71

2.4.5 Port group 1 ................................................. 73

2.4.6 Port group 2 ................................................. 74

2.4.7 Port group 3 ................................................. 76

2.4.8 Port group 4 ................................................. 78

2.4.9 Port group 5 ................................................. 80

2.4.10 Port group 6 ................................................. 82

2.4.11 Port group 7 ................................................. 84

2.4.12 Port group 8 ................................................. 86

2.4.13 Port group 9 ................................................. 88

2.4.14 Port group 10 ................................................ 90

2.4.15 Port group 11 ................................................ 92

2.4.16 Port group 12 ................................................ 94

2.4.17 Port group 13 ................................................ 95

2.4.18 Port group 14 (µPD70F3427 only) ................................ 96

2.5 Noise Elimination ................................................... 97

2.5.1 Analog filtered inputs........................................... 97

2.5.2 Digitally filtered inputs .......................................... 97

2.6 Pin Functions in Reset and Power Save Modes.......................... 101

2.7 Recommended Connection of unused Pins ............................. 102

2.8 Package Pins Assignment ........................................... 103

2.8.1 µPD70F3421, µPD70F3422, µPD70F3423......................... 103

2.8.2 µPD70F3424, µPD70F3425, µPD70F3426A ....................... 104

2.8.3 µPD70F3427 ................................................ 105

R01UH0129ED0701 Rev. 7.01 7

User Manual

Table of Contents

Chapter 3 CPU System Functions............................... 106

3.1 Overview.......................................................... 106

3.1.1 Description ................................................. 107

3.2 CPU Register Set ................................................... 108

3.2.1 General purpose registers (r0 to r31) ............................. 109

3.2.2 System register set ........................................... 110

3.3 Operation Modes ................................................... 116

3.3.1 Normal operation mode........................................ 116

3.3.2 Flash programming mode ...................................... 116

3.4 Address Space..................................................... 117

3.4.1 CPU address space and physical address space.................... 117

3.4.2 Program and data space....................................... 119

3.5 Memory........................................................... 121

3.5.1 Memory areas ............................................... 121

3.5.2 Fixed peripheral I/O area ...................................... 124

3.5.3 Recommended use of data address space......................... 125

3.6 Write Protected Registers............................................ 126

3.7 Instructions and Data Access Times................................... 128

Chapter 4 Clock Generator....................................... 130

4.1 Overview.......................................................... 130

4.1.1 Description ................................................. 131

4.1.2 Clock monitors .............................................. 133

4.1.3 Power save modes overview ................................... 134

4.1.4 Start conditions .............................................. 135

4.1.5 Start-up guideline ............................................ 136

4.2 Clock Generator Registers ........................................... 137

4.2.1 General clock generator registers ................................ 139

4.2.2 SSCG control registers ........................................ 146

4.2.3 Control registers for peripheral clocks............................. 152

4.2.4 Control registers for power save modes ........................... 160

4.2.5 Clock monitor registers ........................................ 166

4.3 Power Save Modes ................................................. 171

4.3.1 Power save modes description .................................. 171

4.3.2 Clock Generator state transitions ................................ 181

4.3.3 Power save mode activation .................................... 183

4.3.4 CPU operation after power save mode release ..................... 186

4.4 Clock Generator Operation........................................... 189

4.4.1 Internal and sub oscillator operation .............................. 189

4.4.2 Watch Timer and Watch Calibration Timer clocks ................... 189

4.4.3 Clock output FOUTCLK ....................................... 189

4.4.4 Default clock generator setup ................................... 190

4.4.5 Operation of the Clock Monitors ................................. 191

Chapter 5 Interrupt Controller (INTC) ........................... 193

5.1 Features .......................................................... 193

5.2 Non-Maskable Interrupts ............................................ 202

5.2.1 Operation .................................................. 205

5.2.2 Restore .................................................... 206

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Table of Contents

5.2.3 Non-maskable interrupt status flag (NP) ........................... 207

5.2.4 NMI0 control ................................................ 207

5.3 Maskable Interrupts................................................. 208

5.3.1 Operation .................................................. 208

5.3.2 Restore .................................................... 210

5.3.3 Priorities of maskable interrupts ................................. 210

5.3.4 xxIC - Maskable interrupts control register ......................... 215

5.3.5 IMR0 to IMR6 - Interrupt mask registers ........................... 219

5.3.6 ISPR - In-service priority register ................................ 222

5.3.7 Maskable interrupt status flag (ID) ............................... 222

5.3.8 External maskable interrupts.................................... 223

5.3.9 Software interrupts ........................................... 223

5.4 Edge and Level Detection Configuration ............................... 224

5.5 Software Exception ................................................. 226

5.5.1 Operation .................................................. 226

5.5.2 Restore .................................................... 227

5.5.3 Exception status flag (EP)...................................... 228

5.6 Exception Trap..................................................... 229

5.6.1 Illegal opcode definition........................................ 229

5.6.2 Debug trap ................................................. 231

5.7 Multiple Interrupt Processing Control .................................. 233

5.8 Interrupt Response Time ............................................ 235

5.9 Periods in Which Interrupts Are Not Acknowledged ...................... 236

Chapter 6 Flash Memory ......................................... 237

6.1 Overview.......................................................... 238

6.1.1 Flash memory address assignment .............................. 239

6.1.2 Flash memory erasure and rewrite ............................... 241

6.1.3 Flash memory programming .................................... 242

6.1.4 Boot block swapping .......................................... 242

6.2 Flash Self-Programming ............................................. 243

6.2.1 Flash self-programming registers ................................ 243

6.2.2 Interrupt handling during flash self-programming .................... 245

6.3 Flash Programming via N-Wire ....................................... 246

6.4 Flash Programming with Flash Programmer ............................ 247

6.4.1 Programming environment ..................................... 247

6.4.2 Communication mode ......................................... 248

6.4.3 Pin connection............................................... 251

6.4.4 Programming method ......................................... 254

Chapter 7 Bus and Memory Control (BCU, MEMC)............ 258

7.1 Overview.......................................................... 258

7.2 Description........................................................ 259

7.2.1 Memory banks and chip select signals ............................ 261

7.2.2 Chips select priority control ..................................... 264

7.2.3 Peripheral I/O area ........................................... 264

7.2.4 NPB access timing ........................................... 266

7.2.5 Bus properties ............................................... 266

7.2.6 Boundary operation conditions .................................. 267

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Table of Contents

7.2.7 Initialization for access to external devices ......................... 268

7.2.8 External bus mute function ..................................... 268

7.3 Registers ......................................................... 269

7.3.1 BCU registers ............................................... 270

7.3.2 Memory controller registers (µPD70F3427 only)..................... 279

7.4 Page ROM Controller ............................................... 288

7.5 Configuration of Memory Access ..................................... 290

7.5.1 Endian format ............................................... 290

7.5.2 Wait function ................................................ 290

7.5.3 Idle state insertion ............................................ 292

7.6 External Devices Interface Timing ..................................... 292

7.6.1 Writing to external devices ..................................... 293

7.6.2 Reading from external devices .................................. 295

7.6.3 Read-write operation on external devices.......................... 297

7.6.4 Write-read operation on external devices .......................... 298

7.7 Page ROM Access Timing ........................................... 299

7.7.1 Half word/word access with 8-bit bus or word access with 16-bit bus..... 300

7.7.2 Byte access with 8-bit bus or byte/half word access with 16-bit bus...... 302

7.8 Data Access Order ................................................. 304

7.8.1 Access to 8-bit data busses .................................... 304

7.8.2 Access to 16-bit data busses ................................... 310

Chapter 8 DMA Controller (DMAC) .............................. 316

8.1 Features .......................................................... 316

8.2 Peripheral and CPU Clock Settings .................................... 318

8.3 DMAC Registers ................................................... 320

8.3.1 DMA Source address registers .................................. 320

8.3.2 DMA destination address registers ............................... 322

8.3.3 DBCn - DMA transfer count registers ............................. 324

8.3.4 DADCn - DMA addressing control registers ........................ 325

8.3.5 DCHCn - DMA channel control registers .......................... 327

8.3.6 DRST - DMA restart register .................................... 328

8.3.7 DTFRn - DMA trigger source select register ........................ 329

8.4 DMA setup and retrigger............................................. 332

8.4.1 DMA initial setup (status after system reset)........................ 332

8.4.2 DMA Retrigger .............................................. 332

8.5 Automatic Restart Function .......................................... 333

8.6 Transfer Type...................................................... 334

8.7 Transfer Object .................................................... 334

8.8 DMA Channel Priorities.............................................. 335

8.9 DMA Transfer Start Factors .......................................... 335

8.10 Forcible Interruption ................................................ 336

8.11 Forcible Termination ................................................ 337

8.12 DMA Transfer Completion ........................................... 338

8.13 Transfer Mode ..................................................... 339

8.13.1 Single transfer mode .......................................... 339

8.13.2 Block transfer mode .......................................... 341

8.14 Cautions .......................................................... 342

8.14.1 Simultaneous program execution and DMA transfer with internal RAM . . . 342

8.14.2 MLE Bit Usage .............................................. 343

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Table of Contents

Chapter 9 ROM Correction Function (ROMC).................. 344

9.1 Overview.......................................................... 344

9.2 “Data Replacement” ROM Correction Unit .............................. 345

9.2.1 Features ................................................... 345

9.2.2 “Data Replacement” ROM correction operation ..................... 346

9.2.3 Setting of ROM correction addresses ............................. 349

9.2.4 “Data Replacement” ROM correction registers ...................... 351

9.3 “DBTRAP” ROM Correction Unit ...................................... 356

9.3.1 “DBTRAP” ROM correction operation ............................. 357

9.3.2 “DBTRAP” ROM correction registers ............................. 358

Chapter 10 Code Protection and Security ....................... 362

10.1 Overview.......................................................... 362

10.2 Boot ROM ......................................................... 362

10.3 N-Wire Debug Interface.............................................. 362

10.4 Flash Writer and Self-Programming Protection .......................... 364

10.5 Additional Firmware Functions ....................................... 365

10.5.1 ID-field..................................................... 365

10.5.2 Checksum calculation ......................................... 365

10.5.3 Variable reset vector .......................................... 365

Chapter 11 16-bit Timer/Event Counter P (TMP) ................ 366

11.1 Overview.......................................................... 366

11.2 Functions ......................................................... 367

11.3 Configuration ...................................................... 367

11.4 TMP Registers ..................................................... 369

11.5 Operation ......................................................... 380

11.5.1 Interval timer mode (TPnMD2 to TPnMD0 = 000).................... 380

11.5.2 External event count mode (TPnMD2 to TPnMD0 = 001).............. 388

11.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010) ....... 396

11.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 = 011) ............ 407

11.5.5 PWM output mode (TPnMD2 to TPnMD0 = 100) .................... 414

11.5.6 Free-running timer mode (TPnMD2 to TPnMD0 = 101) ............... 423

11.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) ......... 440

11.5.8 Timer output operations ....................................... 446

11.6 Operating Precautions .............................................. 447

11.6.1 Capture operation in pulse width measurement and free-running mode . . 447

11.6.2 Count jitter for PCLK4 to PCLK7 count clocks ...................... 447

Chapter 12 16-bit Interval Timer Z (TMZ)......................... 448

12.1 Overview.......................................................... 448

12.1.1 Description ................................................. 449

12.1.2 Principle of operation ......................................... 449

12.2 TMZ Registers ..................................................... 450

12.3 Timing............................................................ 455

12.3.1 Steady operation ............................................. 455

12.3.2 Timer start and stop .......................................... 456

Chapter 13 16-bit Multi-Purpose Timer G (TMG) ................ 458

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